SITNGOW HSV14 El A || waite microetectronics WF2M32-XXX5 2Mx32 5V FLASH MODULE, SMD 5962-97531 (pending) FEATURES M@ Access Time of 90, 120, 150ns M@ Packaging: 66-pin, PGA Type, 1.185 inch square, Hermetic Ceramic HIP (Package 401). 68 lead, 40mm Low Profile COFP (Package 502), 3.5mm (0.140 inch) height. e 68 lead, Hermetic COFP (G2U), 22.4mm (0.880 inch) square (Package 510) 3.56mm (0.140 inch) height. Designed to fit JEDEC 68 lead 0.990 COFJ footprint (Fig. 3) M@ Sector Architecture 32 equal size sectors of 64KBytes per each 2Mx8 chip e Any combination of sectors can be erased. Also supports full chip erase. H Minimum 100,000 Write/Erase Cycles Minimum {0C to 70) WM Organized as 2Mx32 PRELIMINARY* @ Commercial, Industrial, and Military Temperature Ranges @ 5 Volt Read and Write. 5V + 10% Supply. M@ Low Power CMOS or erase cycle completion. M@ Supports reading or programming data to a sector not being erased. m@ RESET pin resets internal state machine to the read mode. @ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity * This data sheet describes a product under development, not fully characterized, and is subject to change without notice Note: Programming information available upon request. TOP VIEW 1 12 2a 34 45 56 Ovos Qwee Ovors vo2a OQ) vee v0312 Qvos OCs2 OQvors voesC) G84) vos) QOvoto Qend Ovo vo2s C) WEaC) Woe CO) Oar Ovon Ovo Av ) wO27 2) vor O Oates Caro Oe Az) a AO Oan Oas Oarz Azo) asl) a2) Qao Oa Owes AaC) AGL ABC) Oats Cveo Ovo7 ABC) West) 023) ! Ovoo cst OC1os wore) CS3C> vO22C) Ovo1 Cais COvos vor) @ND > wo | Qvoz Ovos Ovos wore) worse) vO20C) hi 22 33 44 55 66 FIG. 1 PIN CONFIGURATION FOR WF2M32-XHX5 PIN DESCRIPTION 1/00-31 | Data Inputs/Outputs Ao-20 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable Vec Power Supply GND Ground BLOCK DIAGRAM WE; CS, WE, CS, WEsCSs WEsCS, Ly ti ~ Hoot et +S Too IS pt aa } i 2M x8 | saaxe | 2Mx8 | 2M x8 i J) bE LL ce 8 al a 38 t HOs-7 {708-15 016-23 /O24-31 RESET internally tied to Vcc in the HIP package for this pin configuration. See Alternate Pin Configuration with RESET tied to pin 12 for system control of reset (Fig. 11, page 13) White Microelectronics Phoenix, AZ * (602) 437-1520 May 1997WF2M32-XXX5 Ww WHITE MICROELECTRONICS FIG.2 PIN CONFIGURATION FOR WF2M32-XG2UX5 TOP VIEW PIN DESCRIPTION (i eQa5 5 Q 1/00-31 | Data Inputs/Outputs BezgezxlB5eexze228 A mee ao 0-20 Address Inputs 9876 5 4 3 2 1 E8 67 66 65 64 63 62 61 ve {| 10 sol) vos WE1-4 Write Enables vor {]14 591) voir ne : vO2 (12 58[] Ot CSt-s Chip Selects wos 13 871] vors OE Gutput Enable vOa [] 14 56[] /O20 vOs [15 [} vQas Vec Power Supply vOe [] 16 I} vQze vOr [17 1 vO: . GND Ground Gno [118 Str The White 68 lead G2U COFP END woe 1119 fl woe fills the same fit and function as RESET Reset ee bot the JEDEC 68 lead COFY or 68 vor [22 0) woe PLCC. But the G2U has the TCE VOre Hee W028 and iead inspection advantage O13 [] 24 O29 vOrs (125 H Yose of the COFP form. BLOCK DIAGRAM vrs ize ] vost WE, CS, WE,C5 2 WE, CS, WE, 53, L_22 28 29 30 31 32 83 34 86 36 37 38 39 40 41 42 43 RESET t ri t : i aoneo p Et thi boob . , 2M x8 | 2M x & 2Mx8 | | 2M x8 | i | t | t ' /Oa-7 vOe+s VOis-23 HO24-31 8-67 White Microelectronics Phoenix, AZ (602) 437-1520 SJTNGOW HSV14 GaSJINGOW HSV14 re ed iar lle Xo)ateni-ce)\ Tes WF2M32-XXX5 ABSOLUTE MAXIMUM RATINGS CAPACITANCE (Ta = +25C) Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss Vt -2.0 to +7.0 Vv Parameter Symbol] Conditions Max | Unit Power Dissipation Pr 8 W OE capacitance Coe | Vin=OV,f=1.0MHz| 50 | pF Storage Temperature Tstg -65 to +125 Wes PSA Cwe | Vin = OV, f= 1.0 MHz 20 pF Short Circuit Output Current los 100 mA HIP (Alternate pinout) 50 CQFP G4T 50 CQFP G2U 20 RECOMMENDED DC OPERATING CONDITIONS G2 (Alternate pinout) 50 Parameter Symbol] Min | Typ Max | Unk CS1-4 capacitance Cos | ViN=OV,f=1.0MHz} 20 | pF Supply Voltage Vee 45 5.0 55 v Data I/O capacitance Cvo |Vwo=0V,f=1.0MHz|] 20 pF Ground Vss 0 0 0 v Address input capacitance Cao | Vw =O0V,f=1.0MHz| 50 pF Input High Voltage Vin 2.0 . Veo +0.5| V This parameter is guaranteed by design but not tested. Input Low Voltage Vit -0.5 : +0.8 V Operating Temperature (Mil.}| Ta -55 : +125 C Operating Temperature (Ind.)| Ta -40 . +85 C DC CHARACTERISTICS - CMOS COMPATIBLE (Vcc = 5.0V, Vss = OV, TA= -55C to +125C)} Parameter Symbol Conditions Min Max Unit Input Leakage Current tu Vcc = 5.5, Vin = GND to Vec 10 pA Output Leakage Current ILox32 Vcc = 5,5, Vin = GND to Vec 10 pA Vcc Active Current for Read (1) lect CS = Vii, OF = Vin, f = SMHz 160 mA Vcc Active Current for Program or Erase (2) Icc2 CS = Vu, OF = Vii 240 mA Vcc Standby Current lec3 Vee = 5.5, OS = Vin, f = SMHz, RESET = Vee + 0.3V 4.0 mA Output Low Voltage Vou. fo. = 12.0 mA, Vcc = 4.5 0.45 Output High Voltage Vou lon = -2.5 mA, Vcc = 4.5 0.85xVec Low Vcc Lock-Out Voltage Viko 3.2 42 NOTES: 1. The ice current listed includes both the OC operating current and the frequency dependent component (@ SMHz}. The frequency component typically is tess than 2mA/MHz, with OE at Vin. 2. Ice active while Embedded Aigorithm (program or erase} is in progress. 3. DC test conditions Vit = 0.3V, Vid = Vcc - 0.3V White Microelectronics * Phoenix, AZ * (602) 437-1520 8-68C4 WHITE MICROELECTRONICS Weller eet AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (Vcc = 5.0V, TA= -55C to +125C} Parameter Symbol -90 -120 7150 Unit Min Max Min Max Min Max Write Cycle Time tavay twe 90 120 150 ns Chip Select Setup Time teLWL tes Q 0 0 ns Write Enable Pulse Width twiwH twe 45 50 50 ns Address Setup Time tavwL tas 0 0 0 ns Data Setup Time tovwH tos 45 50 50 as Data Hold Time twHoX toH 0 0 0 ns Address Hold Time tweax {aH 45 50 50 ns Write Enable Pulse Width High fWHWL tweH 20 20 20 ns Duration of Byte Programming Operation fwewut 1 1 1 ms Sector Erase tWHWH2 15 15 15 sec Read Recovery Time before Write teHwe 0 Q Q ks Vcc Setup Time tyes 50 50 50 US Chip Programming Time 100 160 100 sec Output Enable Hold Time (1) tOEH 10 10 10 ns Chip Erase Time 480 480 480 sec RESET Pulse Width (2) tre 500 500 500 ns . For Toggle and Data Polling. . RESET internally tied to Vcc for the default pin configuration in the HIP package. nN AC CHARACTERISTICS ~ READ-ONLY OPERATIONS (Vcc = 5.0V, TA= -58C to +125C} Parameter Symbol 790 7120 215: Unit Min Max Min Max Min Max Read Cycle Time tavav trac 90 120 150 ns Address Access Time tavov tacc 90 120 150 ns Chip Select Access Time tecav tee 90 120 150 ns Output Enable to Output Valid tatav toe 40 50 55 ns Chip Seiect High to Output High Z (1) teHaz {or 20 30 35 ns Output Enable High to Output High Z (1) tGHOZ tor 20 30 35 ns Output Hold from Addresses, CS or OE Change, taxax tox 0 0 0 ns whichever is First RST Low to Read Mode (1,2) tReady 20 20 20 HS 1. Guaranteed by design, not tested. 2. RESET internally tied to Vcc for the default pin configuration in the HIP package. 8-69 White Microelectronics * Phoenix, AZ = (602) 437-1520 SJINGOW HSV14 GaSJTNGOW HSV14 7 WAV | waite microeLectRONics WF2M32-XXX5 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (Vcc = 5.0V, Vss = OV, Ta = -55C to +125C) Parameter Symbo! 90 120 7150 Unit Min Max Min Max Min Max Write Cycle Time tavav two 90 120 150 ns Write Enable Setup Time tWLeEt tws 0 0 0 ns Chip Select Pulse Width tELEH top 45 50 50 ns Address Setup Time tavet tas 0 0 0 ns Data Setup Time {oven tos 45 50 50 ns Data Hold Time teHDx tou 0 0 0 ns Address Hold Time teLax tay 45 50 50 ns Chip Select Pulse Width High teHeL tcPH 20 20 20 ns Duration of Byte Programming Operation twHwH1 1 1 1 ms Sector Erase Time twHWwH2 15 15 15 sec Read Recovery Time TGHEL 0 0 0 Ss Chip Programming Time 100 100 100 sec Chip Erase Time 480 480 480 sec Output Enable Hold Time (1) toeu 10 10 10 ns 1. For Taggle and Data Polling. FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT a | lop Parameter Typ Unit Current Source Input Pulse Levels Vi =0,Vin= 3.0] V Input Rise and Fall 5 ns Input and Output Reference Level 15 V D.U.T. Vz = 1.5V Output Timing Reference Level 1.5 V Co = 50 pf (Bipolar Supply) NOTES: Vz is programmable from -2V to +7V. lo. & lok programmable from 0 ta 16mA Tester Impedance 20=75Q. Vz is typically the midpoint of Vou and VoL. lo. & lon are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. $ Current Source FIG. 4 RESET TIMING DIAGRAM RESET tre -<__ {Ready __| White Microelectronics * Phoenix, AZ (602) 437-1520 8-70("4 WHITE MICROELECTRONICS WT SAN Kye 6s FIG. 5 AC WAVEFORMS FOR READ OPERATIONS J N S x t T. Fy 8 1 o >< : 7 ry t 7 T f a 1 1 I I ' 2 j $ 3 6 2 3 wo | 3 | Re 2 | 8 SZ < Y ; P| Ss y | N q txt s nw wn Ww uw 2 ; oO lo [= 3 3 oO < 8-71 White Microelectronics * Phoenix, AZ * (602) 437-1520 SJINGOW HSV14 GaSJINGOW HSV14 20 | Ww] WHITE MICROELECTRONICS MSA RY Oe ts WRITE/ERASE/PROGRAM i x OPERATION, WE CONTROLLED | 2 | af A | | rT | 4 ta oO uJ Ppt w 2 t & | t | i" i ie} i r ~ >< 3) 6 A f < is | _ aD = & s gs z t =< ma a | =z SS 2 | x |t - so i re g zr oY 4 4 2) 4 1 x Sse ' 3 St Blo z , oo 4 iB ie & 8 a w | naa a i i. ~ att ) | ~ I oo oN n wi w g IS Is Iz g 3 g 6 NOTES: 3 1. PA is the address of the memory location to be programmed. < 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. Dour is the output of the deta written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence White Microelectronics * Phoenix, AZ * (602) 437-1520 8-72WHITE MICROELECTRONICS WF2M32-XXX5 FIG. 7 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS 10H/30H | 55H i {aot YC seh Yar Yo PL NSN SN INS \~ tAH 2AAAH 5555H tas X i \_/ = A om) t Ay cs Vcc Addresses NOTE: 1. SA is the sector address for Sector Erase. 8-73 White Microelectronics * Phoenix, AZ + (602) 437-1520 STINGOW HSVT4 caSJTNGOW HSV14 20 | hI W WHITE MICROELECTRONICS WF2M32-XXX5 FIG. 8 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS J : = 2 x p~ aay a 2 KB S qa 3 ez "Qa om Ko > OS St > a. 2 S > = " Qo 9 { 4 a i Ot w 6 2 x 3 a to 2 See at x wi ( i x 2 t rs 9 Wi Data White Microelectronics Phoenix, AZ (602) 437-1520 8-74WHITE MICROELECTRONICS WF2M32-XXX5 FIG. 9 _ ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS Data Polling _/ Ly <e tAS-> two| | pa tGHEL I 5555H WE " | Addresses Cc Data 5.0V NOTES: PA represents the address of the memory location to be programmed. PO represents the data to be programmed at byte address. D? is the output of the complement of the data written to each chip. Dout is the output of the data written to the device. Figure indicates the last two bus cycles of a four bus cycle sequence. APwun- 8-75 White Microelectranics * Phoenix, AZ * (602) 437-1520 SJINGOW HSV14 caSITNGOW HSV14 e WwW WHITE MICROELECTRONICS WF2M32-XXX5 FIG. 10 ALTERNATE PIN CONFIGURATION FOR WF2M32!-XHX5 TOP VIEW 1 12 23 34 45 56 Ovos OCRESET Qvois vO2aC) veel) vos1C) | Quvos Ocse Ovo vo2s () CS4C} vos0C) Qvow Oano COvois vo2eC) NCC) Wo20C) Oa Ovou Ovore a7 C) vo27C) vox CO) Oare Cato Ode Azad) a> maO / Oa Oas Oar ncC) as) aat) ( Qao Oats Owe Ais) ABC) AB) | Oats Oves Quor As) Az0() O20) | Ovoo Osi OCueoe vos) C83C) vo2C) | QOvor Oats Oivos voi7C) GND) woe) | Qwoz Ovos Cvoe vos ) vars) vo20C) : ir 22 33 44 55 66 PIN DESCRIPTION BLOCK DIAGRAM C82 cs; | D! mi wo! m 4 as mim Ao-2 3 WOo7 108-15 1/00-31 | Data Inputs/Outputs Ao-20 Address Inputs WE Write Enable 81-4 Chip Selects OE Output Enable Vec Power Supply GND Ground RESET Reset c83 C84 VO16-23 WO24-31 ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5 - hes cA a Q ay Zgiw 2 PLexzzeVEssezsz2es Remsen 98 7 65 4 3 2 1 68 67 66 65 64 63 62 61 Oo [] 10 60[] vow vor 14 sof) vow voz {] 12 58l} vor vos []13 571] vOrs Oa (]14 561] O20 Os {]45 58[] vO2: Os {| 16 541] vO22 YO? [17 53]] vOea GND {] 18 521] GND vos [] 19 511] oes vg []20 501} O25 voOro {]21 491) vO26 von []22 48{] O27 Vvorz []23 47[] O28 Wor []24 46] vO29 Vora []25 45/] O30 vors [26 44[] VOs1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a SS QSEetePS22BweQStrssysstes FEeeexeae qlozegzz2zz2ea i+-__ 9.949"-----_ The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead COFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the COFP form. RESET es =~ cs WE OE Ag-20 vOo-7 PIN DESCRIPTION {/O0-31 | Data Inputs/Outputs Ao-20 Address Inputs WE Write Enable ts Chip Select OE Output Enable Vec Power Supply GND Ground RESET Reset VOe-15 W/O16-23 BLOCK DIAGRAM White Microelectronics * Phoenix, AZ (602) 437-1520WHITE MICROELECTRONICS MTA R renee ORDERING INFORMATION W F 2M32 X-XXXXX5 WF 2M X [* LEAD FINISH: Blank = Gold plated leads A = Solder dip leads Vep PROGRAMMING VOLTAGE 5=5V DEVICE GRADE: M= Military Screened -55C to +125C { = Industrial -40C to +85C C = Commercial 0 to +70C PACKAGE TYPE: H_ = Ceramic Hex in tine Package, HIP (Package 401) G2u = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) ACCESS TIME (ns) IMPROVEMENT MARK For HIP Package Biank = 4C5 and 4WE |= 48 and 1WE, RESET + For G2U Package Blank = 4CS and 4WE U=1CS and 1WE ORGANIZATION, 2M x 32 User configurable as 4M x 16 or 8Mx 8 (Except WF2M32U-XG2UX which is 32 bit wide only.) _________________ + Flash PROM WHITE MICROELECTRONICS DEVICE TYPE SECTOR SIZE SPEED PACKAGE SMD NO. 2M x 32 5V Flash Module 64KByte 150ns 66 pin HIP (H) 5962-97531 01HXX* 2M x 32 5V Flash Module 64KByte 120ns 66 pin HIP (H) 5962-97531 O2HXX* 2M x 32 5V Flash Module 64KByte 90ns 66 pin HIP (H)} 5962-97531 O3HXX* 2M x 32 5V Flash Module 64KByte 150ns 68 lead CQFP/J (G2U) 5962-97531 O1HXX* 2M x 32 5V Flash Module 64KByte 120ns 68 lead CQFP/J (G2U) 5962-97531 O2HXX* 2M x 32 5V Flash Module 64KByte 90ns 68 lead CQFP/J (G2U) 5962-97531 03HXX* * Pending 8-77 White Microslectranics * Phoenix, AZ * (602) 437-1520 SJINGOW HSV14 Ga