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unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

64Mx8, 32Mx16 DDR2 DRAM

per clock cycle

with CK

reduced strength options

64Mx8 (16Mx8x4 banks) IS43/46DR86400E

32Mx16 (8Mx16x4 banks) IS43/46DR16320E

x8: 60-ball BGA (8mm x 10.5mm)

5ns @CL=3 DDR2-400B

Commercial (0°C ≤ Tc ≤ 85°C)

Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)

ISSI's 512Mb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

Speed Grade -25D -3D

tCK @CL=6 2.5 —

Clock: CK and CK are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK and negative edge of CK.

Output (read) data is referenced to the crossings of CK and CK (both directions of

crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals

and device input buffers and output drivers. Taking CKE LOW provides Precharge

Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row

Active in any bank). CKE is synchronous for power down entry and exit, and for self

refresh entry. CKE is asynchronous for self refresh exit. After VREF has become

Chip Select: All commands are masked when CS is registered HIGH. CS provides for

external Rank selection on systems with multiple Ranks. CS is considered part of the

command code.

ODT Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal

to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM

signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

DM (x8) or

BA0 - BA1 Input

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or

Precharge command is being applied. Bank address also determines if the mode

register or one of the extended mode registers is to be accessed during a MRS or

EMRS command cycle.

A0 - A13 Input

Address Inputs: Provide the row address for Active commands and the column

address and Auto Precharge bit for Read/Write commands to select one location

out of the memory array in the respective bank. A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

DQ0 to DQ7 Data input/output VSS Ground for internal circuit

DQS, /DQS Differential data strobe VDDQ Supply voltage for DQ circuit

/CS Chip select VSSQ Ground for DQ circuit

/RAS, /CAS, /WE Command input VREF Input reference voltage

CKE Clock enable VDDL Supply voltage for DLL circuit

CK, /CK Differential clock input VSSDL Ground for DLL circuit

DM Write data mask NC No connection

RDQS, /RDQS Differential Redundant Data Strobe

LDQS, UDQS Differential data strobe VDDQ Supply voltage for DQ circuit

/LDQS, /UDQS

/CS Chip select VSSQ Ground for DQ circuit

/RAS, /CAS, /WE Command input VREF Input reference voltage

CKE Clock enable VDDL Supply voltage for DLL circuit

CK, /CK Differential clock input VSSDL Ground for DLL circuit

LDM to UDM Write data mask NC No connection

Absolute Maximum DC Ratings

AC & DC Recommended Operating Conditions

VDD Supply Voltage 1.7 1.8 1.9 V 1

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 5

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1, 5

VREF Input Reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2. 3

Symbol Parameter Rating Units Notes

PARAMETER/CONDITION SYMBOL MIN NOM MAX UNITS NOTES

Deviation of VM with respect to VDDQ/2 ΔVM - 6 + 6 % 1

Package Substrate Theta-ja

(Airflow = 0m/s)

Theta-ja

(Airflow = 1m/s)

60-ball BGA 4-layer 53.9 48.3 46.8 11.6 C/W

84-ball BGA 4-layer 52.0 46.6 45.1 11.5 C/W

VIH (ac) ac input logic HIGH VREF + 0.250 VDDQ + Vpeak VREF + 0.200 VDDQ + Vpeak V 1

VIL (ac) ac input logic LOW VSSQ - Vpeak VREF - 0.250 VSSQ - Vpeak VREF - 0.200 V 1

VREF Input reference voltage 0.5 x VDDQ V 1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

0.6 tAC(min) tAC(max) + 0.6 ns 17,

tAC(max)+1 tAC(min)+2 2.5 x tCK+

Average clock HIGH pulse width tCH(avg) 0.45 0.55 0.45 0.55 tCK(avg) 35,36

Average clock LOW pulse width tCL(avg) 0.45 0.55 0.45 0.55 tCK(avg) 35,36

DQS latching rising transitions to associated

clock edges tDQSS - 0.25 0.25 - 0.25 0.25 tCK(avg) 30

DQS falling edge to CK setup time tDSS 0.2 – 0.2 – tCK(avg) 30

DQS falling edge hold time from CK tDSH 0.2 – 0.2 – tCK(avg) 30

DQS input HIGH pulse width tDQSH 0.35 – 0.35 – tCK(avg)

DQS input LOW pulse width tDQSL 0.35 – 0.35 – tCK(avg)

Write preamble tWPRE 0.35 – 0.35 – tCK(avg)

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10

DQ and DM input setup time tDS(base) 50 – 50 – ps 6, 7, 8, 20,

28, 31

DQ and DM input hold time tDH(base) 175 – 125 – ps 6, 7, 8, 21,

28, 31

DQ and DM input pulse width for each input tDIPW 0.35 – 0.35 – tCK(avg)

DQ output access time from CK/CK tAC - 450 450 - 400 400 ps 40

DQS output access time from CK/CK tDQSCK - 400 400 - 350 350 ps 40

Data-out high-impedance time from CK/CK tHZ – tAC,max – tAC,

max ps 18,40

DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC,min tAC,max tAC,min tAC,

Min(

tCL(abs) )

Min(

tCL(abs) )

DQ hold skew factor tQHS – 340 – 300 ps 38

DQ/DQS output hold time from DQS tQH tHP - tQHS – tHP - tQHS – ps 39

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42

(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)

tCK(avg)

– ns 15

1. DDR2 SDRAM AC Timing Reference Load

Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing

parameters of the part. It is not intended to be either a precise representation of the typical system environment or

a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test

conditions (generally a coaxial transmission line terminated at the tester electronics).

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing

reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = +

500 mV (+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between

DQS and DQS for differential strobe.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in Figure "Slew Rate Test Load".

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method

by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships

relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing

methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via

the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure

proper operation.

DDR2-400/533 tDS/tDH derating with differential data strobe

Address

h) Issue a Mode Register Set command for DLL reset.

i) Issue a precharge all command.

j) Issue 2 or more auto-refresh commands.

k) Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without

resetting the DLL.)

l) At least 200 clocks after step h, execute OCD Calibration. This is done by EMRS to EMR(1) to set OCD Calibration

Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be

issued with other operating parameters of EMR(1).

m) The DDR2 SDRAM is now ready for normal operation.

driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode

Register Set (EMRS) command. Contents of the Mode Register or Extended Mode Registers can be altered by re-