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DS12887

Real Time Clock

DS12887

041697 1/17

FEATURES

•Drop–in replacement for IBM AT computer clock/

calendar

•Pin compatible with the MC146818B and DS1287

•Totally nonvolatile with over 10 years of operation in

the absence of power

•Self–contained subsystem includes lithium, quartz,

and support circuitry

•Counts seconds, minutes, hours, days, day of the

week, date, month, and year with leap year com-

pensation valid up to 2100

•Binary or BCD representation of time, calendar, and

alarm

•12– or 24–hour clock with AM and PM in 12–hour

mode

•Daylight Savings Time option

•Selectable between Motorola and Intel bus timing

•Multiplex bus for pin efficiency

•Interfaced with software as 128 RAM locations

– 14 bytes of clock and control registers

– 114 bytes of general purpose RAM

•Programmable square wave output signal

•Bus–compatible interrupt signals (IRQ)

•Three interrupts are separately software–maskable

and testable

– T ime–of–day alarm once/second to once/day

– Periodic rates from 122 µs to 500 ms

– End of clock update cycle

PIN ASSIGNMENT

24 PIN ENCAPSULATED PACKAGE

VCC

SQW

IRQ

RESET

R/W

MOT

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

PIN DESCRIPTION

AD0–AD7 – Multiplexed Address/Data Bus

NC – No Connection

MOT – Bus Type Selection

CS – Chip Select

AS – Address Strobe

R/W – Read/W rite Input

DS – Data Strobe

RESET – Reset Input

IRQ – Interrupt Request Output

SQW – Square W ave Output

VCC – +5 Volt Supply

GND – Ground

DESCRIPTION

The DS12887 Real Time Clock plus RAM is designed to

be a direct replacement for the DS1287. The DS12887

is identical in form, fit, and function to the DS1287, and

has an additional 64 bytes of general purpose RAM.

Access to this additional RAM space is determined by

the logic level presented on AD6 during the address por-

tion of an access cycle. A lithium energy source, quartz

crystal, and write–protection circuitry are contained

within a 24–pin dual in-line package. As such, the

DS12887 is a complete subsystem replacing 16 compo-

nents in a typical application. The functions include a

nonvolatile time–of–day clock, an alarm, a one-

hundred–year calendar, programmable interrupt,

square wave generator, and 114 bytes of nonvolatile

static RAM. The real time clock is distinctive in that

time–of–day and memory are maintained even in the

absence of power.

DS12887

041697 2/17

OPERATION

The block diagram in Figure 1 shows the pin connec-

tions with the major internal functions of the DS12887. The following paragraphs describe the function of each

pin.

BLOCK DIAGRAM DS12887 Figure 1

USER RAM

114 BYTES

CLOCK, CALENDAR,

AND ALARM RAM

REGISTERS A,B,C,D

SQUARE

WAVE OUT

PERIODIC INTERRUPT/SQUARE WAVE

SELECTOR

OSC.

POWER

SWITCH

AND

WRITE

PROTECT

BUS

INTERFACE

CLOCK/

CALENDAR

UPDATE

BCD/

BINARY

INCREMENT

SQW

IRQ

RESET

DOUBLE

BUFFERED

MOT

ADO–

AD7

R/W

VCC

POK

VCC

VBAT

864 64

POWER–DOWN/POWER–UP

CONSIDERATIONS

The Real Time Clock function will continue to operate

and all of the RAM, time, calendar, and alarm memory

locations remain nonvolatile regardless of the level of

the VCC input. When VCC is applied to the DS12887 and

reaches a level of greater than 4.25 volts, the device

becomes accessible after 200 ms, provided that the

oscillator is running and the oscillator countdown chain

is not in reset (see Register A). This time period allows

the system to stabilize after power is applied. When

VCC falls below 4.25 volts, the chip select input is inter-

nally forced to an inactive level regardless of the value of

CS at the input pin. The DS12887 is, therefore, write–

protected. When the DS12887 is in a write–protected

state, all inputs are ignored and all outputs are in a high

impedance state. When VCC falls below a level of

approximately 3 volts, the external VCC supply is

switched off and an internal lithium energy source sup-

plies power to the Real Time Clock and the RAM

memory.

DS12887

041697 3/17

SIGNAL DESCRIPTIONS

GND, VCC – DC power is provided to the device on

these pins. VCC is the +5 volt input. When 5 volts are

applied within normal limits, the device is fully accessi-

ble and data can be written and read. When VCC is

below 4.25 volts typical, reads and writes are inhibited.

However, the timekeeping function continues unaf-

fected by the lower input voltage. As VCC falls below 3

volts typical, the RAM and timekeeper are switched

over to an internal lithium energy source. The timekeep-

ing function maintains an accuracy of ±1 minute per

month at 25°C regardless of the voltage input on the

VCC pin.

MOT (Mode Select) – The MOT pin offers the flexibility

to choose between two bus types. When connected to

VCC, Motorola bus timing is selected. When connected

to GND or left disconnected, Intel bus timing is selected.

The pin has an internal pull-down resistance of approxi-

mately 20KΩ.

SQW (Square W ave Output) – The SQW pin can out-

put a signal from one of 13 taps provided by the 15 inter-

nal divider stages of the Real Time Clock. The fre-

quency of the SQW pin can be changed by

programming Register A as shown in T able 1. The SQW

signal can be turned on and off using the SQWE bit in

is less than 4.25 volts typical.

PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1

SELECT BITS REGISTER A tPI PERIODIC SQW OUTPUT

RS3 RS2 RS1 RS0

tPI PERIODIC

INTERRUPT RATE

SQW OUTPUT

FREQUENCY

0 0 0 0 None None

0 0 0 1 3.90625 ms 256 Hz

0 0 1 0 7.8125 ms 128 Hz

0 0 1 1 122.070 s8.192 kHz

0 1 0 0 244.141 s4.096 kHz

0 1 0 1 488.281 s2.048 kHz

0 1 1 0 976.5625 s1.024 kHz

0 1 1 1 1.953125 ms 512 Hz

1 0 0 0 3.90625 ms 256 Hz

1 0 0 1 7.8125 ms 128 Hz

1 0 1 0 15.625 ms 64 Hz

1 0 1 1 31.25 ms 32 Hz

1 1 0 0 62.5 ms 16 Hz

1 1 0 1 125 ms 8 Hz

1 1 1 0 250 ms 4 Hz

1 1 1 1 500 ms 2 Hz

DS12887

041697 4/17

AD0–AD7 (Multiplexed Bidirectional Address/Data

Bus) – Multiplexed buses save pins because address

information and data information time share the same

signal paths. The addresses are present during the first

portion of the bus cycle and the same pins and signal

paths are used for data in the second portion of the cycle.

Address/data multiplexing does not slow the access time

of the DS12887 since the bus change from address to

data occurs during the internal RAM access time.

Addresses must be valid prior to the falling edge of AS/

ALE, at which time the DS12887 latches the address

from AD0 to AD6. Valid write data must be present and

held stable during the latter portion of the DS or WR

pulses. In a read cycle the DS12887 outputs 8 bits of

data during the latter portion of the DS or RD pulses. The

read cycle is terminated and the bus returns to a high

impedance state as DS transitions low in the case of

Motorola timing or as RD transitions high in the case of

Intel timing.

AS (Address Strobe Input) – A positive going address

strobe pulse serves to demultiplex the bus. The falling

edge of AS/ALE causes the address to be latched within

the DS12887. The next rising edge that occurs on the

AS bus will clear the address regardless of whether CS

is asserted. Access commands should be sent in pairs.

DS (Data Strobe or Read Input) – The DS/RD pin has

two modes of operation depending on the level of the

MOT pin. When the MOT pin is connected to VCC,

Motorola bus timing is selected. In this mode DS is a

positive pulse during the latter portion of the bus cycle

and is called Data Strobe. During read cycles, DS signi-

fies the time that the DS12887 is to drive the bidirec-

tional bus. In write cycles the trailing edge of DS causes

the DS12887 to latch the written data. When the MOT

pin is connected to GND, Intel bus timing is selected. In

this mode the DS pin is called Read(RD). RD identifies

the time period when the DS12887 drives the bus with

read data. The RD signal is the same definition as the

Output Enable (OE) signal on a typical memory.

R/W (Read/Write Input) – The R/W pin also has two

modes of operation. When the MOT pin is connected to

VCC for Motorola timing, R/W is at a level which indicates

whether the current cycle is a read or write. A read cycle

is indicated with a high level on R/W while DS is high. A

write cycle is indicated when R/W is low during DS.

When the MOT pin is connected to GND for Intel timing,

the R/W signal is an active low signal called WR. In this

mode the R/W pin has the same meaning as the Write

Enable signal (WE) on generic RAMs.

CS (Chip Select Input) – The Chip Select signal must

be asserted low for a bus cycle in the DS12887 to be

accessed. CS must be kept in the active state during DS

and AS for Motorola timing and during RD and WR for

Intel timing. Bus cycles which take place without

asserting CS will latch addresses but no access will

occur. When VCC is below 4.25 volts, the DS12887

internally inhibits access cycles by internally disabling

the CS input. This action protects both the real time

clock data and RAM data during power outages.

IRQ (Interrupt Request Output) – The IRQ pin is an

active low output of the DS12887 that can be used as an

interrupt input to a proc essor. The IRQ output remains

low as long as the status bit causing the interrupt is pres-

ent and the corresponding interrupt–enable bit is set. To

clear the IRQ pin the processor program normally reads

the C register. The RESET pin also clears pending

interrupts.

When no interrupt conditions are present, the IRQ level is

in the high impedance state. Multiple interrupting devices

can be connected to an IRQ bus. The IRQ bus is an open

drain output and requires an external pull–up resistor.

RESET (Reset Input) – The RESET pin has no effect

on the clock, calendar, or RAM. On power–up the

RESET pin can be held low for a time in order to allow

the power supply to stabilize. The amount of time that

RESET is held low is dependent on the application.

However, if RESET is used on power–up, the time

RESET is low should exceed 200 ms to make sure that

the internal timer that controls the DS12887 on pow-

er-up has timed out. When RESET is low and VCC is

above 4.25 volts, the follow ing occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to zero.

B. Alarm Interrupt Enable (AIE) bit is cleared to zero.

C. Update Ended Interrupt Flag (UF) bit is cleared to

zero.

D. Interrupt Request Status Flag (IRQF) bit is cleared to

zero.

E. Periodic Interrupt Flag (PF) bit is cleared to zero.

F . The device is not accessible until RESET is returned

high.

G. Alarm Interrupt Flag (AF) bit is cleared to zero.

H. IRQ pin is in the high impedance state.

I. Square W ave Output Enable (SQWE) bit is cleared

to zero.

J. Update Ended Interrupt Enable (UIE) is cleared to

zero.

DS12887

041697 5/17

In a typical application RESET can be connected to

VCC. This connection will allow the DS12887 to go in

and out of power fail without affecting any of the control

registers.

ADDRESS MAP

The address map of the DS12887 is shown in Figure 2.

The address map consists of 1 14 bytes of user RAM, 10

bytes of RAM that contain the RTC time, calendar, and

alarm data, and four bytes which are used for control

and status. All 128 bytes can be directly written or read

except for the following:

1. Registers C and D are read–only.

2. Bit 7 of Register A is read–only.

3. The high order bit of the seconds byte is read–only.

The contents of four registers (A,B,C, and D) are

described in the “Registers” section.

ADDRESS MAP DS12887 Figure 2

000

14 BYTES

127 7F

SECONDS

SECONDS ALARM

MINUTES

MINUTES ALARM

HOURS

HOURS ALARM

DAY OF THE WEEK

DAY OF THE MONTH

MONTH

YEAR

BINARY OR BCD INPUTS

TIME, CALENDAR AND ALARM LOCATIONS

The time and calendar information is obtained by read-

ing the appropriate memory bytes. The time, calendar ,

and alarm are set or initialized by writing the appropriate

RAM bytes. The contents of the ten time, calendar , and

alarm bytes can be either Binary or Binary–Coded Deci-

mal (BCD) format. Before writing the internal time, cal-

endar, and alarm registers, the SET bit in Register B

should be written to a logic one to prevent updates from

occurring while access is being attempted. In addition

to writing the ten time, calendar, and alarm registers in a

selected format (binary or BCD), the data mode bit (DM)

of Register B must be set to the appropriate logic level.

All ten time, calendar, and alarm bytes must use the

same data mode. The set bit in Register B should be

cleared after the data mode bit has been written to allow

the real time clock to update the time and calendar

bytes. Once initialized, the real time clock makes all

updates in the selected mode. The data mode cannot

be changed without reinitializing the ten data bytes.

Table 2 shows the binary and BCD formats of the ten

time, calendar , and alarm locations. The 24–12 bit can-

not be changed without reinitializing the hour locations.

When the 12–hour format is selected, the high order bit

of the hours byte represents PM when it is a logic one.

The time, calendar, and alarm bytes are always acces-

sible because they are double buffered. Once per

second the ten bytes are advanced by one second and

DS12887

041697 6/17

checked for an alarm condition. If a read of the time and

calendar data occurs during an update, a problem exists

where seconds, minutes, hours, etc. may not correlate.

The probability of reading incorrect time and calendar

data is low. Several methods of avoiding any possible

incorrect time and calendar reads are covered later in

this text.

The three alarm bytes can be used in two ways. First,

when the alarm time is written in the appropriate hours,

minutes, and seconds alarm locations, the alarm inter-

rupt is initiated at the specified time each day if the alarm

enable bit is high . The second use condition is to insert

a “don’t care” state in one or more of the three alarm

bytes. The “don’t care” code is any hexadecimal value

from C0 to FF . The two most significant bits of each byte

set the “don’t care” condition when at logic 1. An alarm

will be generated each hour when the “don’t care” bits

are set in the hours byte. Similarly, an alarm is gener-

ated every minute with “don’t care” codes in the hours

and minute alarm bytes. The “don’t care” codes in all

three alarm bytes create an interrupt every second.

TIME, CALENDAR AND ALARM DATA MODES Table 2

ADDRESS

FUNCTION

DECIMAL RANGE

ADDRESS

LOCATION

FUNCTION

DECIMAL

RANGE BINARY DATA MODE BCD DATA MODE

0 Seconds 0–59 00–3B 00–59

1Seconds Alarm 0–59 00–3B 00–59

2 Minutes 0–59 00–3B 00–59

3Minutes Alarm 0–59 00–3B 00–59

4Hours–12–hr Mode 1–12 01–0C AM, 81–8C PM 01–12AM, 81–92PM

Hours–24–hr Mode 0–23 00–17 00–23

5Hours Alarm–12–hr 1–12 01–0C AM, 81–8C PM 01–12AM, 81–92PM

Hours Alarm–24–hr 0–23 00–17 00–23

6Day of the Week

Sunday = 1 1–7 01–07 01–07

7Date of the Month 1–31 01–1F 01–31

8 Month 1–12 01–0C 01–12

9 Year 0–99 00–63 00–99

NONVOLATILE RAM

The 114 general purpose nonvolatile RAM bytes are not

dedicated to any special function within the DS12887.

They can be used by the processor program as nonvol-

atile memory and are fully available during the update

cycle.

INTERRUPTS

The RTC plus RAM includes three separate, fully auto-

matic sources of interrupt for a processor. The alarm

interrupt can be programmed to occur at rates from

once per second to once per day . The periodic interrupt

can be selected for rates from 500 ms to 122 µs. The

update–ended interrupt can be used to indicate to the

program that an update cycle is complete. Each of

these independent interrupt conditions is described in

greater detail in other sections of this text.

The processor program can select which interrupts, if

any, are going to be used. Three bits in Register B

enable the interrupts. Writing a logic 1 to an interrupt-

enable bit permits that interrupt to be initiated when the

event occurs. A zero in an interrupt-enable bit prohibits

the IRQ pin from being asserted from that interrupt

condition. If an interrupt flag is already set when an

interrupt is enabled, IRQ is immediately set at an active

level, although the interrupt initiating the event may

have occurred much earlier. As a result, there are cases

DS12887

041697 7/17

where the program should clear such earlier initiated

interrupts before first enabling new interrupts.

When an interrupt event occurs, the relating flag bit is

set to logic 1 in Register C. These flag bits are set inde-

pendent of the state of the corresponding enable bit in

without enabling the corresponding enable bits. The

interrupt flag bit is a status bit which software can

interrogate as necessary . When a flag is set, an indica-

tion is given to software that an interrupt event has

occurred since the flag bit was last read; however , care

should be taken when using the flag bits as they are

cleared each time Register C is read. Double latching is

included with Register C so that bits which are set

remain stable throughout the read cycle. All bits which

are set (high) are cleared when read and new interrupts

which are pending during the read cycle are held until

after the cycle is completed. One, two, or three bits can

be set when reading Register C. Each utilized flag bit

should be examined when read to ensure that no inter-

rupts a re lost.

The second flag bit usage method is with fully enabled

interrupts. When an interrupt flag bit is set and the corre-

sponding interrupt enable bit is also set, the IRQ pin is

asserted low . IRQ is asserted as long as at least one of

the three interrupt sources has its flag and enable bits

both set. The IRQF bit in Register C is a one whenever

the IRQ pin is being driven low. Determination that the

RTC initiated an interrupt is accomplished by reading

one or more interrupts have been initiated by the

DS12887. The act of reading Register C clears all

active flag bits and the IRQF bit.

OSCILLATOR CONTROL BITS

When the DS12887 is shipped from the factory, the

internal oscillator is turned off. This feature prevents the

lithium energy cell from being used until it is installed in a

system. A pattern of 010 in bits 4 through 6 of Register A

will turn the oscillator on and enable the countdown

chain. A pattern of 11X will turn the oscillator on, but

holds the countdown chain of the oscillator in reset. All

other combinations of bits 4 through 6 keep the oscilla-

tor off.

SQUARE WAVE OUTPUT SELECTION

Thirteen of the 15 divider taps are made available to a

1-of-15 selector, as shown in the block diagram of Fig-

ure 1. The first purpose of selecting a divider tap is to

generate a square wave output signal on the SQW pin.

The RS0–RS3 bits in Register A establish the square

wave output frequency . These frequencies are listed in

Table 1. The SQW frequency selection shares its

1–of–15 selector with the periodic interrupt generator.

Once the frequency is selected, the output of the SQW

pin can be turned on and off under program control with

the square wave enable bit (SQWE).

PERIODIC INTERRUPT SELECTION

The periodic interrupt will cause the IRQ pin to go to an

active state from once every 500 ms to once every

122 µs. This function is separate from the alarm inter-

rupt which can be output from once per second to once

per day . The periodic interrupt rate is selected using the

same Register A bits which select the square wave fre-

quency (see Table 1). Changing the Register A bits

affects both the square wave frequency and the periodic

interrupt output. However, each function has a separate

enable bit in Register B. The SQWE bit controls the

square wave output. Similarly, the periodic interrupt is

enabled by the PIE bit in Register B. The periodic inter-

rupt can be used with software counters to measure

inputs, create output intervals, or await the next needed

software function.

UPDATE CYCLE

The DS12887 executes an update cycle once per

second regardless of the SET bit in Register B. When

the SET bit in Register B is set to one, the user copy of

the double buffered time, calendar, and alarm bytes is

frozen and will not update as the time increments. How-

ever , the time countdown chain continues to update the

internal copy of the buffer. This feature allows time to

maintain accuracy independent of reading or writing the

time, calendar, and alarm buffers and also guarantees

that time and calendar information is consistent. The

update cycle also compares each alarm byte with the

corresponding time byte and issues an alarm if a match

or if a “don’t care” code is present in all three positions.

There are three methods that can handle access of the

real time clock that avoid any possibility of accessing

inconsistent time and calendar data. The first method

uses the update–ended interrupt. If enabled, an inter-

rupt occurs after every up date cycle that indicates that

over 999 ms are available to read valid time and date

information. If this interrupt is used, the IRQF bit in Reg-

DS12887

041697 8/17

ister C should be cleared before leaving the interrupt

routine.

A second method uses the update–in–progress bit

(UIP) in Register A to determine if the update cycle is in

progress. The UIP bit will pulse once per second. After

the UIP bit goes high, the update transfer occurs 244 µs

later . If a low is read on the UIP bit, the user has at least

244 µs before the time/calendar data will be changed.

Therefore, the user should avoid interrupt service rou-

tines that would cause the time needed to read valid

time/calendar data to exceed 244 µs.

The third method uses a periodic interrupt to determine

if an update cycle is in progress. The UIP bit in Register

A is set high between the setting of the PF bit in Register

C (see Figure 3). Periodic interrupts that occur at a rate

of greater than tBUC allow valid time and date informa-

tion to be reached at each occurrence of the periodic

interrupt. The reads should be complete within 1

(tPI/2+ tBUC) to ensure that data is not read during the

update cycle.

UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3

UIP BIT IN

UF BIT IN

PF BIT IN

tPI/2

tBUC

tPI = Periodic interrupt time interval per Table 1.

tBUC = Delay time before update cycle = 244 µs.

REGISTERS

The DS12887 has four control registers which are

accessible at all times, even during the update cycle.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

UIP

The Update In Progress (UIP) bit is a status flag that can

be monitored. When the UIP bit is a one, the update

transfer will soon occur . When UIP is a zero, the update

transfer will not occur for at least 244 µs. The time, cal-

endar, and alarm information in RAM is fully available

for access when the UIP bit is zero. The UIP bit is read

only and is not affected by RESET . Writing the SET bit in

clears the UIP status bit.

DV0, DV1, DV2

These three bits are used to turn the oscillator on or off

and to reset the countdown chain. A pattern of 010 is the

only combination of bits that will turn the oscillator on

and allow the RTC to keep time. A pattern of 11X will

enable the oscillator but holds the countdown chain in

reset. The next update will occur at 500 ms after a pat-

tern of 010 is written to DV0, DV1, and DV2.

RS3, RS2, RS1, RS0

These four rate–selection bits select one of the 13 taps

on the 15–stage divider or disable the divider output.

The tap selected can be used to generate an output

square wave (SQW pin) and/or a periodic interrupt. The

user can do one of the following:

1. Enable the interrupt with the PIE bit;

2. Enable the SQW output pin with the SQWE bit;

3. Enable both at the same time and the same rate; or

4. Enable neither.

DS12887

041697 9/17

Table 1 lists the periodic interrupt rates and the square

wave frequencies that can be chosen with the RS bits.

These four read/write bits are not affected by RESET.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SET PIE AIE UIE SQWE DM 24/12 DSE

SET

When the SET bit is a zero, the update transfer functions

normally by advancing the counts once per second.

When the SET bit is written to a one, any update transfer

is inhibited and the program can initialize the time and

calendar bytes without an update occurring in the midst

of initializing. Read cycles can be executed in a similar

manner. SET is a read/write bit that is not modified by

RESET or internal functions of the DS12887.

PIE

The periodic interrupt enable PIE bit is a read/write bit

which allows the Periodic Interrupt Flag (PF) bit in Reg-

ister C to drive the IRQ pin low. When the PIE bit is set to

one, periodic interrupts are generated by driving the

IRQ pin low at a rate specified by the RS3–RS0 bits of

from being driven by a periodic interrupt, but the Peri-

odic Flag (PF) bit is still set at the periodic rate. PIE is not

modified by any internal DS12887 functions, but is

cleared to zero on RESET.

AIE

The Alarm Interrupt Enable (AIE) bit is a read/write bit

which, when set to a one, permits the Alarm Flag (AF) bit

in register C to assert IRQ. An alarm interrupt occurs for

each second that the three time bytes equal the three

alarm bytes including a “don’t care” alarm code of binary

11XXXXXX. When the AIE bit is set to zero, the AF bit

does not initiate the IRQ signal. The RESET pin clears

AIE to zero. The internal functions of the DS12887 do

not affect the AIE bit.

UIE

The Update Ended Interrupt Enable (UIE) bit is a read/

write that enables the Update End Flag (UF) bit in Regis-

ter C to assert IRQ. The RESET pin going low or the

SET bit going high clears to UIE bit.

SQWE

When the Square W ave Enable (SQWE) bit is set to a

one, a square wave signal at the frequency set by the

rate–selection bits RS3 through RS0 is driven out on a

SQW pin. When the SQWE bit is set to zero, the SQW

pin is held low; the state of SQWE is cleared by the

RESET pin. SQWE is a read/write bit.

The Data Mode (DM) bit indicates whether time and cal-

endar information is in binary or BCD format. The DM bit

is set by the program to the appropriate format and can

be read as required. This bit is not modified by internal

functions or RESET. A one in DM signifies binary data

while a zero in DM specifies Binary Coded Decimal

(BCD) data.

24/12

The 24/12 control bit establishes the format of the hours

byte. A one indicates the 24–hour mode and a zero indi-

cates the 12–hour mode. This bit is read/write and is not

affected by internal functions of RESET.

DSE

The Daylight Savings Enable (DSE) bit is a read/write bit

which enables two special updates when DSE is set to

one. On the first Sunday in April the time increments

from 1:59:59 AM to 3:00:00 AM. On the last Sunday in

October when the time first reaches 1:59:59 AM it

changes to 1:00:00 AM. These special updates do not

occur when the DSE bit is a zero. This bit is not affected

by internal functions or RESET.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IRQF PF AF UF 0 0 0 0

IRQF

The Interrupt Request Flag (IRQF) bit is set to a one

when one or more of the following are true:

PF = PIE = 1

AF = AIE = 1

UF = UIE = 1

That is, IRQF = PF • PIE + AF • AIE + UF • UIE.

DS12887

041697 10/17

Any time the IRQF bit is a one, the IRQ pin is driven low .

All flag bits are cleared after Register C is read by the

program or when the RESET pin is low.

The Periodic Interrupt Flag (PF) is a read–only bit which

is set to a one when an edge is detected on the selected

tap of the divider chain. The RS3 through RS0 bits

establish the periodic rate. PF is set to a one indepen-

dent of the state of the PIE bit. When both PF and PIE

are ones, the IRQ signal is active and will set the IRQF

bit. The PF bit is cleared by a RESET or a software read

of Register C.

A one in the Alarm Interrupt Flag (AF) bit indicates that

the current time has matched the alarm time. If the AIE

bit is also a one, the IRQ pin will go low and a one will

appear in the IRQF bit. A RESET or a read of Register C

will clear AF.

The Update Ended Interrupt Flag (UF) bit is set after

each update cycle. When the UIE bit is set to one, the

one in UF causes the IRQF bit to be a one which will

assert the IRQ pin. UF is cleared by reading Register C

or a RESET.

BIT 0 THROUGH BIT 3

These are unused bits of the status Register C. These

bits always read zero and cannot be written.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

VRT 0 0 0 0 0 0 0

VRT

The Valid RAM and Time (VRT) bit is set to the one state

by Dallas Semiconductor prior to shipment. This bit is

not writable and should always be a one when read. If a

zero is ever present, an exhausted internal lithium

energy source is indicated and both the contents of the

RTC data and RAM data are questionable. This bit is

unaf fected by RESET.

BIT 6 THROUGH BIT 0

The remaining bits of Register D are not usable. They

cannot be written and, when read, they will always read

zero.

DS12887

041697 11/17

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V

Operating Temperature 0°C to 70°C

Storage Temperature –40°C to +70°C

Soldering Temperature 260°C for 10 seconds (See Note 7)

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Voltage VCC 4.5 5.0 5.5 V 1

Input Logic 1 VIH 2.2 VCC+0.3 V 1

Input Logic 0 VIL –0.3 +0.8 V 1

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Current ICC1 715 mA 2

Input Leakage IIL –1.0 +1.0 A3

I/O Leakage ILO –1.0 +1.0 A4

Input Current IMOT –1.0 +500 A3

Output @ 2.4V IOH –1.0 mA 1, 5

Output @ 0.4V IOL 4.0 mA 1

Write Protect Voltage VTP 4.0 4.25 4.5 V

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 5 pF

Output Capacitance COUT 7 pF

DS12887

041697 12/17

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5V to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Cycle Time tCYC 385 DC ns

Pulse Width, DS/E Low or RD/WR

High PWEL 150 ns

Pulse Width, DS/E High or RD/WR

Low PWEH 125 ns

Input Rise and Fall T ime tR, tF30 ns

R/W Hold Time tRWH 10 ns

R/W Setup T ime Before DS/E tRWS 50 ns

Chip Select Setup Time Before DS,

WR, or RD tCS 20 ns

Chip Select Hold T ime tCH 0ns

Read Data Hold T ime tDHR 10 80 ns

Write Data Hold Time tDHW 0ns

Muxed Address Valid Time to AS/

ALE Fall tASL 30 ns

Muxed Address Hold T ime tAHL 10 ns

Delay T ime DS/E to AS/ALE Rise tASD 20 ns

Pulse Width AS/ALE High PWASH 60 ns

Delay T ime, AS/ALE to DS/E Rise tASED 40 ns

Output Data Delay Time From

DS/E or RD tDDR 20 120 ns 6

Data Setup T ime tDSW 100 ns

Reset Pulse Width tRWL 5ms

IRQ Release from DS tIRDS 2ms

IRQ Release from RESET tIRR 2ms

NOTES:

1. All voltages are referenced to ground.

2. All outputs are open.

3. The MOT pin has an internal pulldown of 20KW.

4. Applies to the AD0–AD7 pins, the IRQ pin,and the SQW pin when each is in the high impedance state.

5. The IRQ pin is open drain.

6. Measured with a load as shown in Figure 4.

7. Real–T ime Clock Modules can be successfully processed through conventional wave–soldering techniques as

long as temperature exposure to the lithium energy source contained within does not exceed +85°C. However,

post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used

to prevent damage to the crystal.

tASED

tASD tCYC

PWEH

PWASH

PWEL

tRWS tRWH

tCS tCH

tDHW

tDHR

tDSW

tAHL

tASL

tDDR

R/W

AD0–AD7

WRITE

AD0–AD7

READ

DS12887

041697 13/17

OUTPUT LOAD Figure 4 +5 VOLTS

50 pF

D.U.T.

1.1 KW

680W

DS12887 BUS TIMING FOR MOTOROLA INTERFACE

DS12887

041697 14/17

DS12887 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE

tCYC

PWASH

tASD

tASD tASED

PWEH

PWEL

tDSW

tCH

tDHW

tASL

tAHL

tCS

ALE

(AS PIN)

(DS PIN)

(R/W PIN)

AD0–AD7

DS12887

041697 15/17

DS12887 BUS TIMING FOR INTEL INTERFACE READ CYCLE

tASD tASED

PWEH

PWEL

tCYC

PWASH

tASD

tCH

tDHR

tASL

tAHL

tCS

ALE

(AS PIN)

(DS PIN)

(R/W PIN)

AD0–AD7

tDDR

DS12887 IRQ RELEASE DELAY TIMING

tRWL

tIRR

tIRDS

RESET

IRQ

DS12887

041697 16/17

POWER DOWN/POWER UP TIMING

VCC

4.50V

3.2V

tPD tREC

DATA RETENTION

tDR

CURRENT SUPPLIED

FROM INTERNAL

LITHIUM ENERGY CELL

POWER DOWN/POWER UP TIMING

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CS at VIH before Power–Down tPD 0 s

VCC slew from 4.5V to 0V

(CS at VIH)tF300 s

VCC slew from 0V to 4.5V

(CS at VIH)tR100 s

CS at VIH after Power–Up tREC 20 200 ms

(tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention tDR 10 years

NOTE:

The real time clock will keep time to an accuracy of +1 minute per month during data retention time for the period of tDR.

WARNING:

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

DS12887

041697 17/17

DS12887 REAL TIME CLOCK PLUS RAM

112

C E

11 EQUAL SPACES AT

.100 .010 TNA

NOTE: PINS 2, 3, 16, 20, 21 AND 22 ARE MISSING BY

DESIGN.

DIM MIN MAX

24–PINPKG

A IN.

B IN.

C IN.

D IN.

E IN.

F IN.

G IN.

H IN.

J IN.

K IN.

1.320

33.53 1.335

33.91

0.675

17.15 0.700

17.78

0.345

8.76 0.370

9.40

0.100

2.54 0.130

3.30

0.015

0.38 0.030

0.76

0.110

2.79 0.140

3.56

0.090

2.29 0.110

2.79

0.590

14.99 0.630

16.00

0.008

0.20 0.012

0.30

0.015

0.38 0.021

0.53