IN
EN
SS
PG
OUT
SNS
CSS
CIN
COUT
1.5 V
GND
1.2 V = 0.5 V
+ 100 mV
+ 200 mV
+ 400 mV
ref
TPS7A7200
FB
1.6V
800mV400mV200mV
100mV
50mV
Optional
CFF
0
1
2
3
4
5
6
1.5V to 1.0V1.5V to 1.2V
1.8V to 1.5V
2.5V to 1.8V
3.0V to 2.5V
3.3V to 3.0V
5.5V to 5.0V
0
1
2
3
Time (100µs/div)
Output Voltage (V)
Output Current (A)
Output Current
Output Current Slew Rate: 1A/µs
G311
TPS7A7200
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SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
2-A, Fast-Transient, Low-Dropout Voltage Regulator
Check for Samples: TPS7A7200
1FEATURES DESCRIPTION
234• Low Dropout Voltage: 180 mV at 2 A The TPS7A7200 low-dropout (LDO) voltage regulator
• VIN Range: 1.5 V to 6.5 V is designed for applications seeking very-low dropout
capability (180 mV at 2 A) with an input voltage from
• Configurable Fixed VOUT Range: 0.9 V to 3.5 V 1.5 V to 6.5 V. The TPS7A7200 offers an innovative,
Adjustable VOUT Range: 0.9 V to 5.0 V user-configurable, output-voltage setting from 0.9 V to
• Very Good Load and Line Transient Response 3.5 V, eliminating external resistors and any
• Stable with Ceramic Output Capacitor associated error.
• 1.5% Accuracy over Line, Load, and The TPS7A7200 has very fast load-transient
Temperature response, is stable with ceramic output capacitors,
• Programmable Softstart and supports a better than 2% accuracy over line,
load, and temperature. A soft-start pin allows for an
• Power Good (PG) Output application to reduce inrush into the load.
• 3-mm × 3-mm QFN-16 and 5-mm × 5-mm QFN- Additionally, an open-drain, power-good signal allows
20 Packages for sequencing power rails.
The TPS7A7200 is available in 3-mm × 3-mm,
APPLICATIONS 16-pin QFN and 5-mm × 5-mm, 20-pin QFN
• Wireless Infrastructure: SerDes, FPGA, DSP™ packages.
• RF Components: VCO, ADC, DAC, LVDS
• Set-Top Boxes: Amplifier, ADC, DAC, FPGA,
DSP
• Wireless LAN, Bluetooth®
• PCs and Printers
• Audio and Visual
Load Transient Response with
Seven Different Results:
1.5 VIN to 1.0 VOUT, 1.5 VIN to 1.2 VOUT,
1.8 VIN to 1.5 VOUT, 2.5 VIN to 1.8 VOUT,
3.0 VIN to 2.5 VOUT, 3.3 VIN to 3.0 VOUT,
and 5.5 VIN to 5.0 VOUT
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DSP is a trademark of Texas Instruments.
3Bluetooth is a registered trademark of Bluetooth SIG, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT Description
TPS7A7200yyyz YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). VALUE
MIN MAX UNIT
IN, PG, EN –0.3 +7.0 V
Voltage SS, FB, SNS, OUT –0.3 VIN + 0.3(2) V
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V –0.3 VOUT + 0.3 V
OUT Internally limited A
Current PG (sink current into IC) 5 mA
Operating virtual junction, TJ–55 +150 °C
Temperature Storage, Tstg –55 +150 °C
Human body model (HBM, JESD22-A114A) 2 kV
Electrostatic Discharge Rating(3) Charged device model (CDM, JESD22-C101B.01) 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or +7.0 V, whichever is smaller.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
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THERMAL INFORMATION TPS7A7200(3)
THERMAL METRIC(1)(2) RGW (QFN) RGT (QFN) UNITS
20 PINS 16 PINS
θJA Junction-to-ambient thermal resistance(4) 35.7 44.6
θJCtop Junction-to-case (top) thermal resistance(5) 33.6 54.3
θJB Junction-to-board thermal resistance(6) 15.2 17.2 °C/W
ψJT Junction-to-top characterization parameter(7) 0.4 1.1
ψJB Junction-to-board characterization parameter(8) 15.4 17.2
θJCbot Junction-to-case (bottom) thermal resistance(9) 3.8 3.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on printed circuit board (PCB) copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4 × 4 thermal via array.
ii. RGT: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
(b) i. RGW: Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage.
ii .RGT: Both the top and bottom copper layers have a dedicated pattern for 5% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.
To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), 1.425 V ≤VIN ≤6.5 V, VIN ≥VOUT(TARGET) + 0.3 V or
VIN ≥VOUT(TARGET) + 0.5 V(1)(2), OUT connected to 50 Ωto GND(3),VEN = 1.1 V, COUT = 10 μF, CSS = 10 nF, CFF = 0 pF (RGW
package), CFF = 220 pF (RGT package)(4), and PG pin pulled up to VIN with 100 kΩ, 27 kΩ ≤ R2 ≤33 kΩfor adjustable
configuration(5), unless otherwise noted.
Typical values are at TJ= +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 1.425 6.5 V
V(SS) SS pin voltage 0.5 V
Output voltage range Adjustable with external feedback resistors 0.9 5.0 V
Fixed with voltage setting pins 0.9 3.5
RGT package only, adjustable, –40°C ≤TA≤+85°C, –1.5 +1.5
25 mA ≤IOUT ≤2 A
VOUT RGT package only, fixed, –40°C ≤TA≤+85°C, –2.0 +2.0
Output voltage accuracy(6)(7) %
25 mA ≤IOUT ≤2 A
Adjustable, 25 mA ≤IOUT ≤2 A –2.0 +2.0
Fixed, 25 mA ≤IOUT ≤2 A –3.0 +3.0
ΔVO(ΔVI) Line regulation IOUT = 25 mA 0.01 %/V
ΔVO(ΔIO) Load regulation 25 mA ≤IOUT ≤2 A 0.1 %/A
VOUT ≤3.3 V, IOUT = 2 A, V(FB) = GND 180 mV
V(DO) Dropout voltage (8) 3.3 V < VOUT, IOUT = 2 A, V(FB) = GND 470 mV
VOUT forced at 0.9 × VOUT(TARGET), VIN = 3.3 V,
I(LIM) Output current limit 2.4 3.1 A
VOUT(TARGET) = 0.9 V
Full load, IOUT = 2 A 2.6 mA
Minimum load, 4 mA
I(GND) GND pin current VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA
Shutdown, PG = (open), 0.1 5 μA
VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V
I(EN) EN pin current VIN = 6.5 V, V(EN) = 0 V and 6.5 V ±0.1 μA
EN pin low-level input voltage
VIL(EN) 0 0.5 V
(disable device)
EN pin high-level input voltage
VIH(EN) 1.1 6.5 V
(enable device)
VIT(PG) PG pin threshold For the direction PG↓with decreasing VOUT 0.85VOUT 0.9VOUT 0.96VOUT V
Vhys(PG) PG pin hysteresis For PG↑0.02VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current into device) 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), V(PG) = 6.5 V 1 μA
I(SS) SS pin charging current V(SS) = GND, VIN = 3.3 V 3.5 5.1 7.2 μA
BW = 100 Hz to 100 kHz,
VnOutput noise voltage 40.65 μVRMS
VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A
Shutdown, temperature increasing +160 °C
Tsd Thermal shutdown temperature Reset, temperature decreasing +140 °C
TJOperating junction temperature –40 +125 °C
(1) When VOUT ≤3.5 V, VIN ≥(VOUT + 0.3 V) or 1.425 V, whichever is greater; when VOUT > 3.5 V, VIN ≥(VOUT + 0.5 V).
(2) VOUT(TARGET) is the calculated target VOUT value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V
in fixed configuration, or the expected VOUT value set by external feedback resistors in adjustable configuration.
(3) This 50-Ωload is disconnected when the test conditions specify an IOUT value.
(4) CFF is the capacitor between FB pin and OUT
(5) R2 is the bottom-side of the feedback resistor between the FB pin and OUT. See Figure 40 for details.
(6) When the TPS7A7200 is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(7) The TPS7A7200 is not tested at VOUT = 0.9 V, 2.7 V ≤VIN ≤6.5 V, and 500 mA ≤IOUT ≤2 A because the power dissipation is higher
than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package.
(8) V(DO) is not defined for output voltage settings below 1.2 V.
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Thermal
Protection
OUT
PG
IN
SS
EN Hysteresis
Current
Limit
UVLO
1.2-V Reference
0.45 V
GND
CSS
Charge
Pump
0.5-V Reference
70 kΩ 50 kΩ
50 kΩ
32R
320R 160R 80R 40R 20R 10R
FB
SNS
1.6V800mV400mV200mV100mV50mV
700-µs
Delay
Optional
TPS7A7200
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SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
NOTE: 320R = 1.024 MΩ(that is, 1R = 3.2 kΩ).
Figure 1. Functional Block Diagram
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OUT
SNS
FB
PG
50mV
IN
EN
SS
NC
1.6V
OUT
100mV 6
200mV 7
GND 8
400mV 9
800mV 10
1
2
3
4
5
15
14
13
12
11
20
OUT
19
18
IN
17
IN
16
Thermal Pad
GND
100mV 5
200mV 6
GND 7
400mV 8
SNS
FB
PG
50mV
1
2
3
4
EN
SS
1.6V
800mV
12
11
10
9
Thermal Pad
OUT
16
OUT
15
14
IN
13
IN
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
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PIN CONFIGURATIONS
RGT PACKAGE RGW PACKAGE
3-mm × 3-mm QFN-16 5-mm × 5-mm QFN-20
(TOP VIEW) (TOP VIEW)
PIN DESCRIPTIONS
NAME RGW RGT DESCRIPTION
50mV,
100mV, Output voltage setting pins. These pins should be connected to ground or left floating. Connecting these
200mV, 5, 6, 7, 4, 5, 6, pins to ground increases the output voltage by the value of the pin name; multiple pins can be
400mV, 9, 10, 11 8, 9, 10 simultaneously connected to GND to select the desired output voltage. Leave these pins floating (open)
800mV, when not in use. See the USER-CONFIGURABLE OUTPUT VOLTAGE section for more details.
1.6V Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disables the device.
EN 14 12 See the ENABLE AND SHUTDOWN THE DEVICE section for more details.
Output voltage feedback pin. Connected to the error amplifier. See the USER-CONFIGURABLE OUTPUT
FB 3 2 VOLTAGE and TRADITIONAL ADJUSTABLE CONFIGURATION sections for more details. A 220-pF
ceramic capacitor from FB pin to OUT is highly recommended.
GND 8, 18 7 Ground pin.
15, 16, Unregulated supply voltage pin. It is recommended to connect an input capacitor to this pin. See INPUT
IN 13, 14
17 CAPACITOR REQUIREMENTS for more details.
Not internally connected. The NC pin is not connected to any electrical node. It is strongly recommended to
NC 12 — connect this pin and the thermal pad to a large-area ground plane. See the Power Dissipation section for
more details.
Regulated output pin. A 4.7-μF or larger capacitance is required for stability. See OUTPUT CAPACITOR
OUT 1, 19, 20 15, 16 REQUIREMENTS for more details.
Active-high power good pin. An open-drain output that indicates when the output voltage reaches 90% of
PG 4 3 the target. See POWER GOOD for more details.
Output voltage sense input pin. See the USER-CONFIGURABLE OUTPUT VOLTAGE and TRADITIONAL
SNS 2 1 ADJUSTABLE CONFIGURATION sections for more details.
Soft-start pin. Leaving this pin open provides soft-start of the default setting.
Connecting an external capacitor between this pin and the ground enables the soft-start function by
SS 13 11 forming an RC-delay circuit in combination with the integrated resistance on the silicon. See the SOFT-
START section for more details.
It is strongly recommended to connect the thermal pad to a large-area ground plane. If available, connect
Thermal Pad an electrically-floating, dedicated thermal plane to the thermal pad as well.
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0
50
100
150
200
250
300
0 0.5 1 1.5 2
Output Current (A)
Dropout Voltage (mV)
−40°C
0°C
25°C
85°C
105°C
125°C
VIN = 1.5 V
FB = GND
G011
0
50
100
150
200
250
300
1 2 3 4 5 5.5
Input Voltage (V)
Dropout Voltage (mV)
−40°C
0°C
25°C
85°C
105°C
125°C
IOUT = 2 A
FB = GND and plot VIN −VOUT
G014
0.873
0.882
0.891
0.9
0.909
0.918
0.927
0 0.5 1 1.5 2
Output Current (A)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
VIN = 1.425 V
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
G201
3.395
3.43
3.465
3.5
3.535
3.57
3.605
0 0.5 1 1.5 2
Output Current (A)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
VIN = 3.8 V
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins
to GND; 50mV, 100mV pins open
G204
0.873
0.882
0.891
0.9
0.909
0.918
0.927
0 0.5 1 1.5 2
Output Current (A)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
VIN = 1.425 V
R1 = 24.1 kΩ, R2 = 30.1 kΩ
G001
4.85
4.9
4.95
5
5.05
5.1
5.15
0 0.5 1 1.5 2
Output Current (A)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
VIN = 5.3 V
R1 = 271 kΩ, R2 = 30.1 kΩ
G004
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SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
LOAD REGULATION LOAD REGULATION
(0.9 V, Adjustable) (5.0 V, Adjustable)
Figure 2. Figure 3.
LOAD REGULATION LOAD REGULATION
(0.9 V, Fixed by Setting Pins) (3.5 V, Fixed by Setting Pins)
Figure 4. Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 6. Figure 7.
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0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VOUT(TARGET) (V)
Actual Output Voltage (V)
VIN = 4 V
IOUT = 50 mA
G020
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
VOUT(TARGET) (V)
Error in Actual Output Voltage (%)
VIN = 4 V
IOUT = 50 mA
G021
0.873
0.882
0.891
0.9
0.909
0.918
0.927
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
IOUT = 25 mA
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
G206
3.395
3.43
3.465
3.5
3.535
3.57
3.605
5 5.5 6 6.5
Input Voltage (V)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
IOUT = 25 mA
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins
to GND; 50mV, 100mV pins open
G207
0.873
0.882
0.891
0.9
0.909
0.918
0.927
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
IOUT = 25 mA
R1 = 24.1 kΩ, R2 = 30.1 kΩ
G006
4.85
4.9
4.95
5
5.05
5.1
5.15
5 5.5 6 6.5
Input Voltage (V)
Output Voltage (V)
−40°C
0°C
25°C
85°C
105°C
125°C
Y−axis scale is 1%Vout/div
IOUT = 25 mA
R1 = 271 kΩ, R2 = 30.1 kΩ
G007
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
LINE REGULATION LINE REGULATION
(0.9 V, Adjustable) (5.0 V, Adjustable)
Figure 8. Figure 9.
LINE REGULATION LINE REGULATION
(0.9 V, Fixed by Setting Pins) (3.5 V, Fixed by Setting Pins)
Figure 10. Figure 11.
OUTPUT VOLTAGE: OUTPUT VOLTAGE:
ACTUAL vs PIN-SETTING ACTUAL (Normalized) vs PIN-SETTING
Figure 12. Figure 13.
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84
85
86
87
88
89
90
91
92
93
94
95
96
−50 −25 0 25 50 75 100 125
Temperature (°C)
Threshould Voltage (%VOUT)
VIN=1.5V
VIN=6.5V VOUT(TARGET) = 1.2 V
100mV, 200mV, 400mV pins to GND
50mV, 800mV, 1.6V pins open
50−Ω resistor between OUT and GND
G050
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2
Forced PG Pin Current (mA)
PG Pin Voltage (V)
VIN = 1.5 V, −40 °C
VIN = 1.5 V, 25 °C
VIN = 1.5 V, 125 °C
VIN = 6.5 V, −40 °C
VIN = 1.5 V, 25 °C
VIN = 1.5 V, 125 °C
Spec limit defined at 1−mA.
VOUT(TARGET) = 1.2 V
100mV, 200mV, 400mV
pins to GND
50mV, 800mV, 1.6V
pins open
50−Ω resistor
from OUT to GND
G051
0
1
2
3
4
5
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
Shutdown Ground Current (µA)
−40°C
0°C
25°C
85°C
105°C
125°C
EN = GND
50−Ω resistor between OUT and GND
G032
0
1
2
3
4
0 0.5 1 1.5 2 2.5 3 3.5
Forced Output Voltage (V)
Current Limit (A)
VIN = 4 V
VOUT(TARGET) = 3.5 V
200mV, 400mV, 800mV, 1.6V pins to GND
50mV, 100mV pins open
G041
0
1
2
3
4
5
0 0.5 1 1.5 2
Output Current (A)
Ground Current (mA)
−40°C
0°C
25°C
85°C
105°C
125°C
VIN = 1.8 V
VOUT(TARGET) = 1.5 V
200mV, 800mV pins to GND
50mV, 100mV, 200mV, 400mV
pins open
G030
0
1
2
3
4
5
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
Ground Current (mA)
−40°C
0°C
25°C
85°C
105°C
125°C
IOUT = 25 mA
VOUT(TARGET) = 0.9 V
400mV pin to GND; 50mV, 100mV
200mV, 800mV, 1.6V pins open
G033
TPS7A7200
www.ti.com
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
GND PIN CURRENT vs OUTPUT CURRENT GND PIN CURRENT vs INPUT VOLTAGE
Figure 14. Figure 15.
GND PIN CURRENT IN SHUTDOWN CURRENT LIMIT
vs TEMPERATURE vs OUTPUT VOLTAGE (Foldback)
Figure 16. Figure 17.
POWER-GOOD THRESHOLD VOLTAGE
vs TEMPERATURE POWER-GOOD PIN DRIVE CAPABILITY
Figure 18. Figure 19.
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0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (dB)
VIN=3.6V, IOUT=0.1A
VIN=3.6V, IOUT=2A
VIN=3.8V, IOUT=0.1A
VIN=3.8V, IOUT=2A
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G071
0.01
0.1
1
10
10 100 1k 10k 100k
Frequency (Hz)
Output Spectral Noise Density (µV/ Hz)
VOUT(TARGET) = 0.9 V
VOUT(TARGET) = 1.2 V
VOUT(TARGET) = 3.3 V
VIN = VOUT(TARGET) + 0.3 V
IOUT = 2 A
100 Hz to 100 kHz RMS Noise
0.9 V: 37.43 µVRMS
1.2 V: 40.65 µVRMS
3.3 V: 82.59 µVRMS
G061
0.01
0.1
1
10
10 100 1k 10k 100k
Frequency (Hz)
Output Spectral Noise Density (µV/ Hz)
CSS = 100nF, COUT = 100µF
CSS = 100nF, COUT = 10µF
CSS = 10nF, COUT = 100µF
CSS = 10nF, COUT = 10µF
CSS = 1nF, COUT = 100µF
CSS = 1nF, COUT = 10µF
VIN = 1.8 V, IOUT = 1 A
VOUT(TARGET) = 1.5 V
200mV, 800mV pins to GND
50mV, 100mV, 400mV, 1.6V pins open
G063
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
NOISE SPECTRAL DENSITY BY OUTPUT VOLTAGE NOISE SPECTRAL DENSITY BY EXTERNAL CAPACITORS
Figure 20. Figure 21.
POWER-SUPPLY RIPPLE REJECTION
vs FREQUENCY
Figure 22.
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0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN
VOUT
Time (1 ms/div)
Voltage (V)
IN = EN
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G302
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN
VOUT
Time (1 ms/div)
Voltage (V)
IN = EN
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G303
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
VIN
VOUT
Time (20 µs/div)
Voltage (V)
IOUT=1A,
VOUT(TARGET)=3.3V
400mV, 800mV, 1.6V
pins to GND
50mV, 100mV, 200mV
pins open
G300
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
VIN
VOUT
Time (2 ms/div)
Voltage (V)
VOUT(TARGET)=3.3V
400mV, 800mV,
1.6V pins to GND
50mV, 100mV,
200mV pins open
50−Ω resistor between
OUT and GND
G301
1
1.1
1.2
1.3
1.4
Output Voltage
0
2
4
6
8
Time (100µs/div)
Output Voltage (V)
Output Current (A)
Output
Current
Output Current Slew Rate: 1A/µs
VOUT(TARGET)=1.2V
100mV, 200mV, 400mV pins to GND
50mV, 800mV, 1.6V pins open
G314
3.1
3.2
3.3
3.4
3.5
Output Voltage
0
2
4
6
8
Time (100µs/div)
Output Voltage (V)
Output Current (A)
Output
Current
Output Current Slew Rate: 1A/µs
VOUT(TARGET)=3.3V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G317
TPS7A7200
www.ti.com
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
(VOUT = 1.2 V) (VOUT = 3.3 V)
Figure 23. Figure 24.
LINE TRANSIENT RESPONSE POWER-UP/POWER-DOWN (IN = EN)
Figure 25. Figure 26.
TURN-ON RESPONSE (IN = EN) TURN-OFF RESPONSE (IN = EN)
Figure 27. Figure 28.
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0.1
1
10
100
1000
1 10 100 1000
CSS (nF)
Softstart Delay (ms)
0%VOUT to 90%VOUT
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G308
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN
VOUT (CSS=0F)
VEN VOUT (CSS=10nF)
VOUT (CSS=100nF)
VOUT (CSS=1µF)
Time (5 ms/div)
Voltage (V)
VOUT(TARGET) = 3.3 V
50−Ω resistor from OUT to GND
G306
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN VOUT (CSS=0F)
VEN VOUT (CSS=10nF)
VOUT (CSS=100nF)
VOUT (CSS=1µF)
Time (50 ms/div)
Voltage (V)
VOUT(TARGET) = 3.3 V
50−Ω resistor from OUT to GND
G307
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN VOUT
VEN
Time (1 ms/div)
Voltage (V)
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G304
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN
VOUT
VEN
Time (1 ms/div)
Voltage (V)
50−Ω resistor from OUT to GND
VOUT(TARGET) = 3.3 V
400mV, 800mV, 1.6V pins to GND
50mV, 100mV, 200mV pins open
G305
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ= +25°C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 μF, COUT = 10 μF, C(SS) = 10 nF, and the PG pin
pulled up to VIN with 100-kΩpull-up resistor, unless otherwise noted.
EN PULSE ON RESPONSE EN PULSE OFF RESPONSE
(Over Stable VIN) (Over Stable VIN)
Figure 29. Figure 30.
SOFT-START DELAY vs CSS (Enlarged View) SOFT-START DELAY vs CSS (Reduced View)
Figure 31. Figure 32.
SOFT-START DELAY vs CSS
Figure 33.
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V = 1.2 V
OUT = 0.5 V + 100 mV + 200 mV + 400 mV
0.5 V is Vref
V = 0.5 V (1 + 3.2R/2.29R) 2.29R is parallel resistance of 16R, 8R, and 4R.´
OUT
3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
Optional
CFF
FB
CFF
TPS7A7200
www.ti.com
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
APPLICATION INFORMATION
OVERVIEW
The TPS7A7200 belongs to a family of new-generation LDO regulators that uses innovative circuitry to offer
very-low dropout voltage along with the flexibility of a programmable output voltage.
The dropout voltage for this LDO regulator family is 0.18 V at 2 A. This voltage is ideal for making the
TPS7A7200 into a point-of-load (POL) regulator because 0.18 V at 2 A is lower than any voltage gap among the
most common voltage rails: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V. This device offers a fully user-
configurable output voltage setting method. The TPS7A7200 output voltage can be programmed to any target
value from 0.9 V to 3.5 V in 50-mV steps.
Another big advantage of using the TPS7A7200 is the wide range of available operating input voltages: from 1.5
V to 6.5 V. The TPS7A7200 also has very good line and load transient response. All these features allow the
TPS7A7200 to meet most voltage-regulator needs for under-6-V applications, using only one device so that less
time is spent on inventory control.
Texas Instruments also offers different output current ratings with other family devices: the TPS7A7100 (1 A) and
TPS7A7300 (3 A).
USER-CONFIGURABLE OUTPUT VOLTAGE
Unlike traditional LDO devices, the TPS7A7200 comes with only one orderable part number; there is no
adjustable or fixed output voltage option. The output voltage of the TPS7A7200 is selectable in accordance with
the names given to the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V. For each
pin connected to the ground, the output voltage setting increases by the value associated with that pin name,
starting from the value of the reference voltage of 0.5 V; floating the pin(s) has no effect on the output voltage.
Figure 34 through Figure 39 show examples of how to program the output voltages.
Figure 34. 0.9-V Configuration Figure 35. 1.2-V Configuration
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V = 3.3 V
OUT = 0.5 V + 400 mV + 800 mV + 1.6 V
0.5 V is Vref
V = 0.5 V (1 + 3.2R/0.571R) 0.571R is parallel resistance of 4R, 2R, and 1R.´
OUT
3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
Optional
CFF
FB
CFF
V = 3.5 V
OUT = 0.5 V + 200 mV + 400 mV + 800 mV + 1.6 V
0.5 V is Vref
V = 0.5 V (1 + 3.2R/0.533R) 0.533R is parallel resistance of 8R, 4R, 2R, and 1R.´
OUT
3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
Optional
FB
CFF
CFF
V = 1.8 V
OUT = 0.5 V + 100 mV + 400 mV + 800 mV
0.5 V is Vref
V = 0.5 V (1 + 3.2R/1.23R) 1.23R is parallel resistance of 16R, 4R, and 2R.´
OUT
3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
FB
CFF
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
Optional
CFF
V = 2.5 V
OUT = 0.5 V + 400 mV + 1.6 V
0.5 V is Vref
V = 0.5 V (1 + 3.2R/0.8R) 0.8R is parallel resistance of 4R and 1R.´
OUT
3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
Optional
CFF
FB
CFF
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
Figure 36. 1.8-V Configuration Figure 37. 2.5-V Configuration
Figure 38. 3.3-V Configuration Figure 39. 3.5-V Configuration
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SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
See Table 1 for a full list of target output voltages and corresponding pin settings. The voltage setting pins have
a binary weight; therefore, the output voltage can be programmed to any value from 0.9 V to 3.5 V in 50-mV
steps.
Figure 12 and Figure 13 shows this output voltage programming performance.
NOTE
Any output voltage setting that is not listed in Table 1 is not covered in the Electrical
Characteristics. For output voltages greater than 3.5 V, use a traditional adjustable
configuration (see the TRADITIONAL ADJUSTABLE CONFIGURATION section).
Table 1. User Configurable Output Voltage Setting
VOUT(TARGET) VOUT(TARGET)
50mV 100mV 200mV 400mV 800mV 1.6V 50mV 100mV 200mV 400mV 800mV 1.6V
(V) (V)
0.90 open open open GND open open 2.25 GND GND open open open GND
0.95 GND open open GND open open 2.30 open open GND open open GND
1.00 open GND open GND open open 2.35 GND open GND open open GND
1.05 GND GND open GND open open 2.40 open GND GND open open GND
1.10 open open GND GND open open 2.45 GND GND GND open open GND
1.15 GND open GND GND open open 2.50 open open open GND open GND
1.20 open GND GND GND open open 2.55 GND open open GND open GND
1.25 GND GND GND GND open open 2.60 open GND open GND open GND
1.30 open open open open GND open 2.65 GND GND open GND open GND
1.35 GND open open open GND open 2.70 open open GND GND open GND
1.40 open GND open open GND open 2.75 GND open GND GND open GND
1.45 GND GND open open GND open 2.80 open GND GND GND open GND
1.50 open open GND open GND open 2.85 GND GND GND GND open GND
1.55 GND open GND open GND open 2.90 open open open open GND GND
1.60 open GND GND open GND open 2.95 GND open open open GND GND
1.65 GND GND GND open GND open 3.00 open GND open open GND GND
1.70 open open open GND GND open 3.05 GND GND open open GND GND
1.75 GND open open GND GND open 3.10 open open GND open GND GND
1.80 open GND open GND GND open 3.15 GND open GND open GND GND
1.85 GND GND open GND GND open 3.20 open GND GND open GND GND
1.90 open open GND GND GND open 3.25 GND GND GND open GND GND
1.95 GND open GND GND GND open 3.30 open open open GND GND GND
2.00 open GND GND GND GND open 3.35 GND open open GND GND GND
2.05 GND GND GND GND GND open 3.40 open GND open GND GND GND
2.10 open open open open open GND 3.45 GND GND open GND GND GND
2.15 GND open open open open GND 3.50 open open GND GND GND GND
2.20 open GND open open open GND
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3.2R
32R 16R 8R 4R 2R 1R
VIN
OUT
SNS
FB
FB
0.5 V
50mV 100mV 200mV 400mV 800mV 1.6V
OUT
SNS
FB
PG
50mV
IN
Thermal Pad
EN
SS
NC
1.6V
100mV
200mV
GND
400mV
800mV
OUT
OUT
GND
IN
IN
R1
R2
R1
R2
Optional
V =
OUT ´0.500
(R + R )
1 2
R2
CFF
CFF
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
TRADITIONAL ADJUSTABLE CONFIGURATION
For any output voltage target that is not supported in the USER-CONFIGURABLE OUTPUT VOLTAGE section,
a traditional adjustable configuration with external-feedback resistors can be used with the TPS7A7200.
Figure 40 shows how to configure the TPS7A7200 as an adjustable regulator with an equation and Table 2 lists
recommended pairs of feedback resistor values.
NOTE
The bottom side of feedback resistor R2 in Figure 40 should be in the range of 27 kΩto
33 kΩin order to maintain the specified regulation accuracy.
Figure 40. Traditional Adjustable Configuration with External Resistors
Table 2. Recommended Feedback-Resistor Values
E96 SERIES R40 SERIES
VOUT(TARGET)
(V) R1 (kΩ) R2 (kΩ) R1 (kΩ) R2 (kΩ)
1.00 30.1 30.1 30.0 30.0
1.20 39.2 28.0 43.7 31.5
1.50 61.9 30.9 60.0 30.0
1.80 80.6 30.9 80.0 30.7
1.90 86.6 30.9 87.5 31.5
2.50 115 28.7 112 28.0
3.00 147 29.4 150 30.0
3.30 165 29.4 175 31.5
5.00 280 30.9 243 27.2
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SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
DROPOUT VOLTAGE
The TPS7A7200 maintains its output voltage regulation with a dropout voltage (VIN – VOUT) greater than 0.18 V
under the test conditions specified in the Electrical Characteristics. In most power distribution tree (system)
designs, the TPS7A7200 can be used with a 0.3-V difference in the common voltage rails (for example, from 3.3
VIN to 3.0 VOUT, from 1.8 VIN to 1.5 VOUT, or from 1.5 VIN to 1.2 VIN).
INPUT CAPACITOR REQUIREMENTS
As a result of its very fast transient response and low-dropout operation support, it is necessary to reduce the
line impedance at the input pin of the TPS7A7200. The line impedance depends heavily on various factors, such
as wire (PCB trace) resistance, wire inductance, and/or output impedance of the upstream voltage supply (power
supply to the TPS7A7200). Therefore, a specific value for the input capacitance cannot be recommended until
the previously listed factors are finalized.
In addition, simple usage of large input capacitance is known to form unwanted LC resonance in combination
with input wire inductance. For example, a 5-nH inductor and a 10-µF input capacitor form an LC filter that has a
resonance at 712 kHz. This value of 712 kHz is well inside the bandwidth of the TPS7A7200 control loop.
The best guideline is to use a capacitor of up to 1 µF with well-designed wire connections (PCB layout) to the
upstream supply. In case it is difficult to optimize the input line, use a large tantalum capacitor in combination
with a good-quality, low-ESR, 1-µF ceramic capacitor.
OUTPUT CAPACITOR REQUIREMENTS
The TPS7A7200 is designed to be stable with standard ceramic capacitors with capacitance values from 4.7 μF
to 47 μF. The TPS7A7200 is evaluated using an X5R-type, 10-μF ceramic capacitor. X5R- and X7R-type
capacitors are highly recommended because they have minimal variation in value and ESR over temperature.
Maximum ESR should be below 1.0 Ω.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases duration of the transient response.
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS7A7200 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage
upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when
the device powers on. As explained in the INPUT CAPACITOR REQUIREMENTS section, the input line
impedance should be well-designed.
SOFT-START
The TPS7A7200 has a SS pin that provides a soft-start (slow start) function.
By leaving the SS pin open, the TPS7A7200 performes a soft-start by its default setting.
As shown in Figure 1, by connecting a capacitor between the SS pin and the ground, the CSS capacitor forms an
RC pair together with the integrated 50-kΩresistor. The RC pair operates as an RC-delay circuit for the soft-start
together with the internal 700-µs delay circuit.
The relationship between CSS and the soft-start time is shown in Figure 31 through Figure 33.
CURRENT LIMIT
The TPS7A7200 internal current limit circuitry protects the regulator during fault conditions. During a current limit
event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current
limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any
applications to use this current limit function as a part of expected normal operation. Extended periods of current
limit operation degrade device reliability.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
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PD+ǒVIN *VOUTǓ IOUT
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
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Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage
while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses
from the input to the output of the device. The energy consumed by the device is minimal during these events;
therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of
the upstream supply during these events.
ENABLE AND SHUTDOWN THE DEVICE
The EN pin switches the enable and disable (shutdown) states of the TPS7A7200. A logic high input at the EN
pin enables the device; a logic low input disables the device. When disabled, the device consumption current is
reduced.
POWER GOOD
The TPS7A7200 has a power good function that works with the PG output pin. When the output voltage
undershoots the threshold voltage VIT(PG) during normal operation, the PG open-drain output turns from a high-
impedance state to a low-impedance state. When the output voltage exceeds the VIT(PG) threshold by an amount
greater than the PG hysteresis, Vhys(PG), the PG open-drain output turns from a low-impedance state to high-
impedance state. By connecting a pull-up resistor (usually between OUT and PG), any downstream device can
receive an active-high enable logic signal.
When setting the output voltage to less than 1.8 V and using a pull-up resistor between OUT and PG, depending
on the downstream device specifications, the downstream device may not accept the PG output as a valid high-
level logic voltage. In such cases, put a pull-up resistor between IN and PG, not between OUT and PG.
Figure 19 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is
calculated using Figure 19, and is approximately 200 Ω. Any pull-up resistor greater than 10 kΩworks fine for
this purpose.
THERMAL INFORMATION
Thermal Protection
The thermal protection feature disables the output when the junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A7200 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A7200 into thermal shutdown
degrades device reliability.
Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 1:
(1)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS7A7200
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
0
20
40
60
80
100
120
0 1 2 3 4 5 6 7 8 9 10
Board Copper Area (inch2)
θJA (°C/W)
θJA(RGW)
θJA(RGT)
G800
R =
qJA
+125 C T° - A
PD
TPS7A7200
www.ti.com
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
On the QFN (RGW or RGT) package, the primary conduction path for heat is through the exposed pad to the
PCB. The pad can be connected to ground or be left floating; however, it should be attached to an appropriate
amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal
resistance depends on the maximum ambient temperature, maximum device junction temperature, and power
dissipation of the device and can be calculated using Equation 2:
(2)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 41 .
Figure 41. θJA vs Board Size
shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a
guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as
explained in the Estimating Junction Temperature section.
Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older θJC,Top
parameter is listed as well.
Where:
PDis the power dissipation shown by Equation 2.
TTis the temperature at the center-top of the IC package.
TBis the PCB temperature measured 1mm away from the IC package on the PCB surface (see
Figure 42). (3)
NOTE: Both TTand TBcan be measured on actual application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TTand TB, see Application Report SBVA025,Using New Thermal Metrics,
available for download at www.ti.com.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS7A7200
0
5
10
15
20
25
0 1 2 3 4 5 6 7 8 9 10
ψJB(RGW)
ψJB(RGT)
ψJT(RGW)ψJT(RGT)
Board Copper Area (inch2)
ψJT and ψJB (°C/W)
G801
T onPCB
BT on ofICtop
T
1mm
(a)ExampleRGW(QFN)PackageMeasurement
TPS7A7200
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
www.ti.com
Figure 42. Measuring Points for TTand TB
By looking at Figure 43, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 3 is a good way to estimate TJby simply measuring TTor TB, regardless of the
application board size.
Figure 43. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to Application Report SBVA025,Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to Application Report SPRA953,IC Package Thermal Metrics, also available on the TI
website.
20 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS7A7200
TPS7A7200
www.ti.com
SBVS136E –MARCH 2012–REVISED SEPTEMBER 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2013) to Revision E Page
• Added new paragraph to Current Limit section .................................................................................................................. 18
Changes from Revision C (May 2012) to Revision D Page
• Added CFF capacitor to front page block diagram ................................................................................................................ 1
• Added CFF test condition and table note to Electrical Characteristics .................................................................................. 4
• Deleted maximum value for Output Current Limit parameter in Electrical Characteristics table .......................................... 4
• Added text to FB pin description ........................................................................................................................................... 6
• Added CFF capacitor to Figure 34 ....................................................................................................................................... 13
• Added CFF capacitor to Figure 35 ....................................................................................................................................... 13
• Added CFF capacitor to Figure 36 ....................................................................................................................................... 13
• Added CFF capacitor to Figure 37 ....................................................................................................................................... 13
• Added CFF capacitor to Figure 38 ....................................................................................................................................... 14
• Added CFF capacitor to Figure 39 ....................................................................................................................................... 14
• Added CFF capacitor to Figure 40 ....................................................................................................................................... 16
• Changed capacitor values in first sentence of OUTPUT CAPACITOR REQUIREMENTS section ................................... 17
Changes from Revision B (April 2012) to Revision C Page
• Added RGT package to Figure 41 ...................................................................................................................................... 19
• Added RGT package to Figure 43 ...................................................................................................................................... 20
Changes from Revision A (March 2012) to Revision B Page
• Changed Accuracy feature bullet .......................................................................................................................................... 1
• Added RGT (QFN-16) package to Features ......................................................................................................................... 1
• Added RGT (QFN-16) package to Thermal Information table. ............................................................................................. 3
• Added test conditions for RGT package to Output Voltage Accuracy parameter ................................................................ 4
• Added RGT package pinout drawing .................................................................................................................................... 6
• Added RGT package to Pin Descriptions table .................................................................................................................... 6
Changes from Original (March 2012) to Revision A Page
• Changed from product preview to production data ............................................................................................................... 1
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS7A7200
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS7A7200RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PYMQ
TPS7A7200RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PYMQ
TPS7A7200RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 SAC
TPS7A7200RGWT ACTIVE VQFN RGW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 SAC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS7A7200 :
•Enhanced Product: TPS7A7200-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A7200RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS7A7200RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS7A7200RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS7A7200RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A7200RGTR QFN RGT 16 3000 367.0 367.0 35.0
TPS7A7200RGTT QFN RGT 16 250 210.0 185.0 35.0
TPS7A7200RGWR VQFN RGW 20 3000 367.0 367.0 35.0
TPS7A7200RGWT VQFN RGW 20 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Aug-2013
Pack Materials-Page 2
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