2008-2011 Microchip Technology Inc. DS39927C
PIC24F16KA102 Family
Data Sheet
20/28-Pin General Purpose,
16-Bit Flash Microcontrollers
with nanoWatt XLP Technology
DS39927C-page 2 2008-2011 Microchip Technology Inc.
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The Microchip name and logo, the Microchip logo, dsPIC,
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© 2008-2011, Microchip Technology Incorporated, Printed in
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Printed on recycled paper.
ISBN: 978-1-61341-690-7
Note the following details of the code protection feature on Microch ip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Microchip received ISO/TS-16949:2009 certification for its worldwide
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and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopp ing
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2008-2011 Microchip Technology Inc. DS39927C-page 3
PIC24F16KA102 FAMILY
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals On
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, Flash, SRAM and Peripherals On
• Sleep – CPU, Flash and Peripherals Off and
SRAM On
• Deep Sleep – CPU, Flash, SRAM and
Most Peripherals Off:
- Run mode currents down to 8
A typical
- Idle mode currents down to 2
A typical
- Deep Sleep mode currents down to 20 nA typical
- RTCC 490 nA, 32 kHz, 1.8V
- Watchdog Timer 350 nA, 1.8V typical
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
Peripheral Feat ures:
• Hardware Real-Time Clock and Calendar (RTCC):
- Provides clock, calendar and alarm functions
- Can run in Deep Sleep Mode
• Programmable Cyclic Redundancy Check (CRC)
• Serial Communication modules:
- SPI, I
2
C™ and two UART modules
• Three 16-Bit Timers/Counters with Programmable
Prescaler
• 16-Bit Capture Inputs
• 16-Bit Compare/PWM Output
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
Analog Features:
• 10-Bit, up to 9-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable Input/
Output Configuration
• Charge Time Measurement Unit (CTMU):
- Used for capacitance sensing
- Time measurement, down to 1 ns resolution
- Delay/pulse generation, down to 1 ns resolution
S pecial Microcontroller Features:
• Operating Voltage Range of 1.8V to 3.6V
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
- Erase/write cycles: 10,000 minimum
- 40-years’ data retention minimum
• Data EEPROM:
- Erase/write cycles: 100,000 minimum
- 40-years’ data retention minimum
• Fail-Safe Clock Monitor
• System Frequency Range Declaration bits:
- Declaring the frequency range optimizes the current
consumption.
• Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via two Pins
• Programmable High/Low-Voltage Detect (HLVD)
• Brown-out Reset (BOR):
- Standard BOR with three programmable trip points;
can be disabled in Sleep
• Extreme Low-Power DSBOR for Deep Sleep,
LPBOR for all other modes
PIC24F
Device
Pins
Program
Memory
(bytes)
SRAM
(bytes)
Data
EEPROM
(bytes)
Timers
16-Bit
Capture
Input
Output
Compare/
PWM
UART/
IrDA®
I2C™
10-Bit A/D
(ch)
Comparators
CTMU (ch)
RTCC
SPI
08KA101 20 8K 1.5K 512 3 1 1 2 1 1 9 2 9 Y
16KA101 20 16K 1.5K 512 3 1 1 2 1 1 9 2 9 Y
08KA102 28 8K 1.5K 512 3 1 1 2 1 1 9 2 9 Y
16KA102 28 16K 1.5K 512 3 1 1 2 1 1 9 2 9 Y
20/28-Pin General Purpose, 16-Bit Flash Microcontrollers
with nanoWatt XLP Technology
PIC24F16KA102 FAMILY
DS39927C-page 4 2008-2011 Microchip Technology Inc.
Pin Diagrams
PIC24XXKAX01
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Pin PDIP, SSOP, SOIC(2)
MCLR/VPP/RA5
OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3
PGC2/AN0/VREF+/CN2/RA0
PGD2/AN1/VREF-/CN3/RA1
PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0
PGC3/SOSCO/T1CK/U2CTS/CN0/RA4
PGD3/SOSCI/U2RTS/U2BCLK/CN1/RB4
OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2
U1RX/CN6/RB2
PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
VDD
VSS
U1TX/INT0/CN23/RB7
U1CTS/SCL1/CN22/RB8
REFO/SS1/T2CK/T3CK/CN11/RB15
AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14
AN11/SDO1/CTPLS/CN13/RB13
AN12/HLVDIN/SCK1/CTED2/CN14/RB12
U1RTS/U1BCLK/SDA1/CN21/RB9
OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
PIC24FXXKAX02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SPDIP, SSOP, SOIC(2)
MCLR/VPP/RA5
VSS
VDD
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0
SOSCO/T1CK/U2CTS/CN0/RA4
SOSCI/U2RTS/U2BCLK/CN1/RB4
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C1INA/C2INC/CN7/RB3
AN4/C1INB/C2IND/U1RX/CN6/RB2
PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
PGD3/SDA1(1)/CN27/RB5
VDD
VSS
PGC3/SCL1(1)/CN24/RB6
IC1/CN9/RA7
OC1/C2OUT/INT2/CTED1/CN8/RA6
U1TX/INT0/CN23/RB7
U1RTS/U1BCLK/SDA1/CN21/RB9
U1CTS/SCL1/CN22/RB8
REFO/SS1/T2CK/T3CK/CN11/RB15
AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14
AN11/SDO1/CTPLS/CN13/RB13
AN12/HLVDIN/CTED2/CN14/RB12
PGD2/SDI1/PMD2/CN16/RB10
PGC2/SCK1/CN15/RB11
Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set.
2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
2008-2011 Microchip Technology Inc. DS39927C-page 5
PIC24F16KA102 FAMILY
Pin Diagrams (Continued)
89
2
3
1
12
13
14
15
106
11
1617181920
7
PIC24FXXKA102
5
4
MCLR/VPP/RA5
PGC2/AN0/VREF+/CN2/RA0
PGD2/AN1/VREF-/CN3/RA1
VDD
VSS
PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0
PGC3/SOSCO/T1CK/U2CTS/CN0/RA4
PGD3/SOSCI/U2RTS/CN1/U2BCLK/RB4
OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3
OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2
OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
U1TX/INT0/CN23/RB7
AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14
U1CTS/SCL1/CN22/RB8
U1RX/CN6/RB2
PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN11/SDO1/CTPLS/ CN13/RB13
AN12/HLVDIN/SCK1/CTED2/CN14/RB12
U1RTS/U1BCLK/SDA1/CN21/RB9
REFO/SS1/T2CK/T3CK/CN11/RB15
Note 1: The bottom pad of the QFN package should be connected to VSS.
2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
20-Pin QFN(1,2)
PIC24F16KA102 FAMILY
DS39927C-page 6 2008-2011 Microchip Technology Inc.
Pin Diagrams (Continued)
Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set.
2: The bottom pad of the QFN package should be connected to VSS.
3: All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
28-Pin QFN(2,3)
10 11
2
3
6
1
18
19
20
21
22
12 13 14 15
8
7
16
17
232425262728
9
PIC24FXXKA102
5
4
VSS
PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C1INA/C2INC/CN7/RB3
AN4/C1INB/C2IND/U1RX/CN6/RB2
PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
IC1/CN9/RA7
OC1/C2OUT/INT2/CTED1/CN8/RA6
U1RTS/U1BCLK/SDA1/CN21/RB9
AN11/SDO1/CTPLS/CN13/RB13
AN12/HLVDIN/CTED2/CN14/RB12
PGD2/SDI1/PMD2/CN16/RB10
PGC2/SCK1/CN15/RB11
VDD
PGC3/SCL1(1)/CN24/RB6
SOSCO/T1CK/U2CTS/CN0/RA4
SOSCI/U2RTS/U2BCLK/CN1/RB4
U1TX/INT0/CN23/RB7
U1CTS/SCL1/CN22/RB8
PGD3/SDA1(1)/CN27/RB5
MCLR/VPP/RA5
AN0/V
REF
+/CN2/RA0
AN1/V
REF
-/CN3/RA1
VDD
Vss
REFO/SS1/T2CK/T3CK/CN11/RB15
AN10/CV
REF
/RTCC/OCFA/C1OUT/INT1/CN12/RB14
2008-2011 Microchip Technology Inc. DS39927C-page 7
PIC24F16KA102 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 17
3.0 CPU ........................................................................................................................................................................................... 23
4.0 Memory Organization ................................................................................................................................................................. 29
5.0 Flash Program Memory.............................................................................................................................................................. 45
6.0 Data EEPROM Memory ............................................................................................................................................................. 51
7.0 Resets ........................................................................................................................................................................................ 57
8.0 Interrupt Controller ..................................................................................................................................................................... 63
9.0 Oscillator Configuration .............................................................................................................................................................. 91
10.0 Power-Saving Features............................................................................................................................................................ 101
11.0 I/O Ports ................................................................................................................................................................................... 113
12.0 Timer1 ..................................................................................................................................................................................... 115
13.0 Timer2/3 ................................................................................................................................................................................... 117
14.0 Input Capture............................................................................................................................................................................ 123
15.0 Output Compare....................................................................................................................................................................... 125
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 131
17.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 139
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147
19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 155
20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 167
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 171
22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 173
23.0 Comparator Module.................................................................................................................................................................. 183
24.0 Comparator Voltage Reference................................................................................................................................................ 187
25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 189
26.0 Special Features ...................................................................................................................................................................... 193
27.0 Development Support............................................................................................................................................................... 203
28.0 Instruction Set Summary .......................................................................................................................................................... 207
29.0 Electrical Characteristics .......................................................................................................................................................... 215
30.0 Packaging Information.............................................................................................................................................................. 251
Appendix A: Revision History............................................................................................................................................................. 269
Index .................................................................................................................................................................................................. 271
The Microchip Web Site..................................................................................................................................................................... 275
Customer Change Notification Service .............................................................................................................................................. 275
Customer Support .............................................................................................................................................................................. 275
Reader Response .............................................................................................................................................................................. 276
Product Identification System ............................................................................................................................................................ 277
PIC24F16KA102 FAMILY
DS39927C-page 8 2008-2011 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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2008-2011 Microchip Technology Inc. DS39927C-page 9
PIC24F16KA102 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24F08KA101
• PIC24F16KA101
• PIC24F08KA102
• PIC24F16KA102
The PIC24F16KA102 family introduces a new line of
extreme low-power Microchip devices: a 16-bit micro-
controller family with a broad peripheral feature set and
enhanced computational performance. It also offers a
new migration option for those high-performance appli-
cations, which may be outgrowing their 8-bit platforms,
but do not require the numerical processing power of a
digital signal processor.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32-bit by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
All of the devices in the PIC24F16KA102 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
•On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.
•Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
•Instruction-Based Power-Saving Modes: There
are three instruction-based power-saving modes:
- Idle Mode: The core is shut down while leaving
the peripherals active.
- Sleep Mode: The core and peripherals that
require the system clock are shut down, leaving
the peripherals that use their own clock, or the
clock from other devices, active.
- Deep Sleep Mode: The core, peripherals (except
RTCC and DSWDT), Flash and SRAM are shut
down.
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
The PIC24F16KA102 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• Two Fast Internal Oscillators (FRCs): One with a
nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.
• A Phase Locked Loop (PLL) frequency multiplier,
available to the External Oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.
• A separate Internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
PIC24F16KA102 FAMILY
DS39927C-page 10 2008-2011 Microchip Technology Inc.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the
internal oscillator and enables the controller to switch to
the internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all the devices share
the same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also helps in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 20-pin to
28-pin devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex.
1.2 Other Special Features
•Communications: The PIC24F16KA102 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There is an I2C™ module that
supports both the Master and Slave modes of
operation. It also comprises UARTs with built-in
IrDA® encoders/decoders and an SPI module.
•Real-Time Clock/Calendar: This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
•10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
faster sampling speed. The 16-deep result buffer
can be used either in Sleep to reduce power, or in
Active mode to improve throughput.
•Charge Time Measurement Unit (CTMU)
Interface: The PIC24F16KA102 family includes
the new CTMU interface module, which can be
used for capacitive touch sensing, proximity
sensing and also for precision time measurement
and pulse generation.
1.3 Details on Individual Family
Members
Devices in the PIC24F16KA102 family are available in
20-pin and 28-pin packages. The general block
diagram for all devices is displayed in Figure 1-1.
The devices are different from each other in two ways:
1. Flash program memory (8 Kbytes for
PIC24F08KA devices, 16 Kbytes for PIC24F16KA
devices).
2. Available I/O pins and ports (18 pins on two
ports for 20-pin devices and 24 pins on two ports
for 28-pin devices).
3. Alternate SCLx and SDAx pins are available
only in 28-pin devices and not in 20-pin devices.
All other features for devices in this family are identical;
these are summarized in Ta b l e 1 - 1 .
A list of the pin features available on the
PIC24F16KA102 family devices, sorted by function, is
provided in Table 1-2.
Note: Table 1-1 provides the pin location of
individual peripheral features and not how
they are multiplexed on the same pin. This
information is provided in the pinout
diagrams on pages 4, 5 and 6 of the data
sheet. Multiplexed features are sorted by
the priority given to a feature, with the
highest priority peripheral being listed
first.
2008-2011 Microchip Technology Inc. DS39927C-page 11
PIC24F16KA102 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24F16KA102 FAMILY
Features
PIC24F08KA101
PIC24F16KA101
PIC24F08KA102
PIC24F16KA102
Operating Frequency DC – 32 MHz
Program Memory (bytes) 8K 16K 8K 16K
Program Memory (instructions) 2816 5632 2816 5632
Data Memory (bytes) 1536
Data EEPROM Memory (bytes) 512
Interrupt Sources (soft vectors/NMI traps) 30 (26/4)
I/O Ports PORTA<6:0>
PORTB<15:12, 9:7, 4, 2:0>
PORTA<7:0>
PORTB<15:0>
Total I/O Pins 18 24
Timers: Total Number (16-bit)
32-Bit (from paired 16-bit timers)
3
1
Input Capture Channels 1
Output Compare/PWM Channels 1
Input Change Notification Interrupt 17 23
Serial Communications: UART
SPI (3-wire/4-wire)
I2C™
2
1
1
10-Bit Analog-to-Digital Module (input channels) 9
Analog Comparators 2
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word
Mismatch (PWRT, OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 20-Pin PDIP/SSOP/SOIC/QFN 28-Pin SPDIP/SSOP/SOIC/QFN
PIC24F16KA102 FAMILY
DS39927C-page 12 2008-2011 Microchip Technology Inc.
FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
PORTA(1)
RA<0:7>
PORTB(1)
RB<0:15>
Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-2 for I/O port pin
descriptions.
Comparators
Timer2/3
Timer1 CTMU
IC1
A/D
10-Bit
OC1/PWM SPI1 I2C1
CN1-22(1) UART1/2
Data EEPROM
OSCI/CLKI
OSCO/CLKO
VDD,
Timing
Generation
VSS MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
DSWDT
RTCCHLVD
REFO
2008-2011 Microchip Technology Inc. DS39927C-page 13
PIC24F16KA102 FAMILY
TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS
Function
Pin Number
I/O Input
Buffer Description
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
AN0 2 19 2 27 I ANA A/D Analog Inputs
AN1 3 20 3 28 I ANA
AN2 4 1 4 1 I ANA
AN3 5 2 5 2 I ANA
AN4 7 4 6 3 I ANA
AN5 8 5 7 4 I ANA
AN10 17 14 25 22 I ANA
AN11 16 13 24 21 I ANA
AN12 15 12 23 20 I ANA
U1BCLK 13 10 18 15 O — UART1 IrDA® Baud Clock
U2BCLK 9 6 11 8 O — UART2 IrDA Baud Clock
C1INA 8 5 7 4 I ANA Comparator 1 Input A (Positive Input)
C1INB 7 4 6 3 I ANA Comparator 1 Input B (Negative Input Option 1)
C1INC 5 2 5 2 I ANA Comparator Input C (Negative Input Option 2)
C1IND 4 1 4 1 I ANA Comparator Input D (Negative Input Option 3)
C1OUT 17 14 25 22 O — Comparator 1 Output
C2INA 5 2 5 2 I ANA Comparator 2 Input A (Positive Input)
C2INB 4 1 4 1 I ANA Comparator 2 Input B (Negative Input Option 1)
C2INC 8 5 7 4 I ANA Comparator 2 Input C (Negative Input Option 2)
C2IND 7 4 6 3 I ANA Comparator 2 Input D (Negative Input Option 3)
C2OUT 14 11 20 17 O — Comparator 2 Output
CLKI 7 4 9 6 I ANA Main Clock Input Connection
CLKO 8 5 10 7 O — System Clock Output
Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
PIC24F16KA102 FAMILY
DS39927C-page 14 2008-2011 Microchip Technology Inc.
CN0 10 7 12 9 I ST Interrupt-on-Change Inputs
CN1 9 6 11 8 I ST
CN2 2 19 2 27 I ST
CN3 3 20 3 28 I ST
CN4 4 1 4 1 I ST
CN5 5 2 5 2 I ST
CN6 6 3 6 3 I ST
CN7 — — 7 4 I ST
CN8 14 11 20 17 I ST
CN9 — — 19 16 I ST
CN11 18 15 26 23 I ST
CN1217142522IST
CN1316132421IST
CN1415122320IST
CN15 — — 22 19 I ST
CN16 — — 21 18 I ST
CN2113101815IST
CN22 12 9 17 14 I ST
CN23 11 8 16 13 I ST
CN24 — — 15 12 I ST
CN27 — — 14 11 I ST
CN2985107IST
CN30 7 4 9 6 I ST
CVREF 17 14 25 22 O ANA Comparator Voltage Reference Output
CTED1 14 11 20 17 I ST CTMU Trigger Edge Input 1
CTED2 15 12 23 20 I ST CTMU Trigger Edge Input 2
CTPLS 16 13 24 21 O — CTMU Pulse Output
IC1 14 11 19 16 I ST Input Capture 1 Input
INT0 11 8 16 13 I ST External Interrupt Inputs
INT1 17 14 25 22 I ST
INT2 14 11 20 17 I ST
HLVDIN 15 12 23 20 I ANA HLVD Voltage Input
MCLR 1 18 1 26 I ST Master Clear (device Reset) Input
OC1 14 11 20 17 O — Output Compare/PWM Outputs
OCFA 17 14 25 22 I — Output Compare Fault A
OSCI 7 4 9 6 I ANA Main Oscillator Input Connection
OSCO 8 5 10 7 O ANA Main Oscillator Output Connection
TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input
Buffer Description
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
2008-2011 Microchip Technology Inc. DS39927C-page 15
PIC24F16KA102 FAMILY
PGC1 5 2 5 2 I/O ST In-Circuit Debugger and ICSP™ Programming
Clock
PGD1 4 1 4 1 I/O ST In-Circuit Debugger and ICSP Programming Data
PGC2 2 19 22 19 I/O ST In-Circuit Debugger and ICSP Programming
Clock
PGD2 3 20 21 18 I/O ST In-Circuit Debugger and ICSP Programming Data
PGC3 10 7 15 12 I/O ST In-Circuit Debugger and ICSP Programming
Clock
PGD3 9 6 14 11 I/O ST In-Circuit Debugger and ICSP Programming Data
RA0 2 19 2 27 I/O ST PORTA Digital I/O
RA1 3 20 3 28 I/O ST
RA2 7 4 9 6 I/O ST
RA3 8 5 10 7 I/O ST
RA4 10 7 12 9 I/O ST
RA5 1 18 1 26 I/O ST
RA6 14 11 20 17 I/O ST
RA7 — — 19 16 I/O ST
RB0 4 1 4 1 I/O ST PORTB Digital I/O
RB1 5 2 5 2 I/O ST
RB2 6 3 6 3 I/O ST
RB3 — — 7 4 I/O ST
RB4 9 6 11 8 I/O ST
RB5 — — 14 11 I/O ST
RB6 — — 15 12 I/O ST
RB7 11 8 16 13 I/O ST
RB8 12 9 17 14 I/O ST
RB9 13 10 18 15 I/O ST
RB10 — — 21 18 I/O ST
RB11 — — 22 19 I/O ST
RB12 15 12 23 20 I/O ST
RB13 16 13 24 21 I/O ST
RB14 17 14 25 22 I/O ST
RB15 18 15 26 23 I/O ST
REFO 18 15 26 23 O — Reference Clock Output
RTCC 17 14 25 22 O — Real-Time Clock Alarm Output
SCK1 15 12 22 19 I/O ST SPI1 Serial Clock Input/Output
SCL1 12 9 17, 15(1)14, 12 (1)I/O I2C I2C1 Synchronous Serial Clock Input/Output
SDA1 13 10 18, 14(1)15, 11(1)I/O I2C I2C1 Data Input/Output
SDI1 17 14 21 18 I ST SPI1 Serial Data Input
SDO1 16 13 24 21 O — SPI1 Serial Data Output
SOSCI 9 6 11 8 I ANA Secondary Oscillator Input
SOSCO 10 7 12 9 O ANA Secondary Oscillator Output
SS1 18 15 26 23 I/O ST Slave Select Input/Frame Select Output (SPI1)
TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input
Buffer Description
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
PIC24F16KA102 FAMILY
DS39927C-page 16 2008-2011 Microchip Technology Inc.
T1CK 10 7 12 9 I ST Timer1 Clock
T2CK 18 15 26 23 I ST Timer2 Clock
T3CK 18 15 26 23 I ST Timer3 Clock
U1CTS 12 9 17 14 I ST UART1 Clear to Send Input
U1RTS 13 10 18 15 O — UART1 Request to Send Output
U1RX 6 3 6 3 I ST UART1 Receive
U1TX 11 8 16 13 O — UART1 Transmit Output
VDD 20 17 13, 28 10, 25 P — Positive Supply for Peripheral Digital Logic and
I/O Pins
VPP 1 18 1 26 P — Programming Mode Entry Voltage
VREF- 3 20 3 28 I ANA A/D and Comparator Reference Voltage (low)
Input
VREF+ 2 19 2 27 I ANA A/D and Comparator Reference Voltage (high)
Input
VSS 19 16 8, 27 5, 24 P — Ground Reference for Logic and I/O Pin
TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Input
Buffer Description
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
2008-2011 Microchip Technology Inc. DS39927C-page 17
PIC24F16KA102 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC24F16KA102 family family
of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
The following pins must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Power Supply Pins”)
•All AV
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
•MCLR
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
•V
CAP pins
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
These pins must also be connected if they are being
used in the end application:
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
PIC24FXXKXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
VDD
MCLR
VCAP
R2
C7
C2(2)
C3(2)
C4(2)
C5(2)
C6(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 16V tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pin
(VCAP)” for explanation of VCAP pin
connections.
2: The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
3: Some PIC24F K parts do not have a
regulator.
(1)
(3)
PIC24F16KA102 FAMILY
DS39927C-page 18 2008-2011 Microchip Technology Inc.
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
•Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
•Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
Note 1: R1  10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R2  470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
PIC24FXXKXX
JP
2008-2011 Microchip Technology Inc. DS39927C-page 19
PIC24F16KA102 FAMILY
2.4 Voltage Regulator Pin (V CAP)
Some of the PIC24F K devices have an internal voltage
regulator. These devices have the voltage regulator
output brought out on the VCAP pin. On the PIC24F K
devices with regulators, a low-ESR (< 5Ω) capacitor is
required on the VCAP pin to stabilize the voltage
regulator output. The VCAP pin must not be connected to
VDD and must use a capacitor of 10 µF connected to
ground. The type can be ceramic or tantalum. Suitable
examples of capacitors are shown in Table 2-1.
Capacitors with equivalent specifications can be used.
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
The placement of this capacitor should be close to VCAP.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 29.0 “Electrical
Characteristics” for additional information.
Refer to Section 29.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
Note: This section applies only to PIC24F K
devices with an on-chip voltage regulator.
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100 1000 10,000
Frequ en cy (MH z)
ESR ()
Note: Typical data measurement at 25°C, 0V DC bias.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS
Make Part # Nominal
Capacitance Base Tolerance Rated Voltage Temp. Range
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC
Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC
Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC
PIC24F16KA102 FAMILY
DS39927C-page 20 2008-2011 Microchip Technology Inc.
2.4.1 CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the inter-
nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler-
ance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.
FIGURE 2-4: DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
16V for the 3.3V or 2.5V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 27.0 “Development Support”.
-80
-70
-60
-50
-40
-30
-20
-10
0
10
5 1011121314151617
DC Bias Voltage (VDC)
Capacitance Change (%)
01234 67 89
16V Capacitor
10V Capacitor
6.3V Capacitor
2008-2011 Microchip Technology Inc. DS39927C-page 21
PIC24F16KA102 FAMILY
2.6 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to
Section 9.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other
signals, in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
•AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
•AN949, “Ma king Your Oscillator Work ”
2.7 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-5: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
GND
`
`
`
OSC1
OSC2
T1OSO
T1OS I
Copper Pour Primary Oscillator
Crystal
Timer1 Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
T1 Oscillator: C1 T1 Oscillator: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
PIC24F16KA102 FAMILY
DS39927C-page 22 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 23
PIC24F16KA102 FAMILY
3.0 CPU
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as a
Software Stack Pointer (SSP) for interrupts and calls.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary of either program memory or data
EEPROM memory defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward
compatibility. All PIC18 instructions and addressing
modes are supported, either directly, or through simple
macros. Many of the ISA enhancements have been
driven by compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing trinary operations (that is,
A + B = C) to be executed in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
A block diagram of the CPU is illustrated in Figure 3-1.
3.1 Programmer’s Model
Figure 3-2 displays the programmer’s model for the
PIC24F. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions.
Table 3-1 provides a description of each register. All
registers associated with the programmer’s model are
memory mapped.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
CPU, refer to the “PIC24F Family
Reference Manual”, Section 2. “CPU”
(DS39703).
PIC24F16KA102 FAMILY
DS39927C-page 24 2008-2011 Microchip Technology Inc.
FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
TABLE 3-1: CPU CORE REGISTERS
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
16 x 16
W Register Array
Divide
Support
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory
Data Latch
Address Bus
16
Literal Data
16 16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
Data EEPROM
Register(s) Name Description
W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
PSVPAG Program Space Visibility Page Address Register
RCOUNT Repeat Loop Counter Register
CORCON CPU Control Register
2008-2011 Microchip Technology Inc. DS39927C-page 25
PIC24F16KA102 FAMILY
FIGURE 3-2: PROGRAMME R’S MODEL
NOVZ C
TBLPAG
22 0
7 0
015
Program Counter
Table Memory Page
ALU STATUS Register (SR)
Working/Address
Registers
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer
Stack Pointer
PSVPAG
7 0 Program Space Visibility
RA
0
RCOUNT
15 0 Repeat Loop Counter
SPLIM Stack Pointer Limit
SRL
Registers or bits shadowed for PUSH.S and POP.S instructions.
0
0
Page Address Register
15 0
CPU Control Register (CORCON)
SRH
W14
W15
DC IPL
210
———————
IPL3 PSV
————————————
——
PC
Divider Working Registers
Multiplier Registers
15 0
Value Register
Address Register
Register
PIC24F16KA102 FAMILY
DS39927C-page 26 2008-2011 Microchip Technology Inc.
3.2 CPU Control Registers
REGISTER 3-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HSC
— — — — — — —DC
bit 15 bit 8
R/W-0, HSC(1)R/W-0, HSC(1)R/W-0, HSC(1)R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
IPL2(2)IPL1(2)IPL0(2)RA N OV Z C
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU interrupt priority level is 7 (15); user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU Interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1 Z: ALU Zero bit
1 = An operation, which effects the Z bit, has set it at some time in the past
0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit (MSb) of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
2008-2011 Microchip Technology Inc. DS39927C-page 27
PIC24F16KA102 FAMILY
3.3 Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of
addition, subtraction, bit shifts and logic operations.
Unless otherwise mentioned, arithmetic operations are
2’s complement in nature. Depending on the operation,
the ALU may affect the values of the Carry (C), Zero
(Z), Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
division for 16-bit divisor.
3.3.1 MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
REGISTER 3-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0
————IPL3
(1)PSV — —
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
bit 1-0 Unimplemented: Read as ‘0’
Note 1: User interrupts are disabled when IPL3 = 1.
PIC24F16KA102 FAMILY
DS39927C-page 28 2008-2011 Microchip Technology Inc.
3.3.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.3.3 MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided below in Tab le 3 -2 .
TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Instruction Description
ASR Arithmetic shift right source register by one or more bits.
SL Shift left source register by one or more bits.
LSR Logical shift right source register by one or more bits.
2008-2011 Microchip Technology Inc. DS39927C-page 29
PIC24F16KA102 FAMILY
4.0 MEMORY ORGANIZATION
As with Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and busing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the PIC24F
devices is 4M instructions. The space is addressable by
a 24-bit value derived from either the 23-bit Program
Counter (PC) during program execution, or from a table
operation or data space remapping, as described in
Section 4.3 “Interfacing Program and Data Memory
Spaces”.
The user access to the program memory space is
restricted to the lower half of the address range
(000000h to 7FFFFFh). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
Memory maps for the PIC24F16KA102 family of
devices are displayed in Figure 4-1.
FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES
000000h
0000FEh
000002h
000100h
F80010h
F80012h
FEFFFEh
FFFFFFh
000004h
000200h
0001FEh
000104h
Configuration Memory Space User Memory Space
Note: Memory areas are not displayed to scale.
Reset Address
Device Config Registers
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F16KA10X
FF0000h
F7FFFEh
F80000h
800000h
7FFFFFh
Reserved
Unimplemented
Read ‘0’
Reset Address
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F08KA10X
Device Config Registers
Reserved
Unimplemented
Read ‘0’
0015FEh
002BFE
User Flash
Program Memory
(5632 instructions)
7FFE00h
Data EEPROM
Data EEPROM
Flash
Program Memory
(2816 instructions)
PIC24F16KA102 FAMILY
DS39927C-page 30 2008-2011 Microchip Technology Inc.
4.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
00000h and 000200h for hard coded program
execution vectors. A hardware Reset vector is provided
to redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
PIC24F devices also have two Interrupt Vector
Tables, located from 000004h to 0000FFh, and
000104h to 0001FFh. These vector tables allow each
of the many device interrupt sources to be handled
by separate ISRs. Section 8.1 “Interrupt Vector
(IVT) T able” discusses the Interrupt Vector Tables in
more detail.
4.1.3 DATA EEPROM
In the PIC24F16KA102 family, the data EEPROM is
mapped to the top of the user program memory space,
starting at address, 7FFE00, and expanding up to
address, 7FFFFF.
The data EEPROM is organized as 16-bit wide memory
and 256 words deep. This memory is accessed using
table read and write operations similar to the user code
memory.
4.1.4 DEVICE CONFIGURATION WORDS
Table 4-1 provides the addresses of the device Config-
uration Words for the PIC24F16KA102 family. Their
location in the memory map is displayed in Figure 4-1.
Refer to Section 26.1 “Configuration Bits” for more
information on device Configuration Words.
TABLE 4-1: DEVICE CONFIGURATION
WORDS FOR PIC24F16KA102
FAMILY DEVICE S
FIGURE 4-2: PROGRAM MEMORY ORGANIZATION
Configuration Word Configuration Word
Addresses
FBS F80000
FGS F80004
FOSCSEL F80006
FOSC F80008
FWDT F8000A
FPOR F8000C
FICD F8000E
FDS F80010
0816
PC Address
000000h
000002h
000004h
000006h
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘
0
’)
least significant word
most significant word
Instruction Width
000001h
000003h
000005h
000007h
msw
Address (lsw Address)
2008-2011 Microchip Technology Inc. DS39927C-page 31
PIC24F16KA102 FAMILY
4.2 Data Address Space
The PIC24F core has a separate, 16-bit wide data
memory space, addressable as a single linear range.
The data space is accessed using two Address
Generation Units (AGUs), one each for read and write
operations. The data space memory map is displayed
in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the Program Space Visibility (PSV) area
(see Section 4.3.3 “Reading Data From Program
Memory Using Program Spa ce Visibility”).
PIC24F16KA102 family devices implement a total of
768 words of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all the
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES
0000h
07FEh
FFFEh
LSB
Address
LSBMSB
MSB
Address
0001h
07FFh
0DFFh
FFFFh
8001h 8000h
7FFFh
0801h 0800h Near
0DFEh
SFR
SFR Space
Data RAM
7FFFh
Program Space
Visibility Area
Note: Data memory areas are not shown to scale.
1FFEh
1FFF
Space
Data Space
Implemented
Data RAM
Unimplemented
Read as ‘0’
PIC24F16KA102 FAMILY
DS39927C-page 32 2008-2011 Microchip Technology Inc.
4.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recog-
nizes that Post-Modified Register Indirect Addressing
mode [Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, the data
memory and the registers are organized as two
parallel, byte-wide entities with shared (word) address
decode, but separate write lines. Data byte writes only
write to the corresponding side of the array or register,
which matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a mis-
aligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed, but the write
will not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
LSB; the MSB is not modified.
A Sign-Extend instruction (SE) is provided to allow the
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3 NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing (MDA) with a 16-bit address field. For
PIC24F16KA102 family devices, the entire
implemented data memory lies in Near Data Space
(NDS).
4.2.4 SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they
control and are generally grouped together by that
module. Much of the SFR space contains unused
addresses; these are read as ‘0’. The SFR space,
where the SFRs are actually implemented, is provided
in Ta b l e 4 - 2 . Each implemented area indicates a
32-byte region where at least one address is
implemented as an SFR. A complete listing of
implemented SFRs, including their addresses, is
provided in Table 4-3 through Ta b l e 4 - 2 3 .
TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0
000h Core ICN Interrupts —
100h Timers Capture —Compare———
200h I2C™ UART SPI ——I/O
300h A/D/CMTU — — — — — —
400h — — — — — — — —
500h — — — — — — — —
600h — RTC/Comp CRC — —
700h —— System/DS/HLVD NVM/PMD — — — —
Legend: — = No implemented SFRs in this block.
2008-2011 Microchip Technology Inc. DS39927C-page 33
PIC24F16KA102 FAMILY
TABLE 4-3: CPU CORE REGISTERS MAP
File
Name AddrBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0All
Resets
WREG0 0000 Working Register 0 0000
WREG1 0002 Working Register 1 0000
WREG2 0004 Working Register 2 0000
WREG3 0006 Working Register 3 0000
WREG4 0008 Working Register 4 0000
WREG5 000A Working Register 5 0000
WREG6 000C Working Register 6 0000
WREG7 000E Working Register 7 0000
WREG8 0010 Working Register 8 0000
WREG9 0012 Working Register 9 0000
WREG10 0014 Working Register 10 0000
WREG11 0016 Working Register 11 0000
WREG12 0018 Working Register 12 0000
WREG13 001A Working Register 13 0000
WREG14 001C Working Register 14 0000
WREG15 001E Working Register 15 0800
SPLIM 0020 Stack Pointer Limit Value Register xxxx
PCL 002E Program Counter Low Byte Register 0000
PCH 0030 ———————— Program Counter Register High Byte 0000
TBLPAG 0032 ———————— Table Memory Page Address Register 0000
PSVPAG 0034 ———————— Program Space Visibility Page Address Register 0000
RCOUNT 0036 REPEAT Loop Counter Register xxxx
SR 0042 ——————— DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 ———————————— IPL3 PSV — — 0000
DISICNT 0052 —— Disable Interrupts Counter Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24F16KA102 FAMILY
DS39927C-page 34 2008-2011 Microchip Technology Inc.
TABLE 4-4: ICN REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 1 3 Bit 1 2 Bit 11 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CNEN1 0060 CN15IE(1)CN14IE CN13IE CN12IE CN11IE(1)—CN9IE CN8IE CN7IE(1)CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE — CN27IE(1)—— CN24IE(1)CN23IE CN22IE CN21IE ————CN16IE
(1)0000
CNPU1 0068 CN15PUE(1)CN14PUE CN13PUE CN12PUE CN11PUE(1)— CN9PUE CN8PUE CN7PUE(1)CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE —CN27PUE
(1)——CN24PUE
(1)CN23PUE CN22PUE CN21PUE ———— CN16PUE(1)0000
CNPD1 0070 CN15PDE(1)CN14PDE CN13PDE CN12PDE CN11PDE(1)— CN9PDE CN8PDE CN7PDE(1)CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000
CNPD2 0072 — CN30PDE CN29PDE —CN27PDE
(1)——CN24PDE
(1)CN23PDE CN22PDE CN21PDE ———— CN16PDE(1)0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are not implemented in 20-pin devices.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000
IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF — — — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 U2TXIF U2RXIF INT2IF — — — — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS3 008A —RTCIF— — — — — — — — — — — — — — 0000
IFS4 008C ——CTMUIF— — — —HLVDIF— — — — CRCIF U2ERIF U1ERIF —0000
IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE — — — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 U2TXIE U2RXIE INT2IE — — — — — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC3 009A —RTCIE— — — — — — — — — — — — — — 0000
IEC4 009C ——CTMUIE— — — —HLVDIE— — — — CRCIE U2ERIE U1ERIE —0000
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4444
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 —T3IP2T3IP1T3IP04444
IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444
IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004
IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — — — — 4440
IPC15 00C2 ————— RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400
IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440
IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004
IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040
INTTREG 00E0 CPUIRQ —VHOLD— ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2011 Microchip Technology Inc. DS39927C-page 35
PIC24F16KA102 FAMILY
TABLE 4-6: TIMER REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register 0000
PR1 0102 Timer1 Period Register FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 — TSYNC TCS —0000
TMR2 0106 Timer2 Register 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000
TMR3 010A Timer3 Register 0000
PR2 010C Timer2 Period Register FFFF
PR3 010E Timer3 Period Register FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 T32 —TCS—0000
T3CON 0112 TON —TSIDL—————— TGATE TCKPS1 TCKPS0 ——TCS—0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7: INPUT CAPTURE REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IC1BUF 0140 Input Capture 1 Register FFFF
IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8: OUTPUT COMPARE REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
OC1RS 0180 Output Compare 1 Secondary Register FFFF
OC1R 0182 Output Compare 1 Register FFFF
OC1CON 0184 ——OCSIDL———————— OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24F16KA102 FAMILY
DS39927C-page 36 2008-2011 Microchip Technology Inc.
TABLE 4-9: I2C™ REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000
I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF
I2C1BRG 0204 — — — — — — — I2C1 Baud Rate Generator Register 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A PSR/WRBF TBF 0000
I2C1ADD 020A — — — — — — I2C1 Address Register 0000
I2C1MSK 020C — — — — — — AMSK9 AMSK8 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in h.5adecimal.
TABLE 4-10: UART REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register 0000
U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UART2 Transmit Register 0000
U2RXREG 0236 — — — — — — — UART2 Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: SPI REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
SPI1STAT 0240 SPIEN — SPISIDL —— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
SPI1BUF 0248 SPI1 Transmit/Receive Buffer 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2011 Microchip Technology Inc. DS39927C-page 37
PIC24F16KA102 FAMILY
TABLE 4-12: PORTA REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5(1)Bit 4 Bit 3 Bit 2 Bit 1 B it 0 All
Resets
TRISA 02C0 — — — — — — — — TRISA7(4)TRISA6 — TRISA4 TRISA3(5,6)TRISA2(5)TRISA1 TRISA0 00DF
PORTA 02C2 — — — — — — — — RA7(4)RA6 RA5 RA4(3)RA3(5,6)RA2(5)RA1(2)RA0(2)xxxx
LATA 02C4 — — — — — — — — LATA7(4)LATA6 —LATA4LATA3
(5,6)LATA2(5)LATA1 LATA0 xxxx
ODCA 02C6 — — — — — — — — ODA7(4)ODA6 — ODA4 ODA3(5,6)ODA2(5)ODA1 ODA0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This bit is available only when MCLRE = 0.
2: A read of RA1 and RA0 results in ‘0’ when debug is active on the PGC2/PGD2 pin.
3: A read of RA4 results in ‘0’ when debug is active on the PGC3/PGD3 pin.
4: These bits are not implemented in 20-pin devices.
5: These bits are available only when the primary oscillator is disabled (POSCMD<1:0> = 00); otherwise read as ‘0’.
6: These bits are available only when the primary oscillator is disabled or EC mode is selected (POSCMD<1:0> = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise read as ‘0’.
TABLE 4-13: PORTB REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11(3)TRISB10(3)TRISB9 TRISB8 TRISB7 TRISB6(3)TRISB5(3)TRISB4 TRISB3(3)TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA RB15 RB14 RB13 RB12 RB11(3)RB10(3)RB9 RB8 RB7 RB6(3)RB5(3)RB4(2)RB3(3)RB2 RB1(1)RB0(1)xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11(3)LATB10(3)LATB9 LATB8 LATB7 LATB6(3)LATB5(3)LATB4 LATB3(3)LATB2 LATB1 LATB0 xxxx
ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: A read of RB1 and RB0 results in ‘0’ when debug is active on the PGEC1/PGED1 pins.
2: A read of RB4 results in ‘0’ when debug is active on the PGEC3/PGED3 pins.
3: PORTB bits, 11, 10, 6, 5 and 3, are not implemented in 20-pin devices.
TABLE 4-14: PAD CONFIGURATION REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
PADCFG1 02FC ——————————— SMBUSDEL OC1TRIS RTSECSEL1 RTSECSEL0 —0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24F16KA102 FAMILY
DS39927C-page 38 2008-2011 Microchip Technology Inc.
TABLE 4-15: A/D REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
ADC1BUF0 0300 A/D Data Buffer 0 xxxx
ADC1BUF1 0302 A/D Data Buffer 1 xxxx
ADC1BUF2 0304 A/D Data Buffer 2 xxxx
ADC1BUF3 0306 A/D Data Buffer 3 xxxx
ADC1BUF4 0308 A/D Data Buffer 4 xxxx
ADC1BUF5 030A A/D Data Buffer 5 xxxx
ADC1BUF6 030C A/D Data Buffer 6 xxxx
ADC1BUF7 030E A/D Data Buffer 7 xxxx
ADC1BUF8 0310 A/D Data Buffer 8 xxxx
ADC1BUF9 0312 A/D Data Buffer 9 xxxx
ADC1BUFA 0314 A/D Data Buffer 10 xxxx
ADC1BUFB 0316 A/D Data Buffer 11 xxxx
ADC1BUFC 0318 A/D Data Buffer 12 xxxx
ADC1BUFD 031A A/D Data Buffer 13 xxxx
ADC1BUFE 031C A/D Data Buffer 14 xxxx
ADC1BUFF 031E A/D Data Buffer 15 xxxx
AD1CON1 0320 ADON —ADSIDL— — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 —— ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL —CSCNA——BUFS— SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC —— SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA —— CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1PCFG 032C — — — PCFG12 PCFG11 PCFG10 ———— PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 — — — CSSL12 CSSL11 CSSL10 ———— CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: CTMU REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bi t 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bi t 4 B it 3 Bit 2 Bit 1 Bit 0 All
Resets
CTMUCON 033C CTMUEN —CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000
CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2011 Microchip Technology Inc. DS39927C-page 39
PIC24F16KA102 FAMILY
TABLE 4-17: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<15:0> xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<15:0> xxxx
RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: DUAL COMPARATOR REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CMSTAT 0630 CMSIDL — — — — — C2EVT C1EVT — — — — — — C2OUT C1OUT 0000
CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0634 CON COE CPOL CLPWR —— CEVT COUT EVPOL1 EVPOL0 —CREF—— CCH1 CCH0 0000
CM2CON 0636 CON COE CPOL CLPWR —— CEVT COUT EVPOL1 EVPOL0 —CREF—— CCH1 CCH0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: CRC REGISTER MAP
File
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CRCCON 0640 —— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0040
CRCXOR 0642 X<15:1> —0000
CRCDAT 0644 CRC Data Input Register 0000
CRCWDAT 0646 CRC Result Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24F16KA102 FAMILY
DS39927C-page 40 2008-2011 Microchip Technology Inc.
TABLE 4-20: CLOCK CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RCON 0740 TRAPR IOPUWR SBOREN —— DPSLP — PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK —LOCK —CF— SOSCEN OSWEN (Note 2)
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3140
OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000
REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
HLVDCON 0756 HLVDEN —HLSIDL— — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
TABLE 4-21: DEEP SLEEP REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets(1)
DSCON 0758 DSEN — — — — — — — — — — — — — DSBOR RELEASE 0000
DSWAKE 075A — — — — — — —DSINT0DSFLT —— DSWDT DSRTCC DSMCLR — DSPOR 0000
DSGPR0 075C Deep Sleep General Purpose Register 0 0000
DSGPR1 075E Deep Sleep General Purpose Register 1 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Deep Sleep registers are only reset on a VDD POR event.
TABLE 4-22: NVM REGISTER MAP
File Na me Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY 0766 — — — — — — — — NVMKEY7 NVMKEY6 NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-23: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
PMD1 0770 — — T3MD T2MD T1MD — — — I2C1MD U2MD U1MD —SPI1MD ——ADC1MD0000
PMD2 0772 — — — — — — —IC1MD———————OC1MD0000
PMD3 0774 — — — — — CMPMD RTCCMD —CRCPMD ———————0000
PMD4 0776 — — — — — — — — — — — EEMD REFOMD CTMUMD HLVDMD —0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2008-2011 Microchip Technology Inc. DS39927C-page 41
PIC24F16KA102 FAMILY
4.2.5 SOFTWARE STACK
In addition to its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as depicted in
Figure 4-4.
For a PC push during any CALL instruction, the MSB of
the PC is Zero-Extended before the push, ensuring that
the MSB is always clear.
The Stack Pointer Limit Value (SPLIM) register,
associated with the Stack Pointer, sets an upper
address boundary for the stack. SPLIM is uninitialized
at Reset. As is the case for the Stack Pointer,
SPLIM<0> is forced to ‘0’ as all stack operations must
be word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM
register are equal, and a push operation is performed,
a stack error trap will not occur. The stack error trap will
occur on a subsequent push operation.
Thus, for example, if it is desirable to cause a stack
error trap when the stack grows beyond address, 0DF6
in RAM, initialize the SPLIM with the value, 0DF4.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
FIGURE 4-4: CALL STACK FRAME
4.3 Interfaci ng Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Apart from the normal execution, the PIC24F
architecture provides two methods by which the
program space can be accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space, PSV
Table instructions allow an application to read or write
small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word (lsw) of the program word.
4.3.1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit (MSb) of
TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG<7> = 0) or the configuration
memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
define a 16K word page in the program space. When
the MSb of the EA is ‘1’, PSVPAG is concatenated with
the lower 15 bits of the EA to form a 23-bit program
space address. Unlike the table operations, this limits
remapping operations strictly to the user memory area.
See Table 4 -24 and Figure 4-5 to know how the
program EA is created for table operations and
remapping accesses from the data EA. Here, P<23:0>
refers to a program space word, whereas D<15:0>
refers to a data space word.
Note: A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
Note: A write to the SPLIM register should not
be immediately followed by an indirect
read operation using W15.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
0000h
PC<22:16>
POP : [--W15]
PUSH : [W15++]
PIC24F16KA102 FAMILY
DS39927C-page 42 2008-2011 Microchip Technology Inc.
TABLE 4-24: PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Access Type Access
Space Prog r am S pace Addr ess
<23> <22:16> <15> <14:1> <0>
Instruction Access
(Code Execution)
User 0PC<22:1> 0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
User TBLPAG<7:0> Data EA<15:0>
0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read)
User 0PSVPAG<7:0>(2)Data EA<14:0>(1)
0 xxxx xxxx xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
2: PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) on
the PIC24F16KA102 family.
0Program Counter
23 Bits
1
PSVPAG
8 Bits
EA
15 Bits
Program Counter(1)
Select
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
0
1/0
User/Configuration
Table Operations(2)
Program Space Visibility(1)
Space Select
24 Bits
23 Bits
(Remapping)
1/0
0
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the
program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration
memory space.
2008-2011 Microchip Technology Inc. DS39927C-page 43
PIC24F16KA102 FAMILY
4.3.2 DATA ACCESS FROM PROGRAM
MEMORY AND DATA EEPROM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program memory without going
through data space. It also offers a direct method of
reading or writing a word of any address within data
EEPROM memory. The TBLRDH and TBLWTH instruc-
tions are the only method to read or write the upper 8 bits
of a program space word as data.
The PC is incremented by 2 for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (byte select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Note: The TBLRDH and TBLWTH instructions are not
used while accessing data EEPROM memory.
Note: Only table read operations will execute in the
configuration memory space, and only then, in
implemented areas, such as the Device ID.
Table write operations are not allowed.
081623
00000000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
23 15 0
TBLPAG
00
000000h
800000h
002BFEh
Program Space Data EA<15:0>
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register. Only read
operations are provided; write operations are also valid in the
user memory area.
PIC24F16KA102 FAMILY
DS39927C-page 44 2008-2011 Microchip Technology Inc.
4.3.3 READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into an 8K word page (in PIC24F08KA1XX
devices) and a 16K word page (in PIC24F16KA1XX
devices) of the program space. This provides
transparent access of stored constant data from the
data space without the need to use special instructions
(i.e., TBLRDL/H).
Program space access through the data space occurs
if the MSb of the data space, EA, is ‘1’, and PSV is
enabled by setting the PSV bit in the CPU Control
(CORCON<2>) register. The location of the program
memory space to be mapped into the data space is
determined by the Program Space Visibility Page
Address register (PSVPAG). This 8-bit register defines
any one of 256 possible pages of 16K words in pro-
gram space. In effect, PSVPAG functions as the upper
8 bits of the program memory address, with the 15 bits
of the EA functioning as the lower bits.
By incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads from this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111 1111’ or ‘0000
0000’ to force a NOP. This prevents possible issues
should the area of code ever be accidentally executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION
Note: PSV access is temporarily disabled during
table reads/writes.
23 15 0
PSVPAG
Data Space
Program Space
0000h
8000h
FFFFh
00 000000h
800000h
002BFEh
When CORCON<2> = 1 and EA<15> = 1:
PSV Area
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
Data EA<14:0>
...while the lower 15 bits
of the EA specify an exact
address within the PSV
area. This corresponds
exactly to the same lower
15 bits of the actual
program space address.
2008-2011 Microchip Technology Inc. DS39927C-page 45
PIC24F16KA102 FAMILY
5.0 FLASH PROGRAM MEMORY
The PIC24FJ64GA family of devices contains internal
Flash program memory for storing and executing appli-
cation code. The memory is readable, writable and
erasable when operating with VDD over 1.8V.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24F16KA102 device to be serially
programmed while in the end application circuit. This is
simply done with two lines for the programming clock
and programming data (which are named PGCx and
PGDx, respectively), and three other lines for power
(VDD), ground (VSS) and Master Clear/Program Mode
Entry Voltage (MCLR/VPP). This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
Real-Time Self-Programming (RTSP) is accomplished
using TBLRD (table read) and TBLWT (table write)
instructions. With RTSP, the user may write program
memory data in blocks of 32 instructions (96 bytes) at a
time, and erase program memory in blocks of 32, 64 and
128 instructions (96,192 and 384 bytes) at a time.
The NVMOP<1:0> (NVMCON<1:0>) bits decide the
erase block size.
5.1 Table Instruct ions and Flash
Programming
Regardless of the method used, Flash memory
programming is done with the table read and write
instructions. These allow direct read and write access to
the program memory space from the data memory while
the device is in normal operating mode. The 24-bit target
address in the program memory is formed using the
TBLPAG<7:0> bits and the Effective Address (EA) from
a W register, specified in the table instruction, as
depicted in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Flash Pro-
gramming, refer to the “PIC24F Family
Reference Manual”, S ection 4. “Program
Memory” (DS39715).
24 Bits
Program
TBLPAG Reg
8 Bits 16 Bits
Using
Byte
24-Bit EA
1/0
Select
Table
Instruction
Counter
Using
User/Configuration
Space Select
Working Reg EA
0Program Counter
0
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DS39927C-page 46 2008-2011 Microchip Technology Inc.
5.2 RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 32 instructions or 96 bytes. RTSP allows
the user to erase blocks of 1 row, 2 rows and 4 rows
(32, 64 and 128 instructions) at a time and to program
one row at a time. It is also possible to program single
words.
The 1-row (96 bytes), 2-row (192 bytes) and 4-row
(384 bytes) erase blocks, and single row write block
(96 bytes) are edge-aligned, from the beginning of
program memory.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in holding
latches until the programming sequence is executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
32 TBLWT instructions are required to write the full row
of memory.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions to
load the buffers. Programming is performed by setting
the control bits in the NVMCON register.
Data can be loaded in any order and the holding
registers can be written to multiple times before
performing a write operation. Subsequent writes,
however, will wipe out any previous writes.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written. A programming cycle is required for
programming each row.
5.3 Enh a n c ed In - C ircuit Seria l
Programming
Enhanced ICSP uses an on-board bootloader, known
as the program executive, to manage the programming
process. Using an SPI data frame format, the program
executive can erase, program and verify program
memory. For more information on Enhanced ICSP, see
the device programming specification.
5.4 Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls the
blocks that need to be erased, which memory type is to
be programmed and when the programming cycle
starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 5.5 “Programming
Operations” for further details.
5.5 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared when
the operation is finished.
Note: Writing to a location multiple times without
erasing it is not recommended.
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REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
WR WREN WRERR PGMONLY(4)— — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ERASE NVMOP5(1)NVMOP4(1)NVMOP3(1)NVMOP2(1)NVMOP1(1)NVMOP0(1)
bit 7 bit 0
Legend: SO = Settable Only bit HC = Hardware Clearable bit
-n = Value at POR ‘1’ = Bit is set R = Readable bit W = Writable bit
‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15 WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 PGMONLY: Program Only Enable bit(4)
bit 11-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<5:0> on the next WR command
0 = Perform the program operation specified by NVMOP<5:0> on the next WR command
bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits(1)
Erase Operations (when ERASE bit is ‘1’):
1010xx = Erase entire boot block (including code-protected boot block)(2)
1001xx = Erase entire memory (including boot block, configuration block, general block)(2)
011010 = Erase 4 rows of Flash memory(3)
011001 = Erase 2 rows of Flash memory(3)
011000 = Erase 1 row of Flash memory(3)
0101xx = Erase entire configuration block (except code protection bits)
0100xx = Erase entire data EEPROM(4)
0011xx = Erase entire general memory block programming operations
0001xx = Write 1 row of Flash memory (when ERASE bit is ‘0’)(3)
Note 1: All other combinations of NVMOP<5:0> are no operation.
2: Available in ICSP™ mode only. Refer to device programming specification.
3: The address in the Table Pointer decides which rows will be erased.
4: This bit is used only while accessing data EEPROM.
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DS39927C-page 48 2008-2011 Microchip Technology Inc.
5.5.1 PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
The user can program one row of Flash program
memory at a time by erasing the programmable row.
The general process is:
1. Read a row of program memory
(32 instructions) and store in data RAM.
2. Update the program data in RAM with the
desired new data.
3. Erase a row (see Example 5-1):
a) Set the NVMOP bits (NVMCON<5:0>) to
‘011000’ to configure for row erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
4. Write the first 32 instructions from data RAM into
the program memory buffers (see Example 5-1).
5. Write the program block to Flash memory:
a) Set the NVMOP bits to ‘000100’ to
configure for row programming. Clear the
ERASE bit and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as
displayed in Example 5-5.
EXAMPLE 5-1: ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE
EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE
; Set up NVMCON for row erase operation
MOV #0x4058, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR), W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0] ; Set base address of erase block
DISI #5 ; Block all interrupts
for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
// C example using MPLAB C30
int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Variable located in Pgm Memory, declared as a
// glob al v a ri ab le
unsigned int offset;
//Set up pointer to the first memory location to be written
TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR
offset = __
builtin_tbloffset(&progAddr);
// Init iali ze lo wer w ord of addr ess
__builtin_tblwtl(offset, 0x0000); // Set base address of erase block
// with dumm y latc h wri te
NVMCON = 0x4058; // Initialize NVMCON
asm("DISI #5"); // Block all interrupts for next 5 instructions
__builtin_write_NVM(); // C30 function to perform unlock
// sequ ence and se t WR
2008-2011 Microchip Technology Inc. DS39927C-page 49
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EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE
EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE
; Set up NVMCON for row programming operations
MOV #0x4004, W0 ;
MOV W0, NVMCON ; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000, W0 ;
MOV W0, TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x1500, W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0, W2 ;
MOV #HIGH_BYTE_0, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1, W2 ;
MOV #HIGH_BYTE_1, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2, W2 ;
MOV #HIGH_BYTE_2, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
; 32nd_program_word
MOV #LOW_WORD_31, W2 ;
MOV #HIGH_BYTE_31, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0] ; Write PM high byte into program latch
// C example using MPLA B C30
#define NUM _INSTRUCTIO N_PER_ROW 64
int __attribu te__ ((spa ce(auto_psv ))) progAd dr = 0x1234 // Variabl e located in Pgm Memo ry
unsigned in t offset;
unsigned in t i;
unsigned in t progData[ 2*NUM_INST RUCTION_PE R_ROW]; // Buffer of data to write
//Set up NV MCON for ro w programm ing
NVMCON = 0x 4004; // Initialize N VMCON
//Set up po inter to th e first me mory locat ion to be w ritten
TBLPAG = __b uiltin_tbl page(&prog Addr); // Initialize PM Pag e Boundary SFR
offset = __
builtin_tbloffset(&progAddr);
// Initial ize lower word of add ress
//Perform T BLWT instru ctions to write nece ssary numbe r of latch es
for(i=0; i < 2*NUM_INS TRUCTION_P ER_ROW; i+ +)
{ __builtin_ tblwtl(off set, progDa ta[i++]); // Write to add ress low wo rd
__builtin_ tblwth(off set, progDa ta[i]); // Write to upper by te
offset = o ffset + 2; // Increment ad dress
}
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DS39927C-page 50 2008-2011 Microchip Technology Inc.
EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE
EXAMPLE 5-6: INITIATING A PROGRAM MING SEQUENCE – ‘C’ LANGUAGE CODE
DISI #5 ; Block all interrupts
for next 5 instructions
MOV #0x55, W0
MOV W0, NVMKEY ; Write the 55 key
MOV #0xAA, W1 ;
MOV W1, NVMKEY ; Write the AA key
BSET NVMCON, #WR ; Start the erase sequence
NOP ; 2 NOPs required after setting WR
NOP ;
BTSC NVMCON, #15 ; Wait for the sequence to be completed
BRA $-2 ;
// C example using MPLAB C30
asm("DISI #5"); // Block all interrupts for next 5 instructions
__builtin_write_NVM(); // Perform unlock sequence and set WR
2008-2011 Microchip Technology Inc. DS39927C-page 51
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6.0 DATA EEPROM MEMORY
The data EEPROM memory is a Nonvolatile Memory
(NVM), separate from the program and volatile data
RAM. Data EEPROM memory is based on the same
Flash technology as program memory, and is optimized
for both long retention and a higher number of
erase/write cycles.
The data EEPROM is mapped to the top of the user
program memory space, with the top address at
program memory address, 7FFE00h to 7FFFFFh. The
size of the data EEPROM is 256 words in
PIC24F16KA102 devices.
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable during normal operation over the
entire VDD range.
Unlike the Flash program memory, normal program
execution is not stopped during a data EEPROM
program or erase operation.
The data EEPROM programming operations are
controlled using the three NVM Control registers:
• NVMCON: Nonvolatile Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
• NVMADR: Nonvolatile Memory Address Register
6.1 NVMCON Register
The NVMCON register (Register 6-1) is also the pri-
mary control register for data EEPROM program/erase
operations. The upper byte contains the control bits
used to start the program or erase cycle, and the flag
bit to indicate if the operation was successfully
performed. The lower byte of NVMCOM configures the
type of NVM operation that will be performed.
6.2 NVMKEY Register
The NVMKEY is a write-only register that is used to
prevent accidental writes or erasures of data EEPROM
locations.
To start any programming or erase sequence, the
following instructions must be executed first, in the
exact order provided:
1. Write 55h to NVMKEY.
2. Write AAh to NVMKEY.
After this sequence, a write will be allowed to the
NVMCON register for one instruction cycle. In most
cases, the user will simply need to set the WR bit in the
NVMCON register to start the program or erase cycle.
Interrupts should be disabled during the unlock
sequence.
The MPLAB® C30 C compiler provides a defined library
procedure (builtin_write_NVM) to perform the
unlock sequence. Example 6-1 illustrates how the
unlock sequence can be performed with in-line
assembly.
EXAMPLE 6-1: DATA EEPROM UNLOCK SEQUENCE
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Data EEPROM, refer to the “PIC24F
Family Reference Manual”, Section 5.
“Data EEPROM” (DS39720).
//Disable Interrupts For 5 instructions
asm volatile ("disi #5");
//Issue Unlock Sequence
asm volatile ("mov #0x55, W0 \n"
"
mov W0, NVMKEY \n"
"mov #0xAA, W1 \n"
"mov W1, NVMKEY \n");
// Perform Write/Erase operations
asm volatile ("bset NVMCON, #WR \n"
"nop \n"
"nop \n");
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DS39927C-page 52 2008-2011 Microchip Technology Inc.
REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER
R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
WR WREN WRERR PGMONLY — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit S = Settable bit HC = Hardware Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit (program or erase)
1 = Initiates a data EEPROM erase or write cycle (can be set but not cleared in software)
0 = Write cycle is complete (cleared automatically by hardware)
bit 14 WREN: Write Enable bit (erase or program)
1 = Enable an erase or program operation
0 = No operation allowed (device clears this bit on completion of the write/erase operation)
bit 13 WRERR: Flash Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming
operation)
0 = The write operation completed successfully
bit 12 PGMONLY: Program Only Enable bit
1 = Write operation is executed without erasing target address(es) first
0 = Automatic erase-before-write: write operations are preceded automatically by an erase of target
address(es)
bit 11-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase Operation Select bit
1 = Perform an erase operation when WR is set
0 = Perform a write operation when WR is set
bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits
Erase Operations (when ERASE bit is ‘1’):
011010 = Erase 8 words
011001 = Erase 4 words
011000 = Erase 1 word
0100xx = Erase entire data EEPROM
Programming Operations (when ERASE bit is ‘0’):
001xx = Write 1 word
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6.3 NVM Address Register
As with Flash program memory, the NVM Address
Registers, NVMADRU and NVMADR, form the 24-bit
Effective Address (EA) of the selected row or word for
data EEPROM operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. These registers are not mapped into the
Special Function Register (SFR) space; instead, they
directly capture the EA<23:0> of the last table write
instruction that has been executed and selects the data
EEPROM row to erase. Figure 6-1 depicts the program
memory EA that is formed for programming and erase
operations.
Like program memory operations, the Least Significant
bit (LSb) of NVMADR is restricted to even addresses.
This is because any given address in the data
EEPROM space consists of only the lower word of the
program memory width; the upper word, including the
uppermost “phantom byte”, are unavailable. This
means that the LSb of a data EEPROM address will
always be ‘0’.
Similarly, the Most Significant bit (MSb) of NVMADRU
is always ‘0’, since all addresses lie in the user program
space.
FIGURE 6-1: DATA EEPROM ADDRESSING WITH TBLPAG AND NVM ADDRESS REGISTERS
6.4 Data EEPROM Operations
The EEPROM block is accessed using table read and
write operations, similar to those used for program
memory. The TBLWTH and TBLRDH instructions are not
required for data EEPROM operations, since the
memory is only 16 bits wide (data on the lower address
is valid only). The following programming operations
can be performed on the data EEPROM:
• Erase one, four or eight words
• Bulk erase the entire data EEPROM
• Write one word
• Read one word
The library procedures are used in the code examples
detailed in the following sections. General descriptions
of each process are provided for users who are not
using the C30 compiler libraries.
24-Bit PM Address
TBLPAG
NVMADR
W Register EA
7Fh xxxxh
0
0
NVMADRU
Note 1: Unexpected results will be obtained
should the user attempt to read the
EEPROM while a programming or erase
operation is underway.
2: The C30 C compiler includes library
procedures to automatically perform the
table read and table write operations,
manage the Table Pointer and write
buffers, and unlock and initiate memory
write sequences. This eliminates the
need to create assembler macros or time
critical routines in C for each application.
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DS39927C-page 54 2008-2011 Microchip Technology Inc.
6.4.1 ERASE DATA EEPROM
The data EEPROM can be fully erased, or can be
partially erased, at three different sizes: one word, four
words or eight words. The bits, NVMOP<1:0>
(NVMCON<1:0>), decide the number of words to be
erased. To erase partially from the data EEPROM, the
following sequence must be followed:
1. Configure NVMCON to erase the required
number of words: one, four or eight.
2. Load TBLPAG and WREG with the EEPROM
address to be erased.
3. Clear NVMIF status bit and enable NVM
interrupt (optional).
4. Write the key sequence to NVMKEY.
5. Set the WR bit to begin erase cycle.
6. Either poll the WR bit or wait for the NVM
interrupt (NVMIF set).
A typical erase sequence is provided in Example 6-2.
This example shows how to do a one-word erase. Sim-
ilarly, a four-word erase and an eight-word erase can
be done. This example uses ‘C’ library procedures to
manage the Table Pointer (builtin_tblpage and
builtin_tbloffset) and the Erase Page Pointer
(builtin_tblwtl). The memory unlock sequence
(builtin_write_NVM) also sets the WR bit to initiate
the operation and returns control when complete.
EXAMPLE 6-2: SINGLE-WORD ERASE
int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM
unsigned int offset;
// Set up NVMCON to erase one word of data EEPROM
NVMCON = 0x4058;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer
offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address
__builtin_tblwtl(offset, 0); // Write EEPROM data to write latch
asm volatile ("disi #5"); // Disable Interrupts For 5 Instructions
__builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle
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6.4.1.1 Data EEPROM Bulk Erase
To erase the entire data EEPROM (bulk erase), the
address registers do not need to be configured
because this operation affects the entire data
EEPROM. The following sequence helps in performing
bulk erase:
1. Configure NVMCON to Bulk Erase mode.
2. Clear NVMIF status bit and enable NVM
interrupt (optional).
3. Write the key sequence to NVMKEY.
4. Set the WR bit to begin erase cycle.
5. Either poll the WR bit or wait for the NVM
interrupt (NVMIF is set).
A typical bulk erase sequence is provided in
Example 6-3.
6.4.2 SINGLE-WORD WRITE
To write a single word in the data EEPROM, the
following sequence must be followed:
1. Erase one data EEPROM word (as mentioned in
Section 6.4.1 “Erase Data EEPROM”) if the
PGMONLY bit (NVMCON<12>) is set to ‘1’.
2. Write the data word into the data EEPROM
latch.
3. Program the data word into the EEPROM:
- Configure the NVMCON register to program one
EEPROM word (NVMCON<5:0> =
0001xx
).
- Clear NVMIF status bit and enable NVM
interrupt (optional).
- Write the key sequence to NVMKEY.
- Set the WR bit to begin erase cycle.
- Either poll the WR bit or wait for the NVM
interrupt (NVMIF is set).
- To get cleared, wait until NVMIF is set.
A typical single-word write sequence is provided in
Example 6-4.
EXAMPLE 6-3: DATA EEPROM BULK ERASE
EXAMPLE 6-4: SINGLE-WORD WRITE TO DATA EEPROM
// Set up NVMCON to bulk erase the data EEPROM
NVMCON = 0x4050;
// Disable Interrupts For 5 Instructions
asm volatile ("disi #5");
// Issue Unlock Sequence and Start Erase Cycle
__builtin_write_NVM();
int __attribute__ ((space( eedata))) eeData = 0 x1234; // Variabl e located in E EPROM,declared as a
global variable.
int newData ; // New data to wri te to EEP ROM
unsigned in t offs et;
// Set up NVMCON to erase one word of data EE PROM
NVMCON = 0x4004;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage (&eeData); // Initialize EE Data page po inter
offset = __builtin_tbloffs et(&eeData); // Initizlize lower word of address
__builtin_tblwtl(offset, n ewData); // Write EEPROM data to write latch
asm volatile ("disi #5"); // Disable Interrupts Fo r 5 Instructions
__builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle
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DS39927C-page 56 2008-2011 Microchip Technology Inc.
6.4.3 READING THE DATA EEPROM
To read a word from data EEPROM, the table read
instruction is used. Since the EEPROM array is only
16 bits wide, only the TBLRDL instruction is needed.
The read operation is performed by loading TBLPAG
and WREG with the address of the EEPROM location,
followed by a TBLRDL instruction.
A typical read sequence, using the Table Pointer manage-
ment (builtin_tblpage and builtin_tbloffset)
and table read (builtin_tblrdl) procedures from the
C30 compiler library, is provided in Example 6-5.
Program Space Visibility (PSV) can also be used to
read locations in the data EEPROM.
EXAMPLE 6-5: READING THE DATA EEPROM USING THE TBLRD COMMAND
int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM,declared
// as a global variable
int data; // Data read from EEPROM
unsigned int offset;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer
offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address
data = __builtin_tblrdl(offset); // Write EEPROM data to write latch
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7.0 RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
•MCLR
: Pin Reset
•SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• Low-Power BOR/Deep Sleep BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
Figure 7-1 displays a simplified block diagram of the
Reset module.
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on a Power-on Reset (POR) and unchanged
by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A POR will clear all bits except for
the BOR and POR bits (RCON<1:0>) which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
FIGURE 7-1: RESE T SYSTEM BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on Resets, refer to the “PIC24F Family
Reference Manual”, Section 40. “Reset
with Programmable Brown-out Reset”
(DS39728).
Note: Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value, after a
device Reset, will be meaningful.
MCLR
VDD
V
DD
Rise
Detect
POR
Sleep or Idle
Brown-out
Reset
RESET
Instruction
WDT
Module
Glitch Filter
BOR
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
BOREN<1:0>
00
01
10
11
0
RCON<SBOREN>
SLEEP
1
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DS39927C-page 58 2008-2011 Microchip Technology Inc.
REGISTER 7-1: RCON: RESET CONTROL REGISTER(1)
R/W-0, HS R/W-0, HS R/W-0 U-0 U-0 R/C-0, HS R/W-0, HS R/W-0
TRAPR IOPUWR SBOREN —— DPSLP CM PMSLP
bit 15 bit 8
R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
EXTR SWR SWDTEN(2)WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13 SBOREN: Software Enable/Disable of BOR bit
1 = BOR is turned on in software
0 = BOR is turned off in software
bit 12-11 Unimplemented: Read as ‘0’
bit 10 DPSLP: Deep Sleep Mode Flag bit
1 = Deep Sleep has occurred
0 = Deep Sleep has not occurred
bit 9 CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch has occurred
0 = A Configuration Word Mismatch has not occurred
bit 8 PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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TABLE 7-1: RESE T FLAG BIT OPERATION
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred (the BOR is also set after a POR)
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event POR
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR
SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR
IDLE (RCON<2>) PWRSAV #IDLE Instruction POR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON <DSEN> set POR
Note: All Reset flag bits may be set or cleared by the user software.
REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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7.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
TABLE 7-2: OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENAB LED)
7.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the system Reset
signal, SYSRST
, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source Determinant
POR FNOSC Configuration bits
(FNOSC<10:8>)
BOR
MCLR COSC Control bits
(OSCCON<14:12>)
WDTO
SWR
Reset Type Clock Source SYSRST Delay System Clock
Delay Notes
POR(6)EC TPOR + TPWRT —1, 2
FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3
LPRC TPOR + TPWRT TLPRC 1, 2, 3
ECPLL TPOR + TPWRT TLOCK 1, 2, 4
FRCPLL TPOR + TPWRT TFRC + TLOCK 1, 2, 3, 4
XT, HS, SOSC TPOR+ TPWRT TOST 1, 2, 5
XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 4, 5
BOR EC TPWRT —2
FRC, FRCDIV TPWRT TFRC 2, 3
LPRC TPWRT TLPRC 2, 3
ECPLL TPWRT TLOCK 2, 4
FRCPLL TPWRT TFRC + TLOCK 2, 3, 4
XT, HS, SOSC TPWRT TOST 2, 5
XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4
All Others Any Clock — — None
Note 1: TPOR = Power-on Reset (POR) delay.
2: TPWRT = 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero.
3: TFRC and TLPRC = RC oscillator start-up times.
4: TLOCK = PLL lock time.
5: T
OST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.
2008-2011 Microchip Technology Inc. DS39927C-page 61
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7.2.1 POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer (OST) has not
expired (if a crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.2.2 FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
7.3 S pecial Function Register Reset
States
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in the Flash Configuration
Word (FOSCSEL); see Table 7-2. The RCFGCAL and
NVMCON registers are only affected by a POR.
7.4 Deep Sleep BOR (DSBOR)
Deep Sleep BOR is a very low-power BOR circuitry,
used when the device is in Deep Sleep mode. Due to
low-current consumption, accuracy may vary.
The DSBOR trip point is around 2.0V. DSBOR is
enabled by configuring DSBOREN (FDS<6>) = 1.
DSBOREN will re-arm the POR to ensure the device will
reset if VDD drops below the POR threshold.
7.5 Brown-out Reset (BOR)
The PIC24F16KA102 family devices implement a BOR
circuit, which provides the user several configuration
and power-saving options. The BOR is controlled by
the BORV<1:0> and BOREN<1:0> Configuration bits
(FPOR<6:5,1:0>). There are a total of four BOR
configurations, which are provided in Tab l e 7- 3.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below the set threshold point will
reset the device. The chip will remain in BOR until VDD
rises above threshold.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above the threshold. Then, it will keep the chip
in Reset for an additional time delay, TPWRT, if VDD drops
below the threshold while the Power-up Timer is running.
The chip goes back into a BOR and the Power-up Timer
will be initialized. Once VDD rises above the threshold,
the Power-up Timer will execute the additional time
delay.
BOR and the Power-up Timer are independently
configured. Enabling the BOR Reset does not
automatically enable the PWRT.
7.5.1 SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<13>). Setting SBOREN
enables the BOR to function as previously described.
Clearing the SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise, it is
read as ‘0’.
Placing BOR under software control gives the user the
additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor the incremental current that the BOR con-
sumes. While the BOR current is typically very small, it
may have some impact in low-power applications.
Note: Even when the BOR is under software
control, the BOR Reset voltage level is still
set by the BORV<1:0> Configuration bits;
it can not be changed in software.
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DS39927C-page 62 2008-2011 Microchip Technology Inc.
7.5.2 DETECTING BOR
When BOR is enabled, the BOR bit (RCON<1>) is
always reset to ‘1’ on any BOR or POR event. This
makes it difficult to determine if a BOR event has
occurred just by reading the state of BOR alone. A
more reliable method is to simultaneously check the
state of both POR and BOR. This assumes that the
POR and BOR bits are reset to ‘0’ in the software
immediately after any POR event. If the BOR bit is ‘1’
while the POR bit is ‘0’, it can be reliably assumed that
a BOR event has occurred.
7.5.3 DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, BOR remains under hard-
ware control and operates as previously described.
However, whenever the device enters Sleep mode,
BOR is automatically disabled. When the device
returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note: Even when the device exits from Deep
Sleep mode, both the POR and BOR are
set.
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8.0 INTERRUPT CONTROLLER
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the CPU. It has the following features:
• Up to eight processor exceptions and
software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
8.1 Interrupt Vector (IVT) Table
The IVT is displayed in Figure 8-1. The IVT resides in
the program memory, starting at location, 000004h.
The IVT contains 126 vectors, consisting of eight
non-maskable trap vectors, plus, up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with Vector 0 will take priority over interrupts
at any other vector address.
PIC24F16KA102 family devices implement
non-maskable traps and unique interrupts; these are
summarized in Ta b l e 8 - 1 and Tab l e 8- 2.
8.1.1 ALTERNATE INTERRUPT VECTOR
TAB LE (AIVT)
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as displayed in Figure 8-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run-time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the Program Counter (PC) to
zero. The microcontroller then begins program execu-
tion at location, 000000h. The user programs a GOTO
instruction at the Reset address, which redirects the
program execution to the appropriate start-up routine.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Interrupt Controller, refer to the
“PIC24F Family Reference Manual”,
Section 8. “Interrupts” (DS39707).
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
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DS39927C-page 64 2008-2011 Microchip Technology Inc.
FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE
Reset – GOTO Instruction 000000h
Reset – GOTO Address 000002h
Reserved 000004h
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 000014h
Interrupt Vector 1
—
—
—
Interrupt Vector 52 00007Ch
Interrupt Vector 53 00007Eh
Interrupt Vector 54 000080h
—
—
—
Interrupt Vector 116 0000FCh
Interrupt Vector 117 0000FEh
Reserved 000100h
Reserved 000102h
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0 000114h
Interrupt Vector 1
—
—
—
Interrupt Vector 52 00017Ch
Interrupt Vector 53 00017Eh
Interrupt Vector 54 000180h
—
—
—
Interrupt Vector 116
Interrupt Vector 117 0001FEh
Start of Code 000200h
Decreasing Natural Order Priority
Interrupt Vector Table (IVT)(1)
Alternate Interrupt Vector Table (AIVT)(1)
Note 1: See Table 8-2 for the interrupt vector list.
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TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS
TABLE 8-1: TRAP VECTOR DETAILS
Vector Number IVT Address AIVT Address Trap Source
0 000004h 000104h Reserved
1 000006h 000106h Oscillator Failure
2 000008h 000108h Address Error
3 00000Ah 00010Ah Stack Error
4 00000Ch 00010Ch Math Error
5 00000Eh 00010Eh Reserved
6 000010h 000110h Reserved
7 000012h 000112h Reserved
Interrupt Source Vector
Number IVT Address AIVT
Address
Interrupt Bit Locations
Flag Enable Priority
ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>
Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>
CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12>
CTMU 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4>
External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>
External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>
External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>
I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>
I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0>
Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>
Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>
HLVD High/Low-Voltage Detect 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC17<2:0>
NVM – NVM Write Complete 15 000032h 000132h IFS0<15> IEC0<15> IPC3<14:12>
Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>
Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8>
SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>
SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>
Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>
Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>
Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>
UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>
UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>
UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>
UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>
UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>
UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>
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8.3 Interrupt Control and Status
Registers
The PIC24F16KA102 family of devices implements a
total of 22 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFS0, IFS1, IFS3 and IFS4
• IEC0, IEC1, IEC3 and IEC4
• IPC0 through IPC5, IPC7 and IPC15 through
IPC19
•INTTREG
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the AIV table.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals, or external signal,
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The IPCx registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
The INTTREG register contains the associated inter-
rupt vector number and the new CPU interrupt priority
level, which are latched into the Vector Number
(VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence listed in
Table 8-2. For example, the INT0 (External Interrupt 0)
is depicted as having a vector number and a natural
order priority of 0. Thus, the INT0IF status bit is found
in IFS0<0>, the INT0IE enable bit in IEC0<0> and the
INT0IP<2:0> priority bits in the first position of IPC0
(IPC0<2:0>).
Although they are not specifically part of the interrupt
control hardware, two of the CPU control registers
contain bits that control interrupt functionality. The ALU
STATUS register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU interrupt
priority level. The user may change the current CPU
priority level by writing to the IPL bits.
The CORCON register contains the IPL3 bit, which
together with IPL<2:0>, also indicates the current CPU
priority level. IPL3 is a read-only bit so that the trap
events cannot be masked by the user’s software.
All interrupt registers are described in Register 8-1
through Register 8-21, in the following sections.
2008-2011 Microchip Technology Inc. DS39927C-page 67
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REGISTER 8-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC
— — — — — — — DC(1)
bit 15 bit 8
R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
IPL2(2,3)IPL1(2,3)IPL0(2,3)RA(1)N(1)OV(1)Z(1)C(1)
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU interrupt priority level is 7 (15); user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
Note 1: See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note: Bit 8 and Bits 4 through 0 are described in Section 3.0 “CPU”.
PIC24F16KA102 FAMILY
DS39927C-page 68 2008-2011 Microchip Technology Inc.
REGISTER 8-2: CORCON: CPU CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0
————IPL3
(2)PSV(1)— —
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 1-0 Unimplemented: Read as ‘0’
Note 1: See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Note: Bit 2 is described in Section 3.0 “CPU”.
2008-2011 Microchip Technology Inc. DS39927C-page 69
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REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
NSTDIS — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0
— — — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14-5 Unimplemented: Read as ‘0’
bit 4 MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
PIC24F16KA102 FAMILY
DS39927C-page 70 2008-2011 Microchip Technology Inc.
REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2
R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0
ALTIVT DISI — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use Alternate Interrupt Vector Table
0 = Use standard (default) vector table
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3 Unimplemented: Read as ‘0’
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
2008-2011 Microchip Technology Inc. DS39927C-page 71
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REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0
R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS
NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF
bit 15 bit 8
R/W-0, HS U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS
T2IF — — — T1IF OC1IF IC1IF INT0IF
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NVMIF: NVM Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 Unimplemented: Read as ‘0’
bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8 T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7 T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6-4 Unimplemented: Read as ‘0’
bit 3 T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
PIC24F16KA102 FAMILY
DS39927C-page 72 2008-2011 Microchip Technology Inc.
REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 U-0
U2TXIF U2RXIF INT2IF —————
bit 15 bit 8
U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0 R/W-0
— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13 INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5 Unimplemented: Read as ‘0’
bit 4 INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3 CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 CMIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2008-2011 Microchip Technology Inc. DS39927C-page 73
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REGISTER 8-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0
—RTCIF— — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-0 Unimplemented: Read as ‘0’
PIC24F16KA102 FAMILY
DS39927C-page 74 2008-2011 Microchip Technology Inc.
REGISTER 8-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS
——CTMUIF————HLVDIF
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0
———— CRCIF U2ERIF U1ERIF —
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CTMUIF: CTMU Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-9 Unimplemented: Read as ‘0’
bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 75
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REGISTER 8-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IE ——— T1IE OC1IE IC1IE INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NVMIE: NVM Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 Unimplemented: Read as ‘0’
bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8 T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7 T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request not is enabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
PIC24F16KA102 FAMILY
DS39927C-page 76 2008-2011 Microchip Technology Inc.
REGISTER 8-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
U2TXIE U2RXIE INT2IE —————
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IE CNIE CMIE MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-5 Unimplemented: Read as ‘0’
bit 4 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 CMIE: Comparator Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
2008-2011 Microchip Technology Inc. DS39927C-page 77
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REGISTER 8-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
—RTCIE— — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-0 Unimplemented: Read as ‘0’
PIC24F16KA102 FAMILY
DS39927C-page 78 2008-2011 Microchip Technology Inc.
REGISTER 8-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
——CTMUIE————HLVDIE
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0
———— CRCIE U2ERIE U1ERIE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CTMUIE: CTMU Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-9 Unimplemented: Read as ‘0’
bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 U2ERIE: UART2 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 U1ERIE: UART1 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 79
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REGISTER 8-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
PIC24F16KA102 FAMILY
DS39927C-page 80 2008-2011 Microchip Technology Inc.
REGISTER 8-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— T2IP2 T2IP1 T2IP0 — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 81
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REGISTER 8-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
PIC24F16KA102 FAMILY
DS39927C-page 82 2008-2011 Microchip Technology Inc.
REGISTER 8-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— NVMIP2 NVMIP1 NVMIP0 — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 NVMIP<2:0>: NVM Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-7 Unimplemented: Read as ‘0’
bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2008-2011 Microchip Technology Inc. DS39927C-page 83
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REGISTER 8-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CNIP2 CNIP1 CNIP0 —CMIP2CMIP1CMIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 MI2C1P<2:0>: Master I2C1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
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REGISTER 8-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — INT1IP2 INT1IP1 INT1IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2008-2011 Microchip Technology Inc. DS39927C-page 85
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REGISTER 8-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— INT2IP2 INT2IP1 INT2IP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
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DS39927C-page 86 2008-2011 Microchip Technology Inc.
REGISTER 8-20: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — RTCIP2 RTCIP1 RTCIP0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as ‘0’
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REGISTER 8-21: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— U1ERIP2 U1ERIP1 U1ERIP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
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REGISTER 8-22: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — HLVDIP2 HLVDIP1 HLVDIP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
REGISTER 8-23: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— CTMUIP2 CTMUIP1 CTMUIP0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
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REGISTER 8-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0
CPUIRQ —VHOLD— ILR3 ILR2 ILR1 ILR0
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
— VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will
happen when the CPU priority is higher than the interrupt priority)
0 = No interrupt request is left unacknowledged
bit 14 Unimplemented: Read as ‘0’
bit 13 VHOLD: Allows Vector Number Capture and Changes what Interrupt is Stored in VECNUM bit
1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current
interrupt
0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred
with higher priority than the CPU, even if other interrupts are pending)
bit 12 Unimplemented: Read as ‘0’
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt Vector pending is Number 135
•
•
•
0000001 = Interrupt Vector pending is Number 9
0000000 = Interrupt Vector pending is Number 8
PIC24F16KA102 FAMILY
DS39927C-page 90 2008-2011 Microchip Technology Inc.
8.4 Interrupt Setup Procedures
8.4.1 INITIALIZATION
To configure an interrupt source:
1. Set the NSTDIS Control bit (INTCON1<15>) if
nested interrupts are not desired.
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits, for all
enabled interrupt sources, may be programmed
to the same non-zero value.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
4. Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
8.4.2 INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address depends on the
programming language (i.e., C or assembler) and the
language development toolsuite that is used to develop
the application. In general, the user must clear the
interrupt flag in the appropriate IFSx register for the
source of the interrupt that the ISR handles. Otherwise,
the ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
8.4.3 TRAP SERVICE ROUTINE (TSR)
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
8.4.4 INTERRUPT DISABLE
All user interrupts can be disabled using the following
procedure:
1. Push the current SR value onto the software
stack using the PUSH instruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Only user interrupts with a priority level of 7 or less can
be disabled. Trap sources (Levels 8-15) cannot be
disabled.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period. Level 7 interrupt sources are not disabled by
the DISI instruction.
Note: At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to Priority Level 4.
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9.0 OSCILLATOR
CONFIGURATION
The oscillator system for the PIC24F16KA102 family of
devices has the following features:
• A total of five external and internal oscillator options
as clock sources, providing 11 different clock
modes.
• On-chip 4x Phase Locked Loop (PLL) to boost
internal operating frequency on select internal and
external oscillator sources.
• Software-controllable switching between various
clock sources.
• Software-controllable postscaler for selective
clocking of CPU for system power savings.
• System frequency range declaration bits for EC
mode. When using an external clock source, the
current consumption is reduced by setting the
declaration bits to the expected frequency range.
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown.
Figure 9-1 provides a simplified diagram of the oscillator
system.
FIGURE 9-1: PIC24F 16 KA10 2 FAMILY CLOCK DIAGRAM
Note: This data sheet summarizes the fea-
tures of this group of PIC24F devices. It
is not intended to be a comprehensive
reference source. For more information
on Oscillator Configuration, refer to the
“PIC24F Family Reference Manual”,
Section 38. “Oscillator with 500 kHz
Low-Power FRC ” (DS39726).
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
Postscaler
CLKDIV<10:8>
WDT, PWRT, DSWDT
FRCDIV
31 kHz (nominal)
8 MHz
FRC
LPRC
Oscillator
SOSC
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FRC
4 x PLL
XTPLL, HSPLL
ECPLL,FRCPLL
8 MHz
4 MHz
CPU
Peripherals
Postscaler
CLKDIV<14:12>
CLKO
Reference Clock
Generator
REFO
REFOCON<15:8>
Oscillator
500 kHz
LPFRC
Oscillator
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9.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and OSCO
pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
The PIC24F16KA102 family devices consist of two
types of secondary oscillator:
- High-Power Secondary Oscillator
- Low-Power Secondary Oscillator
These can be selected by using the SOSCSEL
(FOSC<5>) bit.
• Fast Internal RC (FRC) Oscillator
- 8 MHz FRC Oscillator
- 500 kHz Lower Power FRC Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and 8 MHz FRC sources have
the option of using the internal 4x PLL. The frequency
of the FRC clock source can optionally be reduced by
the programmable clock divider. The selected clock
source generates the processor and peripheral clock
sources.
The processor clock source is divided by two to produce
the internal instruction cycle clock, FCY. In this docu-
ment, the instruction cycle clock is also denoted by
FOSC/2. The internal instruction cycle clock, FOSC/2, can
be provided on the OSCO I/O pin for some operating
modes of the primary oscillator.
9.2 Initial Con fi guration on POR
The oscillator source (and operating mode) that is used
at a device Power-on Reset (POR) event is selected
using Configuration bit settings. The Oscillator
Configuration bit settings are located in the Configuration
registers in the program memory (refer to Section 26.1
“Configuration Bits” for further details). The Primary
Oscillator Configuration bits, POSCMD<1:0>
(FOSC<1:0>), and the Initial Oscillator Select Configura-
tion bits, FNOSC<2:0> (FOSCSEL<2:0>), select the
oscillator source that is used at a POR. The FRC Primary
Oscillator with Postscaler (FRCDIV) is the default (unpro-
grammed) selection. The secondary oscillator, or one of
the internal oscillators, may be chosen by programming
these bit locations. The EC mode frequency range
Configuration bits, POSCFREQ<1:0> (FOSC<4:3>),
optimize power consumption when running in EC
mode. The default configuration is “frequency range is
greater than 8 MHz”.
The Configuration bits allow users to choose between
the various clock modes, shown in Tabl e 9- 1.
9.2.1 CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (FOSC<7:6>) are used
jointly to configure device clock switching and the
FSCM. Clock switching is enabled only when FCKSM1
is programmed (‘0’). The FSCM is enabled only when
FCKSM<1:0> are both programmed (‘00’).
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note
8 MHz FRC Oscillator with Postscaler
(FRCDIV)
Internal 11 111 1, 2
500 MHz FRC Oscillator with Postscaler
(LPFRCDIV)
Internal 11 110 1
Low-Power RC Oscillator (LPRC) Internal 11 101 1
Secondary (Timer1) Oscillator (SOSC) Secondary 00 100 1
Primary Oscillator (HS) with PLL Module
(HSPLL)
Primary 10 011
Primary Oscillator (EC) with PLL Module
(ECPLL)
Primary 00 011
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010
8 MHz FRC Oscillator with PLL Module
(FRCPLL)
Internal 11 001 1
8 MHz FRC Oscillator (FRC) Internal 11 000 1
Note 1: OSCO pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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9.3 Control Registers
The operation of the oscillator is controlled by three
Special Function Registers (SFRs):
• OSCCON
•CLKDIV
•OSCTUN
The OSCCON register (Register 9-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
The Clock Divider register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The FRC Oscillator Tune register (Register 9-3) allows
the user to fine tune the FRC oscillator over a range of
approximately ±5.25%. Each bit increment or decre-
ment changes the factory calibrated frequency of the
FRC oscillator by a fixed amount.
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R-0, HSC R-0, HSC R-0, HSC U-0 R/W-x(1)R/W-x(1)R/W-x(1)
— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0
bit 15 bit 8
R/SO-0, HSC U-0 R-0, HSC(2)U-0 R/CO-0, HS U-0 R/W-0 R/W-0
CLKLOCK —LOCK—CF— SOSCEN OSWEN
bit 7 bit 0
Legend: CO = Clearable Only bit
SO = Settable Only bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000 = 8 MHz FRC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1)
111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000 = 8 MHz FRC Oscillator (FRC)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
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bit 7 CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6 Unimplemented: Read as ‘0’
bit 5 LOCK: PLL Lock Status bit(2)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 Unimplemented: Read as ‘0’
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 Unimplemented: Read as ‘0’
bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
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REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1
ROI DOZE2 DOZE1 DOZE0 DOZEN(1)RCDIV2 RCDIV1 RCDIV0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU and peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: CPU and Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11 DOZEN: DOZE Enable bit(1)
1 = DOZE<2:0> bits specify the CPU and peripheral clock ratio
0 = CPU and peripheral clock ratio are set to 1:1
bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits
When OSCCON (COSC<2:0>) = 111:
111 = 31.25 kHz (divide by 256)
110 = 125 kHz (divide by 64)
101 = 250 kHz (divide by 32)
100 = 500 kHz (divide by 16)
011 = 1 MHz (divide by 8)
010 = 2 MHz (divide by 4)
001 = 4 MHz (divide by 2) (default)
000 = 8 MHz (divide by 1)
When OSCCON (COSC<2:0>) = 110:
111 = 1.95 kHz (divide by 256)
110 = 7.81 kHz (divide by 64)
101 = 15.62 kHz (divide by 32)
100 = 31.25 kHz (divide by 16)
011 = 62.5 kHz (divide by 8)
010 = 125 kHz (divide by 4)
001 = 250 kHz (divide by 2) (default)
000 = 500 kHz (divide by 1)
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
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REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN5(1)TUN4(1)TUN3(1)TUN2(1)TUN1(1)TUN0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Maximum frequency deviation
011110
·
·
·
000001
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111
·
·
·
100001
100000 = Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
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9.4 Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
9.4.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 26.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is unpro-
grammed (‘1’), the clock switching function and FSCM
function are disabled; this is the default setting.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
9.4.2 OSCILLATOR SWITCHING
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1. If desired, read the COSCx bits (OSCCON<14:12>),
to determine the current oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSCx bits
(OSCCON<10:8>) for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bits value is transferred to the COSCx
bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT, FSCM or
RTCC with LPRC as clock source are enabled)
or SOSC (if SOSCEN remains enabled).
Note: The Primary Oscillator mode has three
different submodes (XT, HS and EC),
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either
direction. In these instances, the
application must switch to FRC mode as
a transition clock source between the two
PLL modes.
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DS39927C-page 98 2008-2011 Microchip Technology Inc.
The following code sequence for a clock switch is
recommended:
1. Disable interrupts during the OSCCON register
unlock and write sequence.
2. Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back instructions.
3. Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
4. Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit in the instruction immediately
following the unlock sequence.
6. Continue to execute code that is not
clock-sensitive (optional).
7. Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is provided in Example 9-1.
EXAMPLE 9-1: BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
9.5 Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain oscillator modes, the device clock in the
PIC24F16KA102 family devices can also be configured
to provide a reference clock output signal to a port pin.
This feature is available in all oscillator configurations
and allows the user to select a greater range of clock
submultiples to drive external devices in the
application.
This reference clock output is controlled by the
REFOCON register (Register 9-4). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the ROSEL bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV #OSCCONH, w1
MOV #0x78, w2
MOV #0x9A, w3
MOV.b w2, [w1]
MOV.b w3, [w1]
;Set new oscillator selection
MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV #OSCCONL, w1
MOV #0x46, w2
MOV #0x57, w3
MOV.b w2, [w1]
MOV.b w3, [w1]
;Start oscillator switch operation
BSET OSCCON,#0
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REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROEN: Reference Oscillator Output Enable bit
1 = Reference oscillator is enabled on REFO pin
0 = Reference oscillator is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Primary oscillator is used as the base clock(1)
0 = System clock is used as the base clock; base clock reflects any clock switching of the device
bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in
Sleep mode.
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NOTES:
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PIC24F16KA102 FAMILY
10.0 POWER-SAVING FEATURES
The PIC24F16KA102 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock frequency
• Instruction-based Sleep, Idle and Deep Sleep
modes
• Software controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
10.1 Clock Frequency and Clock
Switching
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
10.2 Instruction-Based Power-Saving
Modes
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. Deep Sleep mode stops clock
operation, code execution and all peripherals except
RTCC and DSWDT. It also freezes I/O states and
removes power to SRAM and Flash memory.
The assembly syntax of the PWRSAV instruction is
shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
10.2.1 SLEEP MODE
Sleep mode includes these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT or RTCC, with LPRC as the
clock source, is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items, such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
EXAMPL E 10-1: PWRSAV INSTRUCTION SYNTAX
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
”Section 39. Power-Saving Features
with Deep Sleep” (DS39727).
Note: SLEEP_MODE and IDLE_MODE are con-
stants, defined in the assembler include
file, for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode
BSET DSCON, #DSEN ; Enable Deep Sleep
PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode
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10.2.2 IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
10.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
10.2.4 DEEP SLEEP MODE
In PIC24F16KA102 family devices, Deep Sleep mode
is intended to provide the lowest levels of power con-
sumption available without requiring the use of external
switches to completely remove all power from the
device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
•MCLR
event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
10.2.4.1 Entering Deep Sleep Mode
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV #SLEEP_MODE), within one
instruction cycle, to minimize the chance that Deep
Sleep will be spuriously entered.
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode.
The sequence to enter Deep Sleep mode is:
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 10.2.4.5 “Deep Sleep WDT” for
details).
2. If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
3. If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module (see Section 19.0 “Real-Time
Clock and Calendar (RTCC)” for more
information).
4. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
5. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
6. Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0 instruction.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
Note: To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
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10.2.4.2 Exiting Deep Sleep Mode
Deep Sleep mode exits on any one of the following events:
• POR event on VDD supply. If there is no DSBOR
circuit to re-arm the VDD supply POR circuit, the
external VDD supply must be lowered to the
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Exiting Deep Sleep mode generally does not retain the
state of the device and is equivalent to a Power-on
Reset (POR) of the device. Exceptions to this include
the RTCC (if present), which remains operational
through the wake-up, the DSGPRx registers and the
DSWDT bit.
Wake-up events that occur from the time Deep Sleep
exits until the time the POR sequence completes are
ignored and are not be captured in the DSWAKE
register.
The sequence for exiting Deep Sleep mode is:
1. After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
2. To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode; if the bit is set, clear it.
3. Determine the wake-up source by reading the
DSWAKE register.
4. Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
5. If application context data has been saved, read
it back from the DSGPR0 and DSGPR1
registers.
6. Clear the RELEASE bit (DSCON<0>).
10.2.4.3 Saving Context Data with the
DSGPR0/DSGPR1 Registers
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because VDDCORE power is not
supplied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1, or data
EEPROM (if available). Unlike other SFRs, the
contents of these registers are preserved while the
device is in Deep Sleep mode. After exiting Deep
Sleep, software can restore the data by reading the
registers and clearing the RELEASE bit (DSCON<0>).
10.2.4.4 I/O Pins During Deep Sleep
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they con-
tinue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing appli-
cation code again. Pins configured as inputs during
Deep Sleep remain high-impedance and pins config-
ured as outputs continue to drive their previous value.
After waking up, the TRIS and LAT registers, and the
SOSCEN bit (OSCCON<1>) are reset. If firmware
modifies any of these bits or registers, the I/O will not
immediately go to the newly configured states. Once
the firmware clears the RELEASE bit (DSCON<0>),
the I/O pins are “released”. This causes the I/O pins to
take the states configured by their respective TRIS and
LAT bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state infor-
mation will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins, how-
ever, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
Note: Any interrupt pending when entering
Deep Sleep mode is cleared,
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10.2.4.5 Deep Sleep WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (FDS<7>). The
device Watchdog Timer (WDT) need not be enabled for
the DSWDT to function. Entry into Deep Sleep mode
automatically resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (FDS<4>). The post-
scaler options are programmed by the
DSWDTPS<3:0> Configuration bits (FDS<3:0>). The
minimum time-out period that can be achieved is
2.1 ms and the maximum is 25.7 days. For more
details on the FDS Configuration register and DSWDT
configuration options, refer to Section 26.0 “Special
Features”.
10.2.4.6 Switching Clocks in Deep Sleep Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from the
SOSC clock source. The RTCC clock source is selected
with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
10.2.4.7 Checking and Clearing the Status of
Deep Sleep
Upon entry into Deep Sleep mode, the status bit
DPSLP (RCON<10>), becomes set and must be
cleared by software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
• The DPSLP bit is clear, but the POR bit is set.
This is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
10.2.4.8 Power-on Resets (PORs)
VDD voltage is monitored to produce PORs. Since exit-
ing from Deep Sleep functionally looks like a POR, the
technique described in Section 10.2.4.7 “Checking
and Clearing the Status of Deep Sleep” should be
used to distinguish between Deep Sleep and a true
POR event.
When a true POR occurs, the entire device, including
all Deep Sleep logic (Deep Sleep registers, RTCC,
DSWDT, etc.) is reset.
10.2.4.9 Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in
invoking and exiting Deep Sleep mode:
1. Device exits Reset and begins to execute its
application code.
2. If DSWDT functionality is required, program the
appropriate Configuration bit.
3. Select the appropriate clock(s) for the DSWDT
and RTCC (optional).
4. Enable and configure the DSWDT (optional).
5. Enable and configure the RTCC (optional).
6. Write context data to the DSGPRx registers
(optional).
7. Enable the INT0 interrupt (optional).
8. Set the DSEN bit in the DSCON register.
9. Enter Deep Sleep by issuing a PWRSV
#SLEEP_MODE command.
10. Device exits Deep Sleep when a wake-up event
occurs.
11. The DSEN bit is automatically cleared.
12. Read and clear the DPSLP status bit in RCON,
and the DSWAKE status bits.
13. Read the DSGPRx registers (optional).
14. Once all state related configurations are
complete, clear the RELEASE bit.
15. Application resumes normal operation.
2008-2011 Microchip Technology Inc. DS39927C-page 105
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REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1)
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
DSEN — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/C-0, HS
— — — — — — DSBOR(2)RELEASE
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
bit 14-2 Unimplemented: Read as ‘0’
bit 1 DSBOR: Deep Sleep BOR Event bit(2)
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
bit 0 RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
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REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS
— — — — — — —DSINT0
bit 15 bit 8
R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS
DSFLT —— DSWDT DSRTCC DSMCLR — DSPOR(2,3)
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
bit 7 DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 6-5 Unimplemented: Read as ‘0’
bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3 DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2 DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1 Unimplemented: Read as ‘0’
bit 0 DSPOR: Power-on Reset Event bit(2,3)
1 = The VDD supply POR circuit was active and a POR event was detected
0 = The VDD supply POR circuit was not active, or was active but did not detect a POR event
Note 1: All register bits are cleared when the DSCON<DSEN> bit is set.
2: All register bits are reset only in the case of a POR event outside Deep Sleep mode, except bit, DSPOR,
which does not reset on a POR event that is caused due to a Deep Sleep exit.
3: Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
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10.3 Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
while using a power-saving mode may stop
communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default.
It is also possible to use Doze mode to selectively reduce
power consumption in event driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. Enabling the automatic return to
full-speed CPU operation on interrupts is enabled by set-
ting the ROI bit (CLKDIV<15>). By default, interrupt
events have no effect on Doze mode operation.
10.4 Selective Peripheral Module
Control
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked, and thus, consume power. There may be
cases where the application needs what these modes
do not provide: the allocation of power resources to
CPU processing with minimal power consumption from
the peripherals.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers.
Both bits have similar functions in enabling or disabling
its associated module. Setting the PMD bit for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
registers will have no effect and read values will be
invalid. Many peripheral modules have a corresponding
PMD bit.
In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. Power consumption
is reduced, but not by as much as the PMD bits are
used. Most peripheral modules have an enable bit;
exceptions include capture, compare and RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the control
bit of the generic name format, “XXXIDL”. By default, all
modules that can operate during Idle mode will do so.
Using the disable on Idle feature disables the module
while in Idle mode, allowing further reduction of power
consumption during Idle mode, enhancing power
savings for extremely critical power applications.
PIC24F16KA102 FAMILY
DS39927C-page 108 2008-2011 Microchip Technology Inc.
REGISTER 10-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
— — T3MD T2MD T1MD — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0
I2C1MD U2MD U1MD — SPI1MD —— ADC1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable.
0 = Timer3 module is enabled
bit 12 T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable.
0 = Timer2 module is enabled
bit 11 T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable.
0 = Timer1 module is enabled
bit 10-8 Unimplemented: Read as ‘0’
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled. All I2C1 registers are held in Reset and are not writable.
0 = I2C1 module is enabled
bit 6 U2MD: UART2 Module Disable bit
1 = UART2 module is disabled. All UART2 registers are held in Reset and are not writable.
0 = UART2 module is enabled
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled. All UART1 registers are held in Reset and are not writable.
0 = UART1 module is enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled. All SPI1 registers are held in Reset and are not writable.
0 = SPI1 module is enabled
bit 2-1 Unimplemented: Read as ‘0’
bit 0 ADC1MD: A/D Module Disable bit
1 = A/D module is disabled. All A/D registers are held in Reset and are not writable.
0 = A/D module is enabled
2008-2011 Microchip Technology Inc. DS39927C-page 109
PIC24F16KA102 FAMILY
REGISTER 10-4: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — I2C1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — OC1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 I2C1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled. All Input Capture registers are held in Reset and are not writable.
0 = Input Capture 1 module is writable
bit 7-1 Unimplemented: Read as ‘0’
bit 0 OC1MD: Input Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled. All Output Compare registers are held in Reset and are not
writable.
0 = Output Compare 1 module is writable
PIC24F16KA102 FAMILY
DS39927C-page 110 2008-2011 Microchip Technology Inc.
REGISTER 10-5: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — — CMPMD RTCCMD —
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
CRCMD — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled. All Comparator Module registers are held in Reset and are not
writable.
0 = Comparator module is enabled
bit 9 RTCCMD: RTCC Module Disable bit
1 = RTCC module is disabled. All RTCC module registers are held in Reset and are not writable.
0 = RTCC module is enabled
bit 8 Unimplemented: Read as ‘0’
bit 7 CRCMD: CRC Module Disable bit
1 = CRC module is disabled. All CRC registers are held in Reset and are not writable.
0 = CRC module is enabled
bit 6-0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 111
PIC24F16KA102 FAMILY
REGISTER 10-6: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— — — EEMD REFOMD CTMUMD HLVDMD —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 EEMD: EEPROM Memory Module Disable bit
1 = Disable EEPROM memory Flash panel, minimizing current consumption
0 = EEPROM memory is disabled
bit 3 REFOMD: Reference Oscillator Module Disable bit
1 = Reference oscillator module is disabled. All Reference Oscillator registers are held in Reset and
are not writable
0 = Reference Oscillator module is enabled
bit 2 CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled. All CTMU registers are held in Reset and are not writable.
0 = CTMU module is enabled
bit 1 HLVDMD: HLVD Module Disable bit
1 = HLVD module is disabled. All HLVD registers are held in Reset and are not writable.
0 = HLVD module is enabled
bit 0 Unimplemented: Read as ‘0’
PIC24F16KA102 FAMILY
DS39927C-page 112 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 113
PIC24F16KA102 FAMILY
11.0 I/O PORTS
All of the device pins (except VDD and VSS) are shared
between the peripherals and the parallel I/O ports. All
I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
11.1 Para llel I/O (P I O ) P o rts
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1
displays how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the Data Latch register (LATx), read
the latch. Writes to the latch, write the latch. Reads
from the port (PORTx), read the port pins, while writes
to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the I/O
ports, refer to the “PIC24F Family Refer-
ence Manual”, Section 12. “I/O Ports with
Peripheral Pin Select (PPS)” (DS39711).
Note that the PIC24F16KA102 family
devices do not support Peripheral Pin
Select features.
Note: The I/O pins retain their state during Deep
Sleep. They will retain this state at
wake-up until the software restore bit
(RELEASE) is cleared.
QD
CK
WR LAT +
TRIS Latch
I/O Pin
WR PORT
Data Bus
QD
CK
Data Latch
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
Output Enable
PIC24F16KA102 FAMILY
DS39927C-page 114 2008-2011 Microchip Technology Inc.
11.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
The maximum open-drain voltage allowed is the same
as the maximum VIH specification.
11.2 Configuring Analog Port Pins
The use of the AD1PCFG and TRIS register controls
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Analog levels on any pin that is defined as a digital
input (including the ANx pins) may cause the input
buffer to consume current that exceeds the device
specifications.
11.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.3 Input Change Notification
The input change notification function of the I/O ports
allows the PIC24F16KA102 family of devices to
generate interrupt requests to the processor in
response to a Change-of-State (COS) on selected
input pins. This feature is capable of detecting input
Change-of-States even in Sleep mode, when the
clocks are disabled. Depending on the device pin
count, there are up to 23 external signals (CN0 through
CN22) that may be selected (enabled) for generating
an interrupt request on a Change-of-State.
There are six control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up/pull-down
connected to it. The pull-ups act as a current source
that is connected to the pin and the pull-downs act as a
current sink to eliminate the need for external resistors
when push button or keypad devices are connected.
On any pin, only the pull-up resistor or the pull-down
resistor should be enabled, but not both of them. If the
push button or the keypad is connected to VDD, enable
the pull-down, or if they are connected to VSS, enable
the pull-up resistors. The pull-ups are enabled
separately using the CNPU1 and CNPU2 registers,
which contain the control bits for each of the CN pins.
Setting any of the control bits enables the weak
pull-ups for the corresponding pins. The pull-downs are
enabled separately using the CNPD1 and CNPD2
registers, which contain the control bits for each of the
CN pins. Setting any of the control bits enables the
weak pull-downs for the corresponding pins.
When the internal pull-up is selected, the pin uses VDD
as the pull-up source voltage. When the internal
pull-down is selected, the pins are pulled down to VSS
by an internal resistor. Make sure that there is no
external pull-up source/pull-down sink when the
internal pull-ups/pull-downs are enabled.
EXAMPLE 11-1: PORT WRITE/READ EXAMPLE
Note: Pull-ups and pull-downs on change
notification pins should always be
disabled whenever the port pin is
configured as a digital output.
MOV 0xFF00, W0; //Configure PORTB<15:8> as inputs and PO RTB<7:0 > as ou tputs
MOV W0, TRISBB;
NOP; //Delay 1 cy cle
BTSS PORTB, #13 ; //Next Instruction
Equivalent ‘C’ Code
TRISB = 0xFF00; //Configure PORTB<15:8> as inputs and PO RTB<7:0 > as ou tputs
NOP(); //Delay 1 cycle
if(PORTBbits.RB13 = = 1) // execute f ollowin g code if PORT B pin 1 3 is se t.
{
}
2008-2011 Microchip Technology Inc. DS39927C-page 115
PIC24F16KA102 FAMILY
12.0 T IMER1
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC), or
operate as a free-running, interval timer/counter. Timer1
can operate in three modes:
•16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation During CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
Figure 12-1 presents a block diagram of the 16-bit
Timer1 module.
To configure Timer1 for operation:
1. Set the TON bit (= 1).
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
FIGURE 12-1: 16- BIT TIMER1 MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Timers, refer to the “PIC24F Famil y Refer-
ence Manual”, Section 14. “Timers”
(DS39704).
TON
Sync
SOSCI
SOSCO/
PR1
Set T1IF
Equal
Comparator
TMR1
Reset
SOSCEN
1
0
TSYNC
Q
QD
CK
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1x
01
TGATE
00
Gate
Sync
PIC24F16KA102 FAMILY
DS39927C-page 116 2008-2011 Microchip Technology Inc.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL—————
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
— TGATE TCKPS1 TCKPS0 —TSYNCTCS —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronize external clock input
0 = Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit
1 = External clock from T1CK pin (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 117
PIC24F16KA102 FAMILY
13.0 TIMER2/3
The Timer2/3 module is a 32-bit timer, which can also be
configured as two independent 16-bit timers with
selectable operating modes.
As a 32-bit timer, Timer2/3 operates in three modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
• Single 32-bit timer
• Single 32-bit synchronous counter
They also support these features:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit Period register match
• A/D Event Trigger
Individually, both of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the A/D event trigger
(this is implemented only with Timer3). The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON and T3CON
registers. T2CON and T3CON are provided in generic
form in Register 13-1 and Register 13-2, respectively.
For 32-bit timer/counter operation, Timer2 is the least
significant word (lsw) and Timer3 is the most significant
word (msw) of the 32-bit timer.
To configure Timer2/3 for 32-bit operation:
1. Set the T32 bit (T2CON<3> = 1).
2. Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value. PR3 will contain the
msw of the value while PR2 contains the lsw.
5. If interrupts are required, set the interrupt enable
bit, T3IE. Use the priority bits, T3IP<2:0>, to set
the interrupt priority.
While Timer2 controls the timer, the interrupt
appears as a Timer3 interrupt.
6. Set the TON bit (= 1).
The timer value, at any point, is stored in the register
pair, TMR<3:2>. TMR3 always contains the msw of the
count, while TMR2 contains the lsw.
To configure any of the timers for individual 16-bit
operation:
1. Clear the T32 bit in T2CON<3>.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx register.
5. If interrupts are required, set the interrupt enable
bit, TxIE; use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit (TxCON<15> = 1).
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Timers, refer to the “PIC24F Famil y Refer-
ence Manual”, Section 14. “Timers”
(DS39704).
Note: For 32-bit operation, T3CON control bits
are ignored. Only T2CON control bits are
used for setup and control. Timer2 clock
and gate inputs are utilized for the 32-bit
timer modules, but an interrupt is
generated with the Timer3 interrupt flags.
PIC24F16KA102 FAMILY
DS39927C-page 118 2008-2011 Microchip Technology Inc.
FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM
TMR3 TMR2
Set T3IF
Equal Comparator
PR3 PR2
Reset
LSB MSB
Note 1: The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits
are respective to the T2CON register.
Data Bus<15:0>
TMR3HLD
Read TMR2(1)
Write TMR2(1)
16
16
16
Q
QD
CK
TGATE
0
1
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY
TCS
TGATE
Gate
T2CK
Sync
A/D Event Trigger
Sync
1x
01
00
16
2008-2011 Microchip Technology Inc. DS39927C-page 119
PIC24F16KA102 FAMILY
FIGURE 13-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 13-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY TCS
1x
01
TGATE
00
Gate
T2CK
Sync
PR2
Set T2IF
Equal Comparator
TMR2
Reset
Q
QD
CK
TGATE
1
0
Sync
TON
TCKPS<1:0>
2
TCY TCS
1x
01
TGATE
00
T3CK
PR3
Set T3IF
Equal Comparator
TMR3
Reset
Q
QD
CK
TGATE
1
0
A/D Event Trigger
Prescaler
1, 8, 64, 256
Sync
PIC24F16KA102 FAMILY
DS39927C-page 120 2008-2011 Microchip Technology Inc.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL—————
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS1 TCKPS0 T32(1)—TCS—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer2 On bit
When T2CON<3> = 1:
1 = Starts 32-bit Timer2/3
0 = Stops 32-bit Timer2/3
When T2CON<3> = 0:
1 = Starts 16-bit Timer2
0 = Stops 16-bit Timer2
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit(1)
1 = Timer2 and Timer3 form a single 32-bit timer
0 = Timer2 and Timer3 act as two 16-bit timers
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer2 Clock Source Select bit
1 = External clock from pin, T2CK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation.
2008-2011 Microchip Technology Inc. DS39927C-page 121
PIC24F16KA102 FAMILY
REGISTER 13-2: T3CON: TIMER3 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1)—TSIDL
(1)—————
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
—TGATE
(1)TCKPS1(1)TCKPS0(1)——TCS
(1)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer3 On bit(1)
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Stop in Idle Mode bit(1)
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer3 Clock Source Select bit(1)
1 = External clock from the T3CK pin (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer
functions are set through T2CON.
PIC24F16KA102 FAMILY
DS39927C-page 122 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 123
PIC24F16KA102 FAMILY
14.0 INPUT CAPTURE
The input capture module is used to capture a timer
value from one of two selectable time bases upon an
event on an input pin.
The input capture features are quite useful in
applications requiring frequency (Time Period) and
pulse measurement. Figure 14-1 depicts a simplified
block diagram of the input capture module.
The PIC24F16KA102 family devices have one input
capture channel. The input capture module has
multiple operating modes, which are selected via the
IC1CON register. The operating modes include:
• Capture timer value on every falling edge of input
applied at the IC1 pin
• Capture timer value on every rising edge of input
applied at the IC1 pin
• Capture timer value on every 4th rising edge of
input applied at the IC1 pin
• Capture timer value on every 16th rising edge of
input applied at the IC1 pin
• Capture timer value on every rising and every
falling edge of input applied at the IC1 pin
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The input capture module has a four-level FIFO buffer.
The number of capture events required to generate a
CPU interrupt can be selected by the user.
FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on Input Capture, refer to the “PIC24F
Family Reference Manual”, Section 15.
“Input Capture” (DS39701).
IC1BUF
IC1 Pin
ICM<2:0> (IC1CON<2:0>)
Mode Select
3
10
Set Flag IC1IF
(in IFSn Register)
TMRy TMRx
Edge Detection Logic
16 16
FIFO
R/W
Logic
ICI<1:0>
ICOV, ICBNE (IC1CON<4:3>)
IC1CON Interrupt
Logic
System Bus
From 16-Bit Timers
ICTMR
(IC1CON<7>)
Prescaler
Counter
(1, 4, 16) Clock Synchronizer
PIC24F16KA102 FAMILY
DS39927C-page 124 2008-2011 Microchip Technology Inc.
14.1 Input Capture Registers
REGISTER 14-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——ICSIDL—————
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0
ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 ICSIDL: Input Capture 1 Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 ICTMR: Input Capture 1 Timer Select bit
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture 1 Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture 1 Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture 1 Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation
for this mode
000 = Input capture module is turned off
2008-2011 Microchip Technology Inc. DS39927C-page 125
PIC24F16KA102 FAMILY
15.0 OUTPUT COMP ARE
15.1 Setup for Single Output Pulse
Generation
When the OCM control bits (OC1CON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OC1 pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2. Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Write the values computed in Steps 2 and 3
above into the Output Compare 1 register,
OC1R, and the Output Compare 1 Secondary
register, OC1RS, respectively.
5. Set Timer Period register, PRy, to value equal to
or greater than the value in OC1RS, the Output
Compare 1 Secondary register.
6. Set the OCM bits to ‘100’ and the OCTSEL
(OC1CON<3>) bit to the desired timer source.
The OC1 pin state will now be driven low.
7. Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
8. Upon the first match between TMRy and OC1R,
the OC1 pin will be driven high.
9. When the incrementing timer, TMRy, matches
the Output Compare 1 Secondary register,
OC1RS, the second and trailing edge
(high-to-low) of the pulse is driven onto the OC1
pin. No additional pulses are driven onto the
OC1 pin and it remains low. As a result of the
second compare match event, the OC1IF inter-
rupt flag bit is set, which will result in an interrupt
if it is enabled, by setting the OC1IE bit. For
further information on peripheral interrupts, refer
to Section 8.0 “Interrupt Controller”.
10. To initiate another single pulse output, change
the Timer and Compare register settings, if
needed, and then issue a write to set the OCM
bits to ‘100’. Disabling and re-enabling of the
timer and clearing the TMRy register are not
required, but may be advantageous for defining
a pulse from a known event time boundary.
The output compare module does not have to be
disabled after the falling edge of the output pulse.
Another pulse can be initiated by rewriting the value of
the OC1CON register.
15.2 Setup for Continuous Output
Pulse Generation
When the OCM control bits (OC1CON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OC1 pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation):
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
2. Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Write the values computed in Step 2 and 3 above
into the Output Compare 1 register, OC1R, and the
Output Compare 1 Secondary register, OC1RS,
respectively.
5. Set the Timer Period register, PRy, to a value
equal to or greater than the value in OC1RS.
6. Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OC1 pin state will
now be driven low.
7. Enable the compare time base by setting the
TON (TyCON<15>) bit to ‘1’.
8. Upon the first match between TMRy and OC1R,
the OC1 pin will be driven high.
9. When the compare time base, TMRy, matches the
OC1RS, the second and trailing edge (high-to-low)
of the pulse is driven onto the OC1 pin.
10. As a result of the second compare match event,
the OC1IF interrupt flag bit is set.
11. When the compare time base and the value in its
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
12. Steps 8 through 11 are repeated and a continu-
ous stream of pulses is generated indefinitely.
The OC1IF flag is set on each OC1RS/TMRy
compare match event.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Output Compare, refer to the “PIC24F
Family Reference Manual”, Section 16.
“Output Compare” (DS39706).
PIC24F16KA102 FAMILY
DS39927C-page 126 2008-2011 Microchip Technology Inc.
15.3 Pulse-Width Modulation (PWM)
Mode
The following steps should be taken when configuring
the output compare module for PWM operation:
1. Set the PWM period by writing to the selected
Timer Period register (PRy).
2. Set the PWM duty cycle by writing to the OC1RS
register.
3. Write the OC1R register with the initial duty
cycle.
4. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.
5. Configure the output compare module for one of
two PWM Operation modes by writing to the
Output Compare Mode bits, OCM<2:0>
(OC1CON<2:0>).
6. Set the TMRy prescale value and enable the
time base by setting TON (TxCON<15>) = 1.
15.3.1 PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 15-1.
EQUATION 15-1: CALCULATING THE PWM
PERIOD(1)
15.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
OC1RS register. The OC1RS register can be written to
at any time, but the duty cycle value is not latched into
OC1R until a match between PRy and TMRy occurs
(i.e., the period is complete). This provides a double
buffer for the PWM duty cycle and is essential for
glitchless PWM operation. In PWM mode, OC1R is a
read-only register.
Some important boundary parameters of the PWM duty
cycle include:
• If the Output Compare 1 register, OC1R, is loaded
with 0000h, the OC1 pin will remain low (0% duty
cycle).
• If OC1R is greater than PRy (Timer Period
register), the pin will remain high (100% duty
cycle).
• If OC1R is equal to PRy, the OC1 pin will be low
for one time base count value and high for all
other count values.
See Example 15-1 for PWM mode timing details.
Table 15-1 provides an example of PWM frequencies
and resolutions for a device operating at 10 MIPS.
EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
Note: The OC1R register should be initialized
before the output compare module is first
enabled. The OC1R register becomes a
read-only Duty Cycle register when the
module is operated in the PWM modes.
The value held in OC1R will become the
PWM duty cycle for the first PWM period.
The contents of the Output Compare 1
Secondary register, OC1RS, will not be
transferred into OC1R until a time base
period match occurs.
Note: A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7, written into the PRy
register, will yield a period consisting of
8 time base cycles.
PWM Period = [(PR y) + 1] • TCY • (Timer Prescale Value)
PWM Frequenc y = 1/[PW M Period]
where:
Note 1: Based on T
CY = 2 * TOSC; Doze mode
and PLL are disabled.
( )
Maximum PWM Resolution (bits) =
FCY
FPWM • (Timer Prescale Value)
log10
log10(2) bits
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2008-2011 Microchip Technology Inc. DS39927C-page 127
PIC24F16KA102 FAMILY
EXAMPLE 15-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Timer Prescaler Ratio 8111111
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Timer Prescaler Ratio 8111111
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL
(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
TCY = 2 * TOSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value)
19.2 s = (PR2 + 1) • 62.5 ns • 1
PR2 = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz
device clock rate:
PWM Resolution = log10(FCY/FPWM)/log102) bits
= (log10(16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1: Based on T
CY = 2 * TOSC; Doze mode and PLL are disabled.
PIC24F16KA102 FAMILY
DS39927C-page 128 2008-2011 Microchip Technology Inc.
FIGURE 15-1: O UTPUT COMPARE MODULE BLOCK DIAGRAM
Comparator
Output
Logic
QS
R
OCM<2:0>
Output Enable
OC1(1)
Set Flag bit
OC1IF(1)
OC1RS(1)
Mode Select
3
Note 1: Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1.
2: OCFA pin controls OC1 channel.
3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time
bases associated with the module.
OCTSEL 01
1616
OCFA(2)
TMR Register Inputs
from Time Bases(3) Period Match Signals
from Time Bases(3)
01
OC1R(1)
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PIC24F16KA102 FAMILY
15.4 Output Compare Register
REGISTER 15-1: OC1CON: OUTPUT COMPARE 1 CONTROL REGISTER
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——OCSIDL —————
bit 15 bit 8
U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0
— — — OCFLT OCTSEL OCM2 OCM1 OCM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 OCSIDL: Stop Output Compare 1 in Idle Mode Control bit
1 = Output Compare 1 will halt in CPU Idle mode
0 = Output Compare 1 will continue to operate in CPU Idle mode
bit 12-5 Unimplemented: Read as ‘0’
bit 4 OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3 OCTSEL: Output Compare 1 Timer Select bit
1 = Timer3 is the clock source for Output Compare 1
0 = Timer2 is the clock source for Output Compare 1
Refer to the device data sheet for specific time bases available to the output compare module.
bit 2-0 OCM<2:0>: Output Compare 1 Mode Select bits
111 = PWM mode on OC1, Fault pin; OCF1 enabled(1)
110 = PWM mode on OC1, Fault pin; OCF1 disabled(1)
101 = Initialize OC1 pin low, generate continuous output pulses on OC1 pin
100 = Initialize OC1 pin low, generate single output pulse on OC1 pin
011 = Compare event toggles OC1 pin
010 = Initialize OC1 pin high, compare event forces OC1 pin low
001 = Initialize OC1 pin low, compare event forces OC1 pin high
000 = Output compare channel is disabled
Note 1: The OCFA pin controls the OC1 channel.
PIC24F16KA102 FAMILY
DS39927C-page 130 2008-2011 Microchip Technology Inc.
REGISTER 15-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SMBUSDEL
(3)
OC1TRIS(2)
RTSECSEL1
(1,4)
RTSECSEL0
(1,4)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 3 OC1TRIS: OC1 Output Tri-State Select bit(2)
1 = OC1 output will not be active on the pin; OCPWM1 can still be used for internal triggers
0 = OC1 output will be active on the pin based on the OCPWM1 module settings
bit 0 Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
2: To enable the actual OC1 output, the OCPWM1 module has to be enabled.
3: Bit 4 is described in Section 17.0 “Inter-Integrated Circuit (I2C™)”.
4: Bits 2 and 1 are described in Section 1 9.0 Real-Time Clock and Calendar (RTCC).
2008-2011 Microchip Technology Inc. DS39927C-page 131
PIC24F16KA102 FAMILY
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial data EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with the SPI and SIOP interfaces
from Motorola®.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
• SDI1: Serial Data Input
• SDO1: Serial Data Output
• SCK1: Shift Clock Input or Output
• SS1: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using
2, 3 or 4 pins. In the 3-pin mode, SS1 is not used. In the
2-pin mode, both SDO1 and SS1 are not used.
Block diagrams of the module in Standard and
Enhanced Buffer modes are displayed in Figure 16-1
and Figure 16-2.
The devices of the PIC24F16KA102 family offer one
SPI module on a device.
To set up the SPI module for the Standard Master mode
of operation:
1. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
2. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Clear the SPIROV bit (SPI1STAT<6>).
4. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
5. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
To set up the SPI module for the Standard Slave mode
of operation:
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IP bits in the IPC2
register to set the interrupt priority.
3. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit
(SPI1CON1<7>) must be set to enable the SS1
pin.
6. Clear the SPIROV bit (SPI1STAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the Serial
Peripheral Interface, refer to the “PIC24F
Family Reference Manual”, Section 23.
“Serial Peripheral Interface (SPI)”
(DS39699).
Note: Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPI1BUF register in either Standard or
Enhanced Buffer mode.
Note: In this section, the SPI module is referred
to as SPI1, or separately as SPI1. Special
Function Registers (SFRs) will follow a
similar notation. For example, SPI1CON1
or SPI1CON2 refers to the control register
for the SPI1 module.
PIC24F16KA102 FAMILY
DS39927C-page 132 2008-2011 Microchip Technology Inc.
FIGURE 16-1: SPI1 MO DULE BLOCK DIAGRAM (STANDARD BUFFER MODE)
Internal Data Bus
SDI1
SDO1
SS1/FSYNC1
SCK1
SPI1SR
bit 0
Shift Control
Edge
Select
FCY
Primary
1:1/4/16/64
Enable
Prescaler
Sync
SPI1BUF
Control
Transfer
Transfer
Write SPI1BUF
Read SPI1BUF
16
SPI1CON1<1:0>
SPI1CON1<4:2>
Master Clock
Secondary
Prescaler
1:1 to 1:8
Clock
Control
2008-2011 Microchip Technology Inc. DS39927C-page 133
PIC24F16KA102 FAMILY
To set up the SPI module for the Enhanced Buffer
Master (EBM) mode of operation:
1. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register.
2. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Clear the SPIROV bit (SPI1STAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
5. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
6. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
3. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
6. Clear the SPIROV bit (SPI1STAT<6>).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
FIGURE 16-2: SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
Internal Data Bus
SDI1
SDO1
SS1/FSYNC1
SCK1
SPI1SR
bit 0
Shift Control
Edge
Select
FCY
Enable
Sync
SPI1BUF
Control
Transfer
Transfer
Write SPI1BUF
Read SPI1BUF
16
SPI1CON1<1:0>
SPI1CON1<4:2>
Master Clock
Clock
Control
Primary
1:1/4/16/64
Prescaler
Secondary
Prescaler
1:1 to 1:8
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
PIC24F16KA102 FAMILY
DS39927C-page 134 2008-2011 Microchip Technology Inc.
REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC
SPIEN — SPISIDL —— SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R-0,HSC R/C-0, HS R/W-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’ HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit H = Hardware Settable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPI1 Enable bit
1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins
0 = Disables module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers are pending.
Slave mode:
Number of SPI transfers are unread.
bit 7 SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)
1 = SPI1 Shift register is empty and ready to send or receive
0 = SPI1 Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded
The user software has not read the previous data in the SPI1BUF register.
0 = No overflow has occurred
bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2 SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPI1 transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPI1SR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete
100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot
011 = Interrupt when the SPI1 receive buffer is full (SPIRBF bit set)
010 = Interrupt when the SPI1 receive buffer is 3/4 or more full
001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty
(SRXMPT bit is set)
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bit 1 SPITBF: SPI1 Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPI1TXB is full
0 = Transmit has started, SPI1TXB is empty
In Standard Buffer mode:
Automatically set in hardware when the CPU writes to the SPITBF location, loading SPITBF.
Automatically cleared in hardware when the SPI1 module transfers data from SPI1TXB to SPIRBF.
In Enhanced Buffer mode:
Automatically set in hardware when CPU writes to the SPI1BUF location, loading the last available buffer location.
Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0 SPIRBF: SPI1 Receive Buffer Full Status bit
1 = Receive is complete; SPI1RXB is full
0 = Receive is not complete; SPI1RXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPI1 transfers data from SPIRBF to SPIRBF.
Automatically cleared in hardware when the core reads the SPI1BUF location, reading SPIRBF.
In Enhanced Buffer mode:
Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location.
Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR.
REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED)
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REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 DISSCK: Disable SCK1 pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11 DISSDO: Disables SDO1 pin bit
1 = SDO1 pin is not used by module; pin functions as I/O
0 = SDO1 pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPI1 Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPI1 is used in Slave mode.
bit 8 CKE: SPI1 Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)
1 =SS1 pin is used for Slave mode
0 =SS1
pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 =Slave mode
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
.
.
.
000 = Secondary prescale 8:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
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bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
REGISTER 16-3: SPI1CON2: SPI1 CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD SPIFPOL —————
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPIFE SPIBEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPI1 Support bit
1 = Framed SPI1 support is enabled
0 = Framed SPI1 support is disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control on SS1 Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0 SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer is enabled
0 = Enhanced Buffer is disabled (Legacy mode)
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DS39927C-page 138 2008-2011 Microchip Technology Inc.
EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
TABLE 16-1: SAMPLE SCK FREQUENCIES(1,2)
FCY = 16 MHz Secondary Prescaler Settings
1:12:14:16:18:1
Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 2000
4:1 4000 2000 1000 667 500
16:1 1000 500 250 167 125
64:1 250 125 63 42 31
FCY = 5 MHz
Primary Prescaler Settings 1:1 5000 2500 1250 833 625
4:1 1250 625 313 208 156
16:1 313 156 78 52 39
64:17839201310
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: SCK1 frequencies are indicated in kHz.
Primary Prescaler * Secondary Prescaler
FCY
FSCK =
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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17.0 INTER-INTEGRATED CIRCUIT
(I2C™)
The Inter-Integrated Circuit (I2C) module is a serial
interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial data EEPROMs, display drivers,
A/D Converters, etc.
The I2C module supports these features:
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the
I2C
protocol
• Automatic clock stretching to provide delays for
the processor to respond to a slave data request
• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
• Multi-Master modes to prevent loss of messages
in arbitration
• Bus Repeater mode, allowing the acceptance of
all messages as a slave regardless of the address
• Automatic SCL
Figure 17-1 illustrates a block diagram of the module.
17.1 Pin Remapping Options
The I2C module is tied to a fixed pin. To allow flexibility
with peripheral multiplexing, the I2C1 module in 28-pin
devices can be reassigned to the alternate pins,
designated as SCL1 and SDA1 during device
configuration.
Pin assignment is controlled by the I2C1SEL
Configuration bit. Programming this bit (= 0) multiplexes
the module to the SCL1 and SDA1 pins.
17.2 Communicating as a Master in a
Single Master Environ ment
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1. Assert a Start condition on SDA1 and SCL1.
2. Send the I2C device address byte to the slave
with a write indication.
3. Wait for and verify an Acknowledge from the
slave.
4. Send the first data byte (sometimes known as
the command) to the slave.
5. Wait for and verify an Acknowledge from the
slave.
6. Send the serial memory address low byte to the
slave.
7. Repeat Steps 4 and 5 until all data bytes are
sent.
8. Assert a Repeated Start condition on SDA1 and
SCL1.
9. Send the device address byte to the slave with
a read indication.
10. Wait for and verify an Acknowledge from the
slave.
11. Enable master reception to receive serial
memory data.
12. Generate an ACK or NACK condition at the end
of a received byte of data.
13. Generate a Stop condition on SDA1 and SCL1.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Inter-Integrated Circuit, refer to the
“PIC24F Family Reference Manual”,
Section 24. “Inter-Integrated Circuit™
(I2C™)” (DS39702).
PIC24F16KA102 FAMILY
DS39927C-page 140 2008-2011 Microchip Technology Inc.
FIGURE 17-1: I 2C™ BLOCK DIAGRAM
I2C1RCV
Internal
Data Bus
SCL1
SDA1
Shift
Match Detect
I2C1ADD
Start and Stop
Bit Detect
Clock
Address Match
Clock
Stretching
I2C1TRN
LSB
Shift Clock
BRG Down Counter
Reload
Control
TCY/2
Start and Stop
Bit Generation
Acknowledge
Generation
Collision
Detect
I2C1CON
I2C1STAT
Control Logic
Read
LSB
Write
Read
I2C1BRG
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2C1MSK
I2C1RSR
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17.3 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1: COMPUTING BAUD RATE
RELOAD VALUE(1)
17.4 Slave Address Masking
The I2C1MSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2C1MSK register causes the slave
module to respond whether the corresponding address
bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set
to ‘00100000’, the slave module will detect both
addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
TABLE 17-1: I2C™ CLOCK RATES(1)
TABLE 17-2: I2C™ RESERVED ADDRESSES(1)
I2C1BRG FCY
FSCL
------------FCY
10 000 000
------------------------------
–


1–=
FSCL FCY
I2C1BRG 1 FCY
10 000 000
------------------------------
++
----------------------------------------------------------------------
=
or
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
Note: As a result of changes in the I2C protocol,
the addresses in Table 1 7-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
Required
System
FSCL FCY I2C1BRG Value Actual
FSCL
(Decimal) (Hexadecimal)
100 kHz 16 MHz 157 9D 100 kHz
100 kHz 8 MHz 78 4E 100 kHz
100 kHz 4 MHz 39 27 99 kHz
400 kHz 16 MHz 37 25 404 kHz
400 kHz 8 MHz 18 12 404 kHz
400kHz 4MHz 9 9 385kHz
400kHz 2MHz 4 4 385kHz
1 MHz 16 MHz 13 D 1.026 MHz
1MHz 8MHz 6 6 1.026MHz
1MHz 4MHz 3 3 0.909MHz
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled;
Slave
Address R/W
Bit Description
0000 000 0 General Call Address(2)
0000 000 1 Start Byte
0000 001 x Cbus Address
0000 010 x Reserved
0000 011 x Reserved
0000 1xx x HS Mode Master Code
1111 1xx x Reserved
1111 0xx x 10-Bit Slave Upper Byte(3)
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2C1 Enable bit
1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins
0 = Disables the I2C1 module; all I2C™ pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCL1 Release Control bit (when operating as I2C slave)
1 = Releases SCL1 clock
0 = Holds SCL1 clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission; hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses are Acknowledged
0 = IPMI Support mode is disabled
bit 10 A10M: 10-Bit Slave Addressing bit
1 = I2C1ADD is a 10-bit slave address
0 = I2C1ADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables the SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for
reception)
0 = General call address is disabled
bit 6 STREN: SCL1 Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching
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bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master; applicable during master receive)
1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware
is clear at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; hardware is clear at the end of eighth bit of master receive data byte
0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware is clear at end of master Stop sequence
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware is clear at end of master
Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDA1 and SCL1 pins; hardware is clear at end of master Start sequence
0 = Start condition is not in progress
REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED)
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REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A PSR/W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware is set or clear at of Acknowledge.
bit 14 TRSTAT: Transmit Status bit
(When operating as I2C™ master; applicable to master transmit operation.)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at beginning of master transmission; hardware is clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches general call address; hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at match of 2nd byte of matched 10-bit address; hardware is clear at Stop detection.
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2C1TRN register failed because the I2C module is busy
0 = No collision
Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software).
bit 6 I2COV : Receive Overflow Flag bit
1 = A byte was received while the I2C1RCV register is still holding the previous byte
0 = No overflow
Hardware is set at attempt to transfer to I2C1RCV (cleared by software).
bit 5 D/A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was the device address
Hardware is clear at device address match; hardware is set by a write to I2C1TRN or by reception of slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
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bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 2 R/W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates the data transfer is output from slave
0 = Write – indicates the data transfer is input to slave
Hardware is set or clear after reception of I2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive complete, I2C1RCV is full
0 = Receive not complete, I2C1RCV is empty
Hardware is set when I2C1RCV is written with received byte; hardware is clear when software reads I2C1RCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2C1TRN is full
0 = Transmit complete, I2C1TRN is empty
Hardware is set when software writes to I2C1TRN; hardware is clear at completion of data transmission.
REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED)
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REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK9 AMSK8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match is not required in this position
0 = Disable masking for bit x; bit match is required in this position
REGISTER 17-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— — — SMBUSDEL OC1TRIS
(2,3)
RTSECSEL1
(1,3)
RTSECSEL0
(1,3)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 SMBUSDEL: SMBus SDA Input Delay Select bit
1 = The I2C module is configured for a longer SMBus input delay (nominal 300 ns delay)
0 = The 12C module is configured for a legacy input delay (nominal 150 ns delay)
bit 0 Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.
2: To enable the actual OC1 output, the OCPWM1 module has to be enabled.
3: Bits<3:1> are described in related chapters.
2008-2011 Microchip Technology Inc. DS39927C-page 147
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18.0 UNIV ERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in this PIC24F device family. The UART is a
full-duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN, RS-232 and RS-485 interfaces. This module also
supports a hardware flow control option with the UxCTS
and UxRTS pins, and also includes an IrDA® encoder
and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
through the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
• Fully Integrated Baud Rate Generator (IBRG) with
16-Bit Prescaler
• Baud Rates Ranging from 1 Mbps to 15 bps at
16 MIPS
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
Detection
• Support for 9-Bit mode with Address Detect (9th
bit = 1)
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is displayed in
Figure 18-1. The UART module consists of these
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Universal Asynchronous Receiver
Transmitter, refer to the “PIC24F Family
Reference Manual”, Section 21. “UART”
(DS39708).
UxRX
IrDA®
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
UxCTS
UxRTS
UxBCLK
Baud Rate Generator
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18.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud
Rate Generator (BRG). The UxBRG register controls
the period of a free-running, 16-bit timer. Equation 18-1
provides the formula for computation of the baud rate
with BRGH = 0.
EQUATION 18-1: UART BAUD RATE WITH
BRGH = 0(1)
Example 18-1 provides the calculation of the baud rate
error for the following conditions:
•F
CY = 4 MHz
• Desired Baud Rate = 9600
The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
possible is FCY/(16 * 65536).
Equation 18-2 provides the formula for computation of
the baud rate with BRGH = 1.
EQUATION 18-2: UART BAUD RATE WITH
BRGH = 1(1)
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
EXAMPLE 18-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Note 1: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Baud Rate = FCY
16 • (UxBRG + 1)
FCY
16 • Baud Rate
UxBRG = – 1
Baud Rate = FCY
4 • (UxBRG + 1)
FCY
4 • Baud Rate
UxBRG = – 1
Note 1: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Desired Baud Rate = FCY/(16 (UxBRG + 1))
Solving for UxBRG value:
UxBRG = ((FCY/Desired Baud Rate)/16) – 1
UxBRG = ((4000000/9600)/16) – 1
UxBRG = 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9 615
Error = (Calculated Baud Rate – Desire d Baud Rate )
Desired Baud Rate
= (9615 – 96 00)/9600
=0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2008-2011 Microchip Technology Inc. DS39927C-page 149
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18.2 Transmitting in 8-Bit Data Mode
1. Set up the UART:
a) Write appropriate values for data, parity and
Stop bits.
b) Write appropriate baud rate value to the
UxBRG register.
c) Set up transmit and receive interrupt enable
and priority bits.
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt
two cycles after being set).
4. Write data byte to lower byte of UxTXREG word.
The value will be immediately transferred to the
Transmit Shift Register (TSR) and the serial bit
stream will start shifting out with the next rising
edge of the baud clock.
5. Alternately, the data byte may be transferred
while UTXEN = 0, and then, the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
6. A transmit interrupt will be generated as per
interrupt control bit, UTXISELx.
18.3 Transmitting in 9-Bit Data Mode
1. Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt
two cycles after being set).
4. Write UxTXREG as a 16-bit value only.
5. A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
6. A transmit interrupt will be generated as per the
setting of control bit, UTXISELx.
18.4 Break and Sync Transmit
Sequence
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte.
1. Configure the UART for the desired mode.
2. Set UTXEN and UTXBRK – sets up the Break
character.
3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
4. Write ‘55h’ to UxTXREG – loads the Sync
character into the transmit FIFO.
5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
18.5 Receiving in 8-Bit or 9-Bit Data
Mode
1. Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
2. Enable the UART.
3. A receive interrupt will be generated when one
or more data characters have been received, as
per interrupt control bit, URXISELx.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
5. Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
18.6 Operation of UxCTS and UxRTS
Control Pins
UARTx Clear to Send (UxCTS) and Request to Send
(UxRTS) are the two hardware-controlled pins that are
associated with the UART module. These two pins
allow the UART to operate in Simplex and Flow Control
modes. They are implemented to control the
transmission and reception between the Data Terminal
Equipment (DTE). The UEN<1:0> bits in the UxMODE
register configure these pins.
18.7 Infrared Support
The UART module provides two types of infrared UART
support: one is the IrDA clock output to support an
external IrDA encoder and decoder device (legacy
module support), and the other is the full
implementation of the IrDA encoder and decoder.
As the IrDA modes require a 16x baud clock, they will
only work when the BRGH bit (UxMODE<3>) is ‘0’.
18.7.1 EXTERNAL IrDA SUPPORT – IrDA
CLOCK OUTPUT
To support external IrDA encoder and decoder devices,
the UxBCLK pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. When
UEN<1:0> = 11, the UxBCLK pin will output the 16x
baud clock if the UART module is enabled; it can be
used to support the IrDA codec chip.
18.7.2 BUILT-IN IrDA ENCODER AND
DECODER
The UART has full implementation of the IrDA encoder
and decoder as part of the UART module. The built-in
IrDA encoder and decoder functionality is enabled
using the IREN bit (UxMODE<12>). When enabled
(IREN = 1), the receive pin (UxRX) acts as the input
from the infrared receiver. The transmit pin (UxTX) acts
as the output to the infrared transmitter.
PIC24F16KA102 FAMILY
DS39927C-page 150 2008-2011 Microchip Technology Inc.
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2)R/W-0(2)
UARTEN — USIDL IREN(1)RTSMD — UEN1 UEN0
bit 15 bit 8
R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is
minimal
bit 14 Unimplemented: Read as ‘0’
bit 13 USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(1)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 =UxRTS pin is in Simplex mode
0 =UxRTS
pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits(2)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by port
latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit is cleared in
hardware on the following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).
2: Bit availability depends on pin availability.
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bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).
2: Bit availability depends on pin availability.
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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC
URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: HC = Hardware Clearable bit
C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle ‘0’
0 = UxTX Idle ‘1’
If IREN = 1:
1 = UxTX Idle ‘1’
0 = UxTX Idle ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset. UxTX pin is controlled
by the PORT register.
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
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bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition) will reset
the receiver buffer and the RSR to the empty state)
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data; at least one more character can be read
0 = Receive buffer is empty
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
PIC24F16KA102 FAMILY
DS39927C-page 154 2008-2011 Microchip Technology Inc.
REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER
U-x U-x U-x U-x U-x U-x U-x W-x
— — — — — — —UTX8
bit 15 bit 8
W-x W-x W-x W-x W-x W-x W-x W-x
UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode)
bit 7-0 UTX<7:0>: Data of the Transmitted Character bits
REGISTER 18-4: UxRXREG: UARTx RECEIVE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC
— — — — — — —URX8
bit 15 bit 8
R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 URX8: Data of the Received Character bit (in 9-bit mode)
bit 7-0 URX<7:0>: Data of the Received Character bits
2008-2011 Microchip Technology Inc. DS39927C-page 155
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19.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
Key features of the RTCC module are:
• Operates in Deep Sleep mode
• Selectable clock source
• Provides hours, minutes and seconds using
24-hour format
• Visibility of one half second period
• Provides calendar – weekday, date, month and
year
• Alarm-configurable for half a second, one second,
10 seconds, one minute, 10 minutes, one hour,
one day, one week, one month or one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat chime
• Year 2000 to 2099 leap year correction
• BCD format for smaller software overhead
• Optimized for long-term battery operation
• User calibration of the 32.768 kHz clock
crystal/32K INTRC frequency with periodic
auto-adjust
19.1 RTCC Source Clock
The user can select between the SOSC crystal
oscillator or the LPRC internal oscillator as the clock
reference for the RTCC module. This is configured
using the RTCOSC (FDS<5>) Configuration bit. This
gives the user an option to trade off system cost,
accuracy and power consumption, based on the overall
system needs.
The RTCC will continue to run, along with its chosen
clock source, while the device is held in Reset with
MCLR and will continue running after MCLR is
released.
FIGURE 19-1: RT CC BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Real-Time Clock and Calendar, refer to the
“PIC24F Family Reference Manual”,
Section 29. “Real-Time Clock and
Calendar (RTCC)” (DS39696).
RTCC Clock Domain CPU Clock Domain
RTCC
RTCC Prescalers
RTCC Timer
Comparator
Alarm Registers with Masks
Repeat Counter
0.5 Sec
RTCC Interrupt Logic
ALRMVAL
RTCVAL
ALCFGRPT
RCFGCAL
Alarm
Event
YEAR
MTHDY
WKDYHR
MINSEC
ALMTHDY
ALWDHR
ALMINSEC
RTCC
Interrupt
RTSECSEL<1:0>
RTCOE
10
00
01
Clock Source
1s
Pin
Alarm Pulse
Input from
SOSC/LPRC
Oscillator
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DS39927C-page 156 2008-2011 Microchip Technology Inc.
19.2 RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
19.2.1 REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RCFGCAL<9:8>) to select the desired
Timer register pair (see Table 19-1).
By writing the RTCVALH byte, the RTCC Pointer value,
the RTCPTR<1:0> bits decrement by one until they
reach ‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
TABLE 19-1: RTCVAL REGISTER MAPPING
The Alarm Value register window (ALRMVALH
and ALRMVALL) uses the ALRMPTR bits
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 19-2).
By writing the ALRMVALH byte, the Alarm Pointer
value bits (ALRMPTR<1:0>) decrement by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
TABLE 19-2: ALRMVAL REGISTER
MAPPING
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes, the ALRMPTR<1:0> value will be
decremented. The same applies to the RTCVALH or
RTCVALL bytes with the RTCPTR<1:0> being
decremented.
19.2.2 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 19-1).
19.2.3 SELECTING RTCC CLOCK SOURCE
The clock source for the RTCC module can be selected
using the RTCOSC (FDS<5>) bit. When the bit is set to
‘1’, the Secondary Oscillator (SOSC) is used as the ref-
erence clock and when the bit is ‘0’, LPRC is used as
the reference clock.
EXAMPLE 19-1: SETTING THE RTCWREN BIT
RTCPTR<1:0> RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00 MINUTES SECONDS
01 WEEKDAY HOURS
10 MONTH DAY
11 — YEAR
ALRMPTR
<1:0>
Alarm Value Register Window
ALRMVAL<15:8> ALRMVAL<7:0>
00 ALRMMIN ALRMSEC
01 ALRMWD ALRMHR
10 ALRMMNTH ALRMDAY
11 ——
Note: This only applies to read operations and
not write operations.
Note: To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 19-1.
asm volatile ("push w7") ;
asm volatile ("push w8
"
) ;
asm volatile ("disi #5
"
) ;
asm volatile ("mov #0x55, w7
"
) ;
asm volatile ("mov w7, _NVMKEY
"
);
asm volatile ("mov #0xAA, w8
"
);
asm volatile ("mov w8, _NVMKEY
"
);
asm volatile ("bset _RCFGCAL, #13
"
) ; //set the RTCWREN bit
asm volatile ("pop w8
"
) ;
asm volatile (
"
pop w7
"
);
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19.2.4 RTCC CONTROL REGISTERS
REGISTER 19-1:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
(
1)
R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0
RTCEN(2)— RTCWREN RTCSYNC HALFSEC(3)RTCOE RTCPTR1 RTCPTR0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple,
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11 HALFSEC: Half Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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DS39927C-page 158 2008-2011 Microchip Technology Inc.
bit 7-0 CAL<7:0>: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute
.
.
.
01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
.
.
.
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
REGISTER 19-1:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
(
1) (CONTINUED)
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— — — SMBUSDEL OC1TRIS
RTSECSEL1
(1)
RTSECSEL0
(1)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-3 Described in Section 15.0 “Output Compare” and Section 17.0 “Inter-Integrated Circuit (I2C™)”.
bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(
1
)
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (can be LPRC or SOSC, depending on the
RTCOSC (FDS<5>) bit setting)
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
bit 0 Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.
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REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit
1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL<7:0>:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.
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19.2.5 RTCVAL REGISTER MAPPINGS
REGISTER 19-4: YEAR: YEAR VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
YRTEN3 YRTEN2 YRTEN2 YRTEN1 YRONE3 YRONE2 YRONE1 YRONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —
MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— —
DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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19.2.6 ALRMVAL REGISTER MAPPINGS
REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —
MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— —
DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x
— — — — — WDAY2 WDAY1 WDAY0
bit 15 bit 8
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
2008-2011 Microchip Technology Inc. DS39927C-page 163
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REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0
bit 15 bit 8
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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19.3 Calibration
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value loaded into the lower half of RCFGCAL is
multiplied by four and will either be added or subtracted
from the RTCC timer, once every minute. Refer to the
steps below for RTCC calibration:
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz crystal.
2. Once the error is known, it must be converted to
the number of error clock pulses per minute.
3. a) If the oscillator is faster than ideal (negative
result form Step 2), the RCFGCAL register value
must be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
b) If the oscillator is slower than ideal (positive
result from Step 2), the RCFGCAL register value
must be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
Divide the number of error clocks, per minute by 4, to
get the correct calibration value and load the
RCFGCAL register with the correct value. (Each 1-bit
increment in the calibration adds or subtracts 4 pulses).
EQUATION 19-1:
Writes to the lower half of the RCFGCAL register
should only occur when the timer is turned off, or
immediately after the rising edge of the seconds pulse.
19.4 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(ALCFGRPT<15>)
• One-time alarm and repeat alarm options
available
19.4.1 CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVAL should only take place when ALRMEN = 0.
As displayed in Figure 19-2, the interval selection of the
alarm is configured through the AMASK bits
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ARPT<7:0> bits (ALCFGRPT<7:0>). When the value
of the ARPT bits equals 00h and the CHIME bit
(ALCFGRPT<14>) is cleared, the repeat function is
disabled and only a single alarm will occur. The alarm
can be repeated, up to 255 times, by loading
ARPT<7:0> with FFh.
After each alarm is issued, the value of the ARPT bits
is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ARPT bits reaches 00h, it rolls
over to FFh and continues counting indefinitely while
CHIME is set.
19.4.2 ALARM INTERRUPT
At every alarm event, an interrupt is generated. In
addition, an alarm pulse output is provided that
operates at half the frequency of the alarm. This output
is completely synchronous to the RTCC clock and can
be used as a trigger clock to other peripherals.
(Ideal Frequency† – Measured Frequency) * 60 =
Clocks per Minute
† Ideal Frequency = 32,768 Hz
Note: It is up to the user to include in the error
value, the initial error of the crystal; drift
due to temperature and drift due to crystal
aging.
Note: Changing any of the registers, other than
the RCFGCAL and ALCFGRPT registers,
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that
the ALCFGRPT register and the CHIME
bit be changed when RTCSYNC = 0.
2008-2011 Microchip Technology Inc. DS39927C-page 165
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FIGURE 19-2: ALARM MASK SETTINGS
Note 1: Annually, except when configured for February 29.
s
ss
mss
mm s s
hh mm ss
dhhmmss
dd hh mm ss
mm d d h h mm s s
Day of
the
Week Month Day Hours Minutes Seconds
Alarm Mask Setting
(AMASK<3:0>)
0000 - Every half second
0001 - Every second
0010 - Every 10 seconds
0011 - Every minute
0100 - Every 10 minutes
0101 - Every hour
0110 - Every day
0111 - Every week
1000 - Every month
1001 - Every year(1)
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NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 167
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20.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The programmable Cyclic Redundancy Check (CRC)
module in PIC24F devices is a software-configurable
CRC checksum generator. The CRC algorithm treats a
message as a binary bit stream and divides it by a fixed
binary number.
The remainder from this division is considered the
checksum. As in division, the CRC calculation is also
an iterative process. The only difference is that these
operations are done on modulo arithmetic based on
mod2. For example, division is replaced with the XOR
operation (i.e., subtraction without carry). The CRC
algorithm uses the term, polynomial, to perform all of
its calculations.
The divisor, dividend and remainder that are
represented by numbers are termed as polynomials
with binary coefficients.
The programmable CRC generator offers the following
features:
• User-programmable polynomial CRC equation
• Interrupt output
• Data FIFO
The module implements a software-configurable CRC
generator. The terms of the polynomial and its length
can be programmed using the CRCXOR (X<15:1>) bits
and the CRCCON (PLEN<3:0>) bits, respectively.
Consider the CRC equation:
EQUATION 20-1: CRC
To program this polynomial into the CRC generator, the
CRC register bits should be set as provided in
Table 20-1.
TABLE 20-1: EXAMPLE CRC SETUP
The value of X<15:1>, the 12th bit and the 5th bit are set
to ‘1’, as required by the equation. The 0 bit required by
the equation is always XORed. For a 16-bit polynomial,
the 16th bit is also always assumed to be XORed;
therefore, the X<15:1> bits do not have the 0 bit or the
16th bit.
The topology of a standard CRC generator is displayed
in Figure 20-2.
FIGURE 20-1: CRC SHIFTER DETAILS
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Program-
mable Cyclic Redundancy Check, refer to
the “PIC24F Family Reference Manual”,
Section 30. “Programmable Cyclic
Redundancy Check (CRC)” (DS39714).
Bit Name Bit Va lue
PLEN<3:0> 1111
X<15:1> 000100000010000
x16 + x12 + x5 + 1
IN
OUT
BIT 0
0
1
clk
X1
IN
OUT
BIT 1
0
1
clk
X2
IN
OUT
BIT 2
0
1
clk
X3
IN
OUT
BIT 15
0
1
clk
X15
XOR
D
OUT
01 2 15
PLEN<3:0>
Hold Hold Hold Hold
CRC Read Bus
CRC Write Bus
CRC Shift Register
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DS39927C-page 168 2008-2011 Microchip Technology Inc.
FIGURE 20-2: CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1
20.1 User Interface
20.1.1 DATA INTERFACE
To start serial shifting, a value of ‘1’ must be written to
the CRCGO bit.
The module incorporates a FIFO that is 8-level deep
when PLEN<3:0> > 7 and 16-deep, otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte.
For example, if PLEN = 5, then the size of the data is
PLEN + 1 = 6. The data must be written as follows:
data<5:0> = crc_input<5:0>
data<7:6> = bxx
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD bits
(CRCCON<12:8>) increments by one. The serial
shifter starts shifting data into the CRC engine when
CRCGO = 1 and VWORD<4:0> > 0. When the Most
Significant bit (MSb) is shifted out, the VWORD bits
decrement by one. The serial shifter continues shifting
until the VWORD bits reach zero. Therefore, for a given
value of PLEN, it will take (PLEN + 1) * VWORD
number of clock cycles to complete the CRC
calculations.
When the VWORD bits reach 8 (or 16), the CRCFUL bit
will be set. When the VWORD bits reach 0, the
CRCMPT bit will be set.
To continually feed data into the CRC engine, the
recommended mode of operation is to initially “prime”
the FIFO with a sufficient number of words so no
interrupt is generated before the next word can be
written. Once that is done, start the CRC by setting the
CRCGO bit to ‘1’. From that point onward, the VWORD
bits should be polled. If they read less than 8 or 16,
another word can be written into the FIFO.
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the
condition to generate an interrupt will not be met;
therefore, no interrupt will be generated (see
Section 20.1.2 “Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
20.1.2 INTERRUPT OPERATION
When the VWORD<4:0> bits make a transition from a
value of ‘1’ to ‘0’, an interrupt will be generated.
20.2 Operation in Power Save Modes
20.2.1 SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
20.2.2 IDLE MODE
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
DQ
BIT 0
clk
DQ
BIT 4
clk
DQ
BIT 5
clk
DQ
BIT 12
clk
XOR
SDOx
CRC Read Bus
CRC Write Bus
DQ
BIT 15
clk
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20.3 Registers
There are four registers used to control programmable
CRC operation:
• CRCCON
• CRCXOR
• CRCDAT
• CRCWDAT
REGISTER 20-1: CRCCON: CRC CONTROL REGISTER
U-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
—— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0
bit 15 bit 8
R-0, HSC R-1, HSC U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CSIDL: CRC Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-8 VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7, or
16 when PLEN<3:0> 7.
bit 7 CRCFUL: FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: FIFO Empty Bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5 Unimplemented: Read as ‘0’
bit 4 CRCGO: Start CRC bit
1 = Start CRC serial shifter
0 = CRC serial shifter is turned off
bit 3-0 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial to be generated minus 1.
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REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X15 X14 X13 X12 X11 X10 X9 X8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
X7 X6 X5 X4 X3 X2 X1 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits
bit 0 Unimplemented: Read as ‘0’
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21.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
The High/Low-Voltage Detect module (HLVD) is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
The HLVD Control register (see Register 21-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
FIGURE 21-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the High/Low-Voltage Detect, refer to
the “PIC24F Family Reference Manual”,
Section 36. “High-Level Integration
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725).
Set
VDD
16-to-1 MUX
HLVDEN
HLVDL<3:0>
HLVDIN
VDD
Externally Generated
Trip Point
HLVDIF
HLVDEN
Internal Band Gap
Voltag e Reference
VDIR
1.2V Typical
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DS39927C-page 172 2008-2011 Microchip Technology Inc.
REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
HLVDEN —HLSIDL—————
bit 15 bit 8
R/W-0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 HLSIDL: HLVD Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6 BGVST: Band Gap Voltage Stable Flag bit
1 = Indicates that the band gap voltage is stable
0 = Indicates that the band gap voltage is unstable
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the internal reference voltage is stable and the High-Voltage Detect logic generates
the interrupt flag at the specified voltage range
0 = Indicates that the internal reference voltage is unstable and the High-Voltage Detect logic will not
generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be
enabled
bit 4 Unimplemented: Read as ‘0’
bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Trip Point 1(1)
1101 = Trip Point 2(1)
1100 = Trip Point 3(1)
.
.
.
0000 = Trip Point 15(1)
Note 1: For actual trip point, refer to Section 29.0 “Electrical Characteristics”.
2008-2011 Microchip Technology Inc. DS39927C-page 173
PIC24F16KA102 FAMILY
22.0 10-BIT HIGH-SPEED A/D
CONVERTER
The 10-bit A/D Converter has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 500 ksps
• Nine analog input pins
• External voltage reference input pins
• Internal band gap reference inputs
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable Buffer Fill modes
• Four result alignment options
• Operation During CPU Sleep and Idle modes
On all PIC24F16KA102 family devices, the 10-bit A/D
Converter has nine analog input pins, designated AN0
through AN5 and AN10 through AN12. In addition,
there are two analog input pins for external voltage
reference connections (VREF+ and VREF-). These
voltage reference inputs may be shared with other
analog input pins.
A block diagram of the A/D Converter is displayed in
Figure 22-1.
To perform an A/D conversion:
1. Configure the A/D module:
a) Configure port pins as analog inputs and/or
select band gap reference inputs
(AD1PCFG<15:13>, AD1PCFG<9:6>).
b) Select voltage reference source to match
expected range on analog inputs
(AD1CON2<15:13>).
c) Select the analog conversion clock to match
the desired data rate with the processor
clock (AD1CON3<7:0>).
d) Select the appropriate sample/conversion
sequence (AD1CON1<7:5> and
AD1CON3<12:8>).
e) Select how conversion results are
presented in the buffer (AD1CON1<9:8>).
f) Select interrupt rate (AD1CON2<5:2>).
g) Turn on A/D module (AD1CON1<15>).
2. Configure A/D interrupt (if required):
a) Clear the AD1IF bit.
b) Select A/D interrupt priority.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the 10-Bit High-Speed A/D Converter,
refer to the “PIC24F Family Reference
Manual”, Section 17. “10-Bit A/D
Converter” (DS39705).
PIC24F16KA102 FAMILY
DS39927C-page 174 2008-2011 Microchip Technology Inc.
FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Comparator
10-Bit SAR Conversion Logic
VREF+
DAC
AN12
AN10
AN11
AN4
AN5
AN0
AN1
AN2
AN3
VREF-
Sample Control
S/H
AVSS
AVDD
ADC1BUF0:
ADC1BUFF
AD1CON1
AD1CON2
AD1CON3
AD1CHS
AD1PCFG
Control Logic
Data Formatting
Input MUX Control
Conversion Control
Pin Config Control
Internal Data Bus
16
VR+VR-
MUX A
MUX B
VINH
VINL
VINH
VINH
VINL
VINL
VBG
VBG/2
AD1CSSL
VR+
VR-
VR Select
AN1
AN1
2008-2011 Microchip Technology Inc. DS39927C-page 175
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REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON(1)—ADSIDL— — —FORM1FORM0
bit 15 bit 8
R/W
-0
R/W
-0
R/W-0
U-0 U-0
R/W-0 R/W
-0, HSC
R/W
-0, HSC
SSRC2 SSRC1 SSRC0 —— ASAM SAMP DONE
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: A/D Operating Mode bit(1)
1 = A/D Converter module is operating
0 = A/D Converter is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (sddd dddd dd00 0000)
10 = Fractional (dddd dddd dd00 0000)
01 = Signed integer (ssss sssd dddd dddd)
00 = Integer (0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU event ends sampling and starts conversion
101 = Reserved
100 = Reserved
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
bit 4-3 Unimplemented: Read as ‘0’
bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: A/D Sample Enable bit
1 = A/D sample/hold amplifier is sampling input
0 = A/D sample/hold amplifier is holding
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is not done
Note 1: Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the
conversion values from the buffer before disabling the module.
PIC24F16KA102 FAMILY
DS39927C-page 176 2008-2011 Microchip Technology Inc.
REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0
VCFG2 VCFG1 VCFG0 OFFCAL(1)— CSCNA — —
bit 15 bit 8
R-0, HSC
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
bit 12 OFFCAL: Offset Calibration bit(1)
1 = Converts to get the offset calibration value
0 = Converts to get the actual input value
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling buffer, 08-0F; user should access data in 00-07
0 = A/D is currently filling buffer, 00-07; user should access data in 08-0F
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.
.
.
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to
zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG
contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter
in this mode. The conversion result is stored by the user software and used to compensate subsequent
conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit
set to all normal A/D conversions.
VCFG<2:0> VR+VR-
000 AVDD AVSS
001 External VREF+ pin AVSS
010 AVDD External VREF- pin
011 External VREF+ pin External VREF- pin
1xx AVDD AVSS
2008-2011 Microchip Technology Inc. DS39927C-page 177
PIC24F16KA102 FAMILY
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer is configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)
0 = Buffer is configured as one 16-word buffer (ADC1BUFn<15:0>)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and
MUX A input multiplexer settings for all subsequent samples
0 = Always uses MUX A input multiplexer settings
REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to
zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG
contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter
in this mode. The conversion result is stored by the user software and used to compensate subsequent
conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit
set to all normal A/D conversions.
REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC —— SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
bit 15 bit 8
U
-0
U
-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: A/D Conversion Clock Source bit
1 = A/D internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 T
AD
·
·
·
00001 = 1 TAD
00000 = 0 TAD (not recommended)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits
111111 = 64 • T
CY
111110 = 63 • TCY
·
·
·
000001 = 3 • TCY
000000 = 2 • TCY
PIC24F16KA102 FAMILY
DS39927C-page 178 2008-2011 Microchip Technology Inc.
-
REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8
R/W
-0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 14-12 Unimplemented: Read as ‘0’
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits
1111 = Channel 0 positive input is band gap reference (VBG)
1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2)
1101 = No channels connected (actual A/D MUX switch activates, but input floats); used for CTMU
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Reserved
1000 = Reserved
0111 = AVDD
0110 = AVSS
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0011 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 6-4 Unimplemented: Read as ‘0’
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for Sample A bits
1111 = Channel 0 positive input is band gap reference (VBG)
1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2)
1101 = No channels connected (actual A/D MUX switch activates but input floats); used for CTMU
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Reserved
1000 = Reserved
0111 = AVDD
0110 = AVSS
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0011 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
2008-2011 Microchip Technology Inc. DS39927C-page 179
PIC24F16KA102 FAMILY
REGISTER 22-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PCFG15 PCFG14 — PCFG12 PCFG11 PCFG10 — —
bit 15 bit 8
U
-0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PCFG15: Analog Input Pin Configuration Control bit
1 = Analog channel is disabled from input scan
0 = Internal band gap (VBG) channel is enabled for input scan
bit 14 PCFG14: Analog Input Pin Configuration Control bit
1 = Analog channel is disabled from input scan
0 = Internal VBG/2 channel is enabled for input scan
bit 13 Unimplemented: Read as ‘0’
bit 12-10 PCFG<12:10>: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled; A/D samples pin voltage
bit 9-6 Unimplemented: Read as ‘0’
bit 5-0 PCFG<5:0>: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin configured in Analog mode; I/O port read is disabled; A/D samples pin voltage
PIC24F16KA102 FAMILY
DS39927C-page 180 2008-2011 Microchip Technology Inc.
REGISTER 22-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — — CSSL12 CSSL11 CSSL10 — —
bit 15 bit 8
U
-0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-10 CSSL<12:10>: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel is selected for input scan
0 = Analog channel omitted from input scan
bit 9-6 Unimplemented: Read as ‘0’
bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel is selected for input scan
0 = Analog channel omitted from input scan
2008-2011 Microchip Technology Inc. DS39927C-page 181
PIC24F16KA102 FAMILY
EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1)
FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TAD = TCY • (ADCS + 1)
TAD
TCY
ADCS = – 1
CPIN
VA
Rs ANx VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 250Sampling
Switch
RSS
CHOLD
= A/D capacitance
VSS
VDD
= 4.4 pF (Typical)
±500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from A/D)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k.
RSS 5 k (Typical)
6-11 pF
(Typical)
PIC24F16KA102 FAMILY
DS39927C-page 182 2008-2011 Microchip Technology Inc.
FIGURE 22-3: A/D TRANSFER FUNCTION
10 0000 0001 (513)
10 0000 0010 (514)
10 0000 0011 (515)
01 1111 1101 (509)
01 1111 1110 (510)
01 1111 1111 (511)
11 1111 1110 (1022)
11 1111 1111 (1023)
00 0000 0000 (0)
00 0000 0001 (1)
Output Code
10 0000 0000 (512)
(VINH – VINL)
VR-
VR+ – VR-
1024
512 * (VR+ – VR-)
1024
VR+
VR- +
VR- +
1023 * (VR+ – VR-)
1024
VR- +
0
(Binary (Decimal))
Voltage Level
2008-2011 Microchip Technology Inc. DS39927C-page 183
PIC24F16KA102 FAMILY
23.0 COMPARATOR MODULE
The comparator module provides two dual input
comparators. The inputs to the comparator can be
configured to use any one of four external analog
inputs, as well as a voltage reference input from either
the internal band gap reference, divided by 2 (VBG/2),
or the comparator voltage reference generator.
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module is displayed
in Figure 23-1. Diagrams of the possible individual
comparator configurations are displayed in
Figure 23-2.
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 23-2).
FIGURE 23-1: COMPARATOR MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Comparator module, refer to the “PIC24F
Family Reference Manual”, Section 46.
“Scalable Comparator Module”
(DS39734).
C1
VIN-
VIN+
CXINB
CXINC
CXINA
CXIND
CVREF
VBG/2
C2
VIN-
VIN+
COE
C1OUT
Pin
CPOL
Trigger/Interrupt
Logic
CEVT
EVPOL<1:0>
COUT
Input
Select
Logic
CCH<1:0>
CREF
COE
C2OUT
Pin
CPOL
Trigger/Interrupt
Logic
CEVT
EVPOL<1:0>
COUT
PIC24F16KA102 FAMILY
DS39927C-page 184 2008-2011 Microchip Technology Inc.
FIGURE 23-2: INDIVIDUAL COMPARATOR CON FIGURATIONS
Cx
VIN-
VIN+Off (Read as ‘0’)
Comparator Off
CON = 0, CREF = x, CCH<1:0> = xx
Comparator CxINB < CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 00
COE
CxOUT
Cx
VIN-
VIN+
COE
CXINB
CXINA
Comparator CxIND < CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 10
Cx
VIN-
VIN+
COE
CxOUT
CXIND
CXINA
Comparator CxINC < CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 01
Cx
VIN-
VIN+
COE
CXINC
CXINA
Comparator VBG/2 < CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 11
Cx
VIN-
VIN+
COE
VBG/2
CXINA
Comparator CxINB < CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 00
Cx
VIN-
VIN+
COE
CXINB
CVREF
Comparator CxIND < CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 10
Cx
VIN-
VIN+
COE
CXIND
CVREF
Comparator CxINC < CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 01
Cx
VIN-
VIN+
COE
CXINC
CVREF
Comparator VBG/2 < CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 11
Cx
VIN-
VIN+
COE
VBG/2
CVREF
Pin
Pin
CxOUT
Pin
CxOUT
Pin
CxOUT
Pin
CxOUT
Pin
CxOUT
Pin
CxOUT
Pin
CxOUT
Pin
-
-
-
-
--
-
-
-
2008-2011 Microchip Technology Inc. DS39927C-page 185
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REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0
CON COE CPOL CLPWR —— CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL1 EVPOL0 — CREF —— CCH1 CCH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12 CLPWR: Comparator Low-Power Mode Select bit
1 = Comparator operates in Low-Power mode
0 = Comparator does not operate in Low-Power mode
bit 11-10 Unimplemented: Read as ‘0’
bit 9 CEVT: Comparator Event bit
1 = Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8 COUT: Comparator Output bit
When CPOL = 0:
1 =VIN+ > VIN-
0 =V
IN+ < VIN-
When CPOL = 1:
1 =VIN+ < VIN-
0 =V
IN+ > VIN-
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
PIC24F16KA102 FAMILY
DS39927C-page 186 2008-2011 Microchip Technology Inc.
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to the internal CVREF voltage
0 = Non-inverting input connects to the CxINA pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of comparator connects to VBG/2
10 = Inverting input of comparator connects to CxIND pin
01 = Inverting input of comparator connects to CxINC pin
00 = Inverting input of comparator connects to CxINB pin
REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED)
REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC
CMIDL — — — — — C2EVT C1EVT
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC
— — — — — — C2OUT C1OUT
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CMIDL: Comparator Stop in Idle Mode bit
1 = Disable comparator interrupts when the device enters Idle mode; the module is still enabled
0 = Continue operation of all enabled comparators in Idle mode
bit 14-10 Unimplemented: Read as ‘0’
bit 9 C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON<9>).
bit 8 C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON<9>).
bit 7-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON<8>).
bit 0 C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON<8>).
2008-2011 Microchip Technology Inc. DS39927C-page 187
PIC24F16KA102 FAMILY
24.0 COMPARATOR VOLTAGE
REFERENCE 24.1 Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 24-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON<5>).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR<3:0>), with one range offering finer resolution.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Comparator Voltage Reference, refer to
the “PIC24F Family Reference Manual”,
Section 20. “Comparator Voltage
Reference Module” (DS39709).
16-to-1 MUX
CVR<3:0>
8R
R
CVREN
CVRSS = 0
AVDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
AVSS
PIC24F16KA102 FAMILY
DS39927C-page 188 2008-2011 Microchip Technology Inc.
REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF circuit is powered on
0 =CV
REF circuit is powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 =CVREF voltage level is output on CVREF pin
0 =CV
REF voltage level is disconnected from CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 =CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size
0 =CV
RSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = VREF+ – VREF-
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1 and CVRSS = 0:
CVREF = (CVR<3:0>/24) * (CVRSRC)
When CVRR = 0 and CVRSS = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)
When CVRR = 1 and CVRSS = 1:
CVREF = ((CVR<3:0>/24) * (CVRSRC)) + VREF-
When CVRR = 0 and CVRSS = 1:
CVREF = (1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)) + VREF-
2008-2011 Microchip Technology Inc. DS39927C-page 189
PIC24F16KA102 FAMILY
25.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides charge measure-
ment, accurate differential time measurement between
pulse sources and asynchronous pulse generation. Its
key features include:
• Four-edge input trigger sources
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edges
• Time measurement resolution of one nanosecond
• Accurate current source suitable for capacitive
measurement
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance,
or generate output pulses that are independent of the
system clock. The CTMU module is ideal for interfacing
with capacitive-based touch sensors.
The CTMU is controlled through two registers:
CTMUCON and CTMUICON. CTMUCON enables the
module, and controls edge source selection, edge
source polarity selection, and edge sequencing. The
CTMUICON register selects the current range of
current source and trims the current.
25.1 Measuring Capacitance
The CTMU module measures capacitance by
generating an output pulse with a width equal to the
time between edge events on two separate input chan-
nels. The pulse edge events to both input channels can
be selected from four sources: two internal peripheral
modules (OC1 and Timer1) and two external pins
(CTED1 and CTED2). This pulse is used with the mod-
ule’s precision current source to calculate capacitance
according to the relationship:
For capacitance measurements, the A/D Converter
samples an external capacitor (CAPP) on one of its
input channels, after the CTMU output’s pulse. A
precision resistor (RPR) provides current source
calibration on a second A/D channel. After the pulse
ends, the converter determines the voltage on the
capacitor. The actual calculation of capacitance is
performed in software by the application.
Figure 25-1 displays the external connections used for
capacitance measurements, and how the CTMU and
A/D modules are related in this application. This example
also shows the edge events coming from Timer1, but
other configurations using external edge sources are
possible. A detailed discussion on measuring capaci-
tance and time with the CTMU module is provided in the
“PIC24F Family Reference Manual”.
FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
CAPACITANCE MEASUREMENT
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Charge Measurement Unit, refer to the
“PIC24F Family Reference Manual”,
Secti on 11. “C harg e Time Me asur ement
Unit (CTMU)” (DS39724).
I = C • dV
dT
PIC24F Device
A/D Converter
CTMU
ANx
CAPP
Output
Pulse
EDG1
EDG2
RPR
ANY
Timer1
Current Source
PIC24F16KA102 FAMILY
DS39927C-page 190 2008-2011 Microchip Technology Inc.
25.2 Measuring Time
Time measurements on the pulse width can be similarly
performed using the A/D module’s internal capacitor
(CAD) and a precision resistor for current calibration.
Figure 25-2 displays the external connections used for
time measurements, and how the CTMU and A/D
modules are related in this application. This example
also shows both edge events coming from the external
CTED pins, but other configurations using internal
edge sources are possible.
25.3 Pulse Generation and Delay
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON<12>), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the comparator
voltage reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. When CDELAY charges above the CVREF
trip point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of CDELAY and
the CVREF trip point.
Figure 25-3 shows the external connections for pulse
generation, as well as the relationship of the different
analog modules required. While CTED1 is shown as
the input pulse source, other options are available. A
detailed discussion on pulse generation with the CTMU
module is provided in the “PIC24F Family Reference
Manual”.
FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
TIME MEASUREMENT
FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
PULSE DELAY GENERATION
PIC24F Device
A/D Converter
CTMU
CTED1
CTED2
ANx
Output Pulse
EDG1
EDG2
CAD
RPR
Current Source
C2
CVREF
CTPLS
PIC24F Device
Current Source
Comparator
CTMU
CTED1
C2INB
CDELAY
EDG1
-
2008-2011 Microchip Technology Inc. DS39927C-page 191
PIC24F16KA102 FAMILY
REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7 EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 4 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
PIC24F16KA102 FAMILY
DS39927C-page 192 2008-2011 Microchip Technology Inc.
bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 1 EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0 EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
.
.
.
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current
.
.
.
100010
100000 = Maximum negative change from nominal current
bit 9-8 IRNG<1:0>: Current Source Range Select bits
11 = 100 Base current
10 = 10 Base current
01 = Base current level (0.55 A nominal)
00 = Current source is disabled
bit 7-0 Unimplemented: Read as ‘0’
2008-2011 Microchip Technology Inc. DS39927C-page 193
PIC24F16KA102 FAMILY
26.0 SPECIAL FEATURES
PIC24F16KA102 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
26.1 Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped, starting
at program memory location, F80000h. A complete list is
provided in Table 26-1. A detailed explanation of the
various bit functions is provided in Register 26-1 through
Register 26-8.
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
TABLE 26-1: CONFIGURATION REGISTERS
LOCATIONS
REGISTER 26-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
Watchdog Timer, High-Level Device inte-
gration and Programming Diagnostics,
refer to the individual sections of the
“PIC24F Family Reference Manual”
provided below:
•
Section 9. “Watchdog Timer (WDT)”
(DS39697)
•Section 36. “High-Level Integration
with Programmable High/
Low-Volt age Detect (HLVD)”
(DS39725)
•Section 33. “Programming and
Diagnostics” (DS39716)
Configuration
Register Address
FBS F80000
FGS F80004
FOSCSEL F80006
FOSC F80008
FWDT F8000A
FPOR F8000C
FICD F8000E
FDS F80010
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
———— BSS2 BSS1 BSS0 BWRP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-1 BSS<2:0>: Boot Segment Program Flash Code Protection bits
111 = No boot program Flash segment
011 = Reserved
110 = Standard security, boot program Flash segment starts at 200h, ends at 000AFEh
010 = High-security boot program Flash segment starts at 200h, ends at 000AFEh
101 = Standard security, boot program Flash segment starts at 200h, ends at 0015FEh(1)
001 = High-security, boot program Flash segment starts at 200h, ends at 0015FEh(1)
100 = Reserved
000 = Reserved
bit 0 BWRP: Boot Segment Program Flash Write Protection bit
1 = Boot segment may be written
0 = Boot segment is write-protected
Note 1: This selection should not be used in PIC24F08KA1XX devices.
PIC24F16KA102 FAMILY
DS39927C-page 194 2008-2011 Microchip Technology Inc.
REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER
REGISTER 26-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1
— — — — — — GSS0 GWRP
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1 GSS0: General Segment Code Flash Code Protection bit
1 = No protection
0 = Standard security is enabled
bit 0 GWRP: General Segment Code Flash Write Protection bit
1 = General segment may be written
0 = General segment is write-protected
R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1
IESO — — — — FNOSC2 FNOSC1 FNOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6-3 Unimplemented: Read as ‘0’
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)
011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = 500 kHz Low-Power FRC Oscillator with divide-by-N (LPFRCDIV)
111 = 8 MHz FRC Oscillator with divide-by-N (FRCDIV)
2008-2011 Microchip Technology Inc. DS39927C-page 195
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REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
FCKSM1 FCKSM0 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC POSCMD1 POSCMD0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 SOSCSEL: Secondary Oscillator Select bit
1 = Secondary oscillator is configured for high-power operation
0 = Secondary oscillator is configured for low-power operation
bit 4-3 POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits
11 = Primary oscillator/external clock input frequency is greater than 8 MHz
10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz
01 = Primary oscillator/external clock input frequency is less than 100 kHz
00 = Reserved; do not use
bit 2 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00)
0 = CLKO output is disabled
bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator mode is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock mode is selected
PIC24F16KA102 FAMILY
DS39927C-page 196 2008-2011 Microchip Technology Inc.
REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER
R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FWDTEN: Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
bit 6 WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard WDT is selected; windowed WDT disabled
0 = Windowed WDT is enabled
bit 5 Unimplemented: Read as ‘0’
bit 4 FWPSA: WDT Prescaler bit
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
2008-2011 Microchip Technology Inc. DS39927C-page 197
PIC24F16KA102 FAMILY
REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1
MCLRE(2)BORV1(3)BORV0(3)I2C1SEL(1)PWRTEN — BOREN1 BOREN0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MCLRE: MCLR Pin Enable bit(2)
1 = MCLR pin is enabled; RA5 input pin is disabled
0 = RA5 input pin is enabled; MCLR is disabled
bit 6-5 BORV<1:0>: Brown-out Reset Enable bits(3)
11 = Brown-out Reset is set to the lowest voltage
10 = Brown-out Reset
01 = Brown-out Reset is set to the highest voltage
00 = Low-Power Brown-out Reset occurs around 2.0V
bit 4 I2C1SEL: Alternate I2C1 Pin Mapping bit(1)
0 = Alternate location for SCL1/SDA1 pins
1 = Default location for SCL1/SDA1 pins
bit 3 PWRTEN: Power-up Timer Enable bit
0 = PWRT is disabled
1 = PWRT is enabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
Note 1: Applies only to 28-pin devices.
2: The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a
user from accidentally locking out the device from the low-voltage test entry.
3: Refer to Section 29.0, Electrical Characteristics for the BOR voltages.
PIC24F16KA102 FAMILY
DS39927C-page 198 2008-2011 Microchip Technology Inc.
REGISTER 26-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER
R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1
DEBUG — — — — — FICD1 FICD0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 DEBUG: Background Debugger Enable bit
1 = Background debugger is disabled
0 = Background debugger functions are enabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1-0 FICD<1:0:> ICD Pin Select bits
11 = PGC1/PGD1 are used for programming and debugging the device
10 = PGC2/PGD2 are used for programming and debugging the device
01 = PGC3/PGD3 are used for programming and debugging the device
00 = Reserved; do not use
2008-2011 Microchip Technology Inc. DS39927C-page 199
PIC24F16KA102 FAMILY
REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DSWDTEN DSBOREN RTCOSC DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = DSWDT is enabled
0 = DSWDT is disabled
bit 6 DSBOREN: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes)
1 = Deep Sleep BOR is enabled in Deep Sleep
0 = Deep Sleep BOR is disabled in Deep Sleep
bit 5 RTCOSC: RTCC Reference Clock Select bit
1 = RTCC uses SOSC as a reference clock
0 = RTCC uses LPRC as a reference clock
bit 4 DSWDTOSC: DSWDT Reference Clock Select bit
1 = DSWDT uses LPRC as a reference clock
0 = DSWDT uses SOSC as a reference clock
bit 3-0 DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days) nominal
1110 = 1:536,870,912 (6.4 days) nominal
1101 = 1:134,217,728 (38.5 hours) nominal
1100 = 1:33,554,432 (9.6 hours) nominal
1011 = 1:8,388,608 (2.4 hours) nominal
1010 = 1:2,097,152 (36 minutes) nominal
1001 = 1:524,288 (9 minutes) nominal
1000 = 1:131,072 (135 seconds) nominal
0111 = 1:32,768 (34 seconds) nominal
0110 = 1:8,192 (8.5 seconds) nominal
0101 = 1:2,048 (2.1 seconds) nominal
0100 = 1:512 (528 ms) nominal
0011 = 1:128 (132 ms) nominal
0010 = 1:32 (33 ms) nominal
0001 = 1:8 (8.3 ms) nominal
0000 = 1:2 (2.1 ms) nominal
PIC24F16KA102 FAMILY
DS39927C-page 200 2008-2011 Microchip Technology Inc.
REGISTER 26-9: DEVID: DEVICE ID REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
RRRRRRRR
FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0
bit 15 bit 8
RRRRRRRR
DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘0’
bit 15-8 FAMID<7:0>: Device Family Identifier bits
00001011 = PIC24F16KA102 family
bit 7-0 DEV<7:0>: Individual Device Identifier bits
00000011 = PIC24F16KA102
00001010 = PIC24F08KA102
00000001 = PIC24F16KA101
00001000 = PIC24F08KA101
REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R R R R
———— REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-4 Unimplemented: Read as ‘0’
bit 3-0 REV<3:0>: Minor Revision Identifier bits
2008-2011 Microchip Technology Inc. DS39927C-page 201
PIC24F16KA102 FAMILY
26.2 Watchdog Timer (WDT)
For the PIC24F16KA102 family of devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction During normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
26.2.1 WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last
1/4 of the programmed WDT period. A CLRWDT instruc-
tion executed before that window causes a WDT
Reset, similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
26.2.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
FIGURE 26-1: WDT BLOCK DIAGRAM
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
LPRC Input WDT Overflow
Wake from Sleep
31 kHz
Prescaler Postscaler
FWPSA
SWDTEN
FWDTEN
Reset
All Device Resets
Sleep or Idle Mode
LPRC Control
CLRWDT Instr.
PWRSAV Instr.
(5-Bit/7-Bit) 1:1 to 1:32.768
WDTPS<3:0>
1 ms/4 ms
Exit Sleep or
Idle Mode
WDT
Counter
Transition to
New Clock Source
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DS39927C-page 202 2008-2011 Microchip Technology Inc.
26.3 Deep Sleep Watchdog Timer
(DSWDT)
In PIC24F16KA102 family devices, in addition to the
WDT module, a DSWDT module is present which runs
while the device is in Deep Sleep, if enabled. It is
driven by either the SOSC or LPRC oscillator. The
clock source is selected by the Configuration bit,
DSWDTOSC (FDS<4>).
The DSWDT can be configured to generate a time-out
at 2.1 ms to 25.7 days by selecting the respective
postscaler. The postscaler can be selected by the
Configuration bits, DSWDTPS<3:0> (FDS<3:0>).
When the DSWDT is enabled, the clock source is also
enabled.
DSWDT is one of the sources that can wake-up the
device from Deep Sleep mode.
26.4 Program Verification and
Code Protection
For all devices in the PIC24F16KA102 family, code
protection for the boot segment is controlled by the
Configuration bit, BSS0, and the general segment by
the Configuration bit, GSS0. These bits inhibit external
reads and writes to the program memory space; this
has no direct effect in normal execution mode.
Write protection is controlled by bit, BWRP, for the boot
segment and bit, GWRP, for the general segment in the
Configuration Word. When these bits are programmed
to ‘0’, internal write and erase operations to program
memory are blocked.
26.5 In-Circuit Serial Programming
PIC24F16KA102 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
26.6 In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This
function allows simple debugging functions when used
with MPLAB IDE. Debugging functionality is controlled
through the EMUCx (Emulation/Debug Clock) and
EMUDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, PGCx, PGDx and the
EMUDx/EMUCx pin pair. In addition, when the feature
is enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
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PIC24F16KA102 FAMILY
27.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
27.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
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DS39927C-page 204 Preliminary 2008-2011 Microchip Technology Inc.
27.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
27.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
27.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
2008-2011 Microchip Technology Inc. Preliminary DS39927C-page 205
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27.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
27.8 MPLAB REAL ICE In-Circ uit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
27.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
27.10 PICkit 3 In-Cir cuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
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DS39927C-page 206 Preliminary 2008-2011 Microchip Technology Inc.
27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
27.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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28.0 INSTRUCTION SET SUMMARY
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while
maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
Table 28-1 lists the general symbols used in describing
the instructions. The PIC24F instruction set summary
in Ta bl e 28-2 lists all the instructions, along with the
status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register, specified by the value, ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register, where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all of the required
information is available in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect
CALL/GOTO, all table reads and writes, and
RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
Certain instructions that involve skipping over the
subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
Note: This chapter is a brief summary of the
PIC24F instruction set architecture and is
not intended to be a comprehensive
reference source.
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DS39927C-page 208 2008-2011 Microchip Technology Inc.
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0000h...1FFFh}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’
None Field does not require an entry, may be blank
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit6 6-bit signed literal {-16...16}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
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TABLE 28-2: INSTRUCTION SET OVERVIEW
Assembly
Mnemonic Assembly Syntax Description # of
Words # of
Cycles Status Flags
Affected
ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z
ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z
ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z
AND AND f f = f .AND. WREG 1 1 N, Z
AND f,WREG WREG = f .AND. WREG 1 1 N, Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z
ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z
BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None
BRA GT,Expr Branch if Greater than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None
BRA LE,Expr Branch if Less than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1
(2 or 3)
None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1
(2 or 3)
None
PIC24F16KA102 FAMILY
DS39927C-page 210 2008-2011 Microchip Technology Inc.
BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1
(2 or 3)
None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1
(2 or 3)
None
BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep
COM COM f f = f 11N, Z
COM f,WREG WREG = f 11N, Z
COM Ws,Wd Wd = Ws 11N, Z
CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z
CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z
CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z
CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z
CPB Wb,Ws Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1 1 C, DC, N, OV, Z
CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1
(2 or 3)
None
CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1
(2 or 3)
None
CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1
(2 or 3)
None
CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if 11
(2 or 3)
None
DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C
DEC DEC f f = f –1 1 1 C, DC, N, OV, Z
DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z
DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z
DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z
DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z
DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV
EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic Assembly Syntax Description # of
Words # of
Cycles Status Flags
Affected
2008-2011 Microchip Technology Inc. DS39927C-page 211
PIC24F16KA102 FAMILY
GOTO GOTO Expr Go to Address 2 2 None
GOTO Wn Go to Indirect 1 2 None
INC INC f f = f + 1 1 1 C, DC, N, OV, Z
INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z
INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z
IOR IOR f f = f .IOR. WREG 1 1 N, Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z
LNK LNK #lit14 Link Frame Pointer 1 1 None
LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z
MOV MOV f,Wn Move f to Wn 1 1 None
MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None
MOV f Move f to f 1 1 N, Z
MOV f,WREG Move f to WREG 1 1 N, Z
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N, Z
MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z
NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z
NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z
NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None
POP.S Pop Shadow Registers 1 1 All
PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic Assembly Syntax Description # of
Words # of
Cycles Status Flags
Affected
PIC24F16KA102 FAMILY
DS39927C-page 212 2008-2011 Microchip Technology Inc.
PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep
RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
RESET RESET Software Device Reset 1 1 None
RETFIE RETFIE Return from Interrupt 1 3 (2) None
RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
RETURN RETURN Return from Subroutine 1 3 (2) None
RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z
RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z
RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z
RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z
SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z
SETM SETM f f = FFFFh 1 1 None
SETM WREG WREG = FFFFh 1 1 None
SETM Ws Ws = FFFFh 1 1 None
SL SL f f = Left Shift f 1 1 C, N, OV, Z
SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z
SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z
SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z
SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z
SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z
SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z
SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z
SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None
TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic Assembly Syntax Description # of
Words # of
Cycles Status Flags
Affected
2008-2011 Microchip Technology Inc. DS39927C-page 213
PIC24F16KA102 FAMILY
TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
ULNK ULNK Unlink Frame Pointer 1 1 None
XOR XOR f f = f .XOR. WREG 1 1 N, Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z
ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic Assembly Syntax Description # of
Words # of
Cycles Status Flags
Affected
PIC24F16KA102 FAMILY
DS39927C-page 214 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 215
PIC24F16KA102 FAMILY
29.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24F16KA102 family electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24F16KA102 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +175°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V
Voltage on any combined analog and digital pin, with respect to VSS ........................................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V)
Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (1)..........................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (1)..............................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Tabl e 2 9-1 ).
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
PIC24F16KA102 FAMILY
DS39927C-page 216 2008-2011 Microchip Technology Inc.
29.1 DC Characteristics
FIGURE 29-1: PIC24F16 KA10 2 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 29-2: PIC24F16KA10 2 FAM I LY VOLTAGE-FREQUENCY GRAPH
(INDUSTRIAL, EXTENDED)
Frequency (MHz)
Voltage (VDD)
1.80V
32 MHz
3.60V
3.00V
3.60V
8 MHz
Note: For Industrial temperatures, for frequencies between 8 MHz and 32 MHz,
FMAX = (20 MHz/V) * (VDD – 1.8V) + 8 MHz.
0
24 MHz16 MHz0
3.00V
Frequency (MHz)
Voltage (VDD)
1.80V
32 MHz
3.60V
3.00V
3.60V
8 MHz
3.00V
Note: For Extended temperatures, for frequencies between 8 MHz and 24 MHz,
FMAX = (13.33 MHz/V) * (VDD – 1.8V) + 8 MHz.
0
24 MHz16 MHz0
2008-2011 Microchip Technology Inc. DS39927C-page 217
PIC24F16KA102 FAMILY
TABLE 29-1: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
Operating Junction Temperature Range TJ-40 — +175 °C
Operating Ambient Temperature Range TA-40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)PDPINT + PI/OW
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 20-Pin PDIP JA 62.4 — °C/W 1
Package Thermal Resistance, 28-Pin SPDIP JA 60 — °C/W 1
Package Thermal Resistance, 20-Pin SSOP JA 108 — °C/W 1
Package Thermal Resistance, 28-Pin SSOP JA 71 — °C/W 1
Package Thermal Resistance, 20-Pin SOIC JA 75 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC JA 80.2 — °C/W 1
Package Thermal Resistance, 20-Pin QFN JA 43 — °C/W 1
Package Thermal Resistance, 28-Pin QFN JA 32 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
PIC24F16KA102 FAMILY
DS39927C-page 218 2008-2011 Microchip Technology Inc.
TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS
TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS S tandard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
DC10 VDD Supply Voltage 1.8 — 3.6 V
DC12 VDR RAM Data Retention
Voltage(2)1.5 — — V
DC16 VPOR VDD St art Voltage
to Ensure Internal
Power-on Reset Signal
VSS —0.7V
DC17 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05 — — V/ms 0-3.3V in 0.1s
0-2.5V in 60 ms
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
DC18 VHLVD HLVD Voltage on VDD
Transition
HLVDL<3:0> = 0000 —1.851.94V
HLVDL<3:0> = 0001 1.81 1.90 2.00 V
HLVDL<3:0> = 0010 1.85 1.95 2.05 V
HLVDL<3:0> = 0011 1.90 2.00 2.10 V
HLVDL<3:0> = 0100 1.95 2.05 2.15 V
HLVDL<3:0> = 0101 2.06 2.17 2.28 V
HLVDL<3:0> = 0110 2.12 2.23 2.34 V
HLVDL<3:0> = 0111 2.24 2.36 2.48 V
HLVDL<3:0> = 1000 2.31 2.43 2.55 V
HLVDL<3:0> = 1001 2.47 2.60 2.73 V
HLVDL<3:0> = 1010 2.64 2.78 2.92 V
HLVDL<3:0> = 1011 2.74 2.88 3.02 V
HLVDL<3:0> = 1100 2.85 3.00 3.15 V
HLVDL<3:0> = 1101 2.96 3.12 3.28 V
HLVDL<3:0> = 1110 3.22 3.39 3.56 V
2008-2011 Microchip Technology Inc. DS39927C-page 219
PIC24F16KA102 FAMILY
FIGURE 29-3: BROWN-OUT RESET CHARACTERISTICS
TABLE 29-5: BOR TRIP POINTS
Standard Opera ting C onditions (u nl ess otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Param
No. Sym Characteristic Min Typ Max Units Conditions
DC19 VBOR BOR Voltage on VDD Transition BOR = 00 — — — — LPBOR(1)
BOR = 01 2.92 3 3.08 V
BOR = 10 2.63 2.7 2.77 V
BOR = 11 1.75 1.82 1.85 V
DC14 VBHYS BOR Hysteresis — 5 — mV
Note 1: LPBOR re-arms the POR circuit, but does not cause a BOR. LPBOR can be used to ensure a POR after the sup-
ply voltage rises to a safe operating level. It does not stop code execution after the supply voltage falls below a
chosen trip point.
BO10
Reset (Due to BOR)
VDDCORE
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
TVREG + TRST
BO15
SY25
PIC24F16KA102 FAMILY
DS39927C-page 220 2008-2011 Microchip Technology Inc.
TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Paramete r No. Typical(1)Max Units Conditions
IDD Current(2)
DC20
195
330
A
-40°C
1.8V
0.5 MIPS,
FOSC = 1 MHz
DS20a 330 +25°C
DC20b 330 +60°C
DC20c 330 +85°C
DC20d 500 +125°C
DC20e
365
590
A
-40°C
3.3V
DC20f 590 +25°C
DC20g 645 +60°C
DC20h 720 +85°C
DC20i 800 +125°C
DC22
363
600
A
-40°C
1.8V
1 MIPS,
FOSC = 2 MHz
DC22a 600 +25°C
DC22b 600 +60°C
DC22c 600 +85°C
DC22d 800 +125°C
DC22e
695
1100
A
-40°C
3.3V
DC22f 1100 +25°C
DC22g 1100 +60°C
DC22h 1100 +85°C
DC22i 1500 +125°C
DC23
11
18
mA
-40°C
3.3V 16 MIPS,
FOSC = 32 MHz
DC23a 18 +25°C
DC23b 18 +60°C
DC23c 18 +85°C
DC23d 18 +125°C
DC27
2.25
3.40
mA
-40°C
2.5V
FRC (4 MIPS),
FOSC = 8 MHz
DC27a 3.40 +25°C
DC27b 3.40 +60°C
DC27c 3.40 +85°C
DC27d 3.40 +125°C
DC27e
3.05
4.60
mA
-40°C
3.3V
DC27f 4.60 +25°C
DC27g 4.60 +60°C
DC27h 4.60 +85°C
DC27i 5.40 +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: Operating Parameters:
• EC mode with clock input driven with a square wave rail-to-rail
• I/Os are configured as outputs, driven low
• MCLR – VDD
• WDT FSCM is disabled
• SRAM, program and data memory are active
• All PMD bits are set except for modules being measured
2008-2011 Microchip Technology Inc. DS39927C-page 221
PIC24F16KA102 FAMILY
DC31
8
28
A
-40°C
1.8V
LPRC (31 kHz)
DC31a 28 +25°C
DC31b 28 +60°C
DC31c 28 +85°C
DC31d
15
55
A
-40°C
3.3V
DC31e 55 +25°C
DC31f 55 +60°C
DC31g 55 +85°C
DC31h 250 +125°C
TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONT INUED )
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Paramete r No. Typical(1)Max Units Conditions
IDD Current(2)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: Operating Parameters:
• EC mode with clock input driven with a square wave rail-to-rail
• I/Os are configured as outputs, driven low
• MCLR – VDD
• WDT FSCM is disabled
• SRAM, program and data memory are active
• All PMD bits are set except for modules being measured
PIC24F16KA102 FAMILY
DS39927C-page 222 2008-2011 Microchip Technology Inc.
TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No. Typical(1)Max Units Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set(2)
DC40
48
100
A
-40°C
1.8V
0.5 MIPS,
FOSC = 1 MHz
DC40a 100 +25°C
DC40b 100 +60°C
DC40c 100 +85°C
DC40d 100 +125°C
DC40e
106
215
A
-40°C
3.3V
DC40f 215 +25°C
DC40g 215 +60°C
DC40h 215 +85°C
DC40i 450 +125°C
DC42
94
200
A
-40°C
1.8V
1 MIPS,
FOSC = 2 MHz
DC42a 200 +25°C
DC42b 200 +60°C
DC42c 200 +85°C
DC42d 300 +125°C
DC42e
160
395
A
-40°C
3.3V
DC42f 395 +25°C
DC42g 395 +60°C
DC42h 395 +85°C
DC42i 600 +125°C
DC43
3.1
6.0
mA
-40°C
3.3V 16 MIPS,
FOSC = 32 MHz
DC43a 6.0 +25°C
DC43b 6.0 +60°C
DC43c 6.0 +85°C
DC43d 6.0 +125°C
DC44
0.56
0.74
mA
-40°C
1.8V
FRC (4 MIPS),
FOSC = 8 MHz
DC44a 0.74 +25°C
DC44b 0.74 +60°C
DC44c 0.74 +85°C
DC44d 0.74 +125°C
DC44e
0.95
1.50
mA
-40°C
3.3V
DC44f 1.50 +25°C
DC44g 1.50 +60°C
DC44h 1.50 +85°C
DC44i 1.50 +125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Operating Parameters:
• Core is off
• EC mode with the clock input driven with a square wave rail-to-rail
• I/Os are configured as outputs, driven low
• MCLR – VDD
• WDT FSCM are disabled
• SRAM, program and data memory are active
• All PMD bits are set except for the modules being measured
2008-2011 Microchip Technology Inc. DS39927C-page 223
PIC24F16KA102 FAMILY
DC50
2
18
A
-40°C
1.8V
LPRC (31 kHz)
DC50a 18 +25°C
DC50b 18 +60°C
DC50c 18 +85°C
DC50d
4
40 -40°C
3.3V
DC50e 40 +25°C
DC50f 40 +60°C
DC50g 40 +85°C
DC50h 60 +125°C
TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param No. Typical(1)Max Units Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set(2)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Operating Parameters:
• Core is off
• EC mode with the clock input driven with a square wave rail-to-rail
• I/Os are configured as outputs, driven low
• MCLR – VDD
• WDT FSCM are disabled
• SRAM, program and data memory are active
• All PMD bits are set except for the modules being measured
PIC24F16KA102 FAMILY
DS39927C-page 224 2008-2011 Microchip Technology Inc.
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC60
0.025
0.200
A
-40°C
1.8V
Base Power-Down Current
(Sleep)(3)
DC60a 0.200 +25°C
DC60b 0.870 +60°C
DC60c 1.350 +85°C
DC60d 10.00 +125°C
DC60e
0.105
0.540
A
-40°C
3.3V
DC60f 0.540 +25°C
DC60g 1.680 +60°C
DC60h 2.450 +85°C
DC60i 11.00 +125°C
DC70
0.020
0.150
A
-40°C
1.8V
Base Deep Sleep Current
DC70a 0.150 +25°C
DC70b 0.430 +60°C
DC70c 0.630 +85°C
DC70d 3.00 +125°C
DC70e
0.035
0.300
A
-40°C
3.3V
DC70f 0.300 +25°C
DC70g 0.700 +60°C
DC70h 0.980 +85°C
DC70i 5.00 +125°C
DC61
0.55
0.65
A
-40°C
1.8V
Watchdog Timer Current (WDT)(3,4)
DC61a 0.65 +25°C
DC61b 0.65 +60°C
DC61c 0.65 +85°C
DC61d 1.20 +125°C
DC61e
0.87
0.95
A
-40°C
3.3V
DC61f 0.95 +25°C
DC61g 0.95 +60°C
DC61h 0.95 +85°C
DC61i 1.50 +125°C
Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low.
WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: Current applies to Sleep only.
5: Current applies to Sleep and Deep Sleep.
6: Current applies to Deep Sleep only.
2008-2011 Microchip Technology Inc. DS39927C-page 225
PIC24F16KA102 FAMILY
DC62
0.450
0.650
A
-40°C
1.8V
Timer1 w/32 kHz Crystal: T132
(SOSC – LP)(3)
DC62a 0.650 +25°C
DC62b 0.650 +60°C
DC62c 0.650 +85°C
DC62d — +125°C
DC62e
0.730
0.980
A
-40°C
3.3V
DC62f 0.980 +25°C
DC62g 0.980 +60°C
DC62h 0.980 +85°C
DC62i — +125°C
DC64
5.5
7.10
A
-40°C
1.8V
HLVD(3,4)
DC64a 7.10 +25°C
DC64b 7.80 +60°C
DC64c 8.30 +85°C
DC64d 10.00 +125°C
DC64e
6.2
7.10
A
-40°C
3.3V
DC64f 7.10 +25°C
DC64g 7.80 +60°C
DC64h 8.30 +85°C
DC64i 9.00 +125°C
DC63
4.5
6.60
A
-40°C
3.3V BOR(3,4)
DC63a 6.60 +25°C
DC63b 6.60 +60°C
DC63c 6.60 +85°C
DC63d 9.00 +125°C
DC62
0.49
0.65
A
-40°C
1.8V
RTCC(3,5)
DC62a 0.65 +25°C
DC62b 0.65 +60°C
DC62c 0.65 +85°C
DC62d 0.98 +125°C
DC62e
0.80
0.98
A
-40°C
3.3V
DC62f 0.98 +25°C
DC62g 0.98 +60°C
DC62h 0.98 +85°C
DC62i 0.98 +125°C
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CO N T IN UED)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low.
WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: Current applies to Sleep only.
5: Current applies to Sleep and Deep Sleep.
6: Current applies to Deep Sleep only.
PIC24F16KA102 FAMILY
DS39927C-page 226 2008-2011 Microchip Technology Inc.
DC70
0.045
0.200
A
-40°C
1.8V
LPBOR(3,4)
DC70a 0.200 +25°C
DC70b 0.200 +60°C
DC70c 0.200 +85°C
DC70d 1.45 +125°C
DC70e
0.095
0.200
A
-40°C
3.3V
DC70f 0.200 +25°C
DC70g 0.200 +60°C
DC70h 0.200 +85°C
DC70i 1.55 +125°C
DC71
0.35
0.55
A
-40°C
1.8V
Deep Sleep Watchdog Timer:
DSWDT (SOSC – LP)(6)
DC71a 0.55 +25°C
DC71b 0.55 +60°C
DC71c 0.55 +85°C
DC71d 1.70 +125°C
DC71e
0.55
0.75
A
-40°C
3.3V
DC71f 0.75 +25°C
DC71g 0.75 +60°C
DC71h 0.75 +85°C
DC71i 2.10 +125°C
DC72
0.005
0.200
A
-40°C
1.8V
Deep Sleep BOR (DSBOR)(6)
DC72a 0.200 +25°C
DC72b 0.200 +60°C
DC72c 0.200 +85°C
DC72d 0.200 +125°C
DC72e
0.010
0.200
A
-40°C
3.3V
DC72f 0.200 +25°C
DC72g 0.200 +60°C
DC72h 0.200 +85°C
DC72i 0.200 +125°C
TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CO N T IN UED)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Parameter
No. Typical(1)Max Units Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low.
WDT, etc., are all switched off.
3: The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
4: Current applies to Sleep only.
5: Current applies to Sleep and Deep Sleep.
6: Current applies to Deep Sleep only.
2008-2011 Microchip Technology Inc. DS39927C-page 227
PIC24F16KA102 FAMILY
TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS S tandar d Oper ating Conditi ons: 1. 8V to 3.6 V (u nless othe rwis e stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
VIL Input Low Volt ag e(4)————
DI10 I/O Pins VSS — 0.2 VDD V
DI15 MCLR VSS — 0.2 VDD V
DI16 OSCI (XT mode) VSS — 0.2 VDD V
DI17 OSCI (HS mode) VSS — 0.2 VDD V
DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled
VIH(5)Input High Volta ge(4)————
DI20 I/O Pins:
with Analog Functions
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
VDD
V
V
DI25 MCLR 0.8 VDD —VDD V
DI26 OSCI (XT mode) 0.7 VDD —VDD V
DI27 OSCI (HS mode) 0.7 VDD —VDD V
DI28 I/O Pins with I2C Buffer:
with Analog Functions
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
VDD
V
V
DI29 I/O Pins with SMBus 2.1 — VDD V2.5V VPIN VDD
DI30 ICNPU CNx Pull-up Current 50 250 500 AVDD = 3.3V, VPIN = VSS
IIL Input Leakage
Current(2,3)
DI50 I/O Ports — 0.050 ±0.100 AVSS VPIN VDD,
Pin at high-impedance
DI51 VREF+, VREF-, AN0, AN1 — 0.300 ±0.500 AVSS VPIN VDD,
Pin at high-impedance
DI55 MCLR ——±5.0AVSS VPIN VDD
DI56 OSCI — — ±5.0 AVSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Ta b l e 1- 2 for I/O pin buffer types.
5: VIH requirements are met when internal pull-ups are enabled.
PIC24F16KA102 FAMILY
DS39927C-page 228 2008-2011 Microchip Technology Inc.
TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS Standard Op er at ing C onditions: 1.8V to 3.6V (unles s ot her w i se stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
VOL Output Low Voltage
DO10 All I/O Pins — — 0.4 V IOL = 4.0 mA, VDD = 3.6V
——0.4VIOL = 3.5 mA, VDD = 2.0V
DO16 OSC2/CLKO — — 0.4 V IOL = 8.0 mA, VDD = 3.6V
——0.4VIOL = 4.5 mA, VDD = 1.8V
VOH Output High Voltage
DO20 All I/O Pins 3 — — V IOH = -3.0 mA, VDD = 3.6V
1.8 — — V IOH = -1.0 mA, VDD = 2.0V
DO26 OSC2/CLKO 3 — — V IOH = -2.5 mA, VDD = 3.6V
1.8 — — V IOH = -1.0 mA, VDD = 2.0V
Note 1: Data in “Typ” column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not
tested.
2008-2011 Microchip Technology Inc. DS39927C-page 229
PIC24F16KA102 FAMILY
TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS Stand ar d Op er at i ng Conditions: 1.8V to 3.6V (unless otherw i se stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
Program Flash Me m or y
D130 EPCell Endurance 10,000(2)——E/W
D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating voltage
D133A TIW Self-Timed Write Cycle Time — 2 — ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are
violated
D135 IDDP Supply Current During
Programming
—10—mA
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Self-write and block erase.
TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY
DC CHARACTERISTICS Standard Oper at ing C onditions: 1.8V to 3.6V (unless othe rwi se state d)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
Data EEPROM Memory
D140 EPD Cell Endurance 100,000 — — E/W
D141 VPRD VDD for Read VMIN —3.6VVMIN = Minimum operating voltage
D143A TIWD Self-Timed Write Cycle
Time
—4 —ms
D143B TREF Number of Total Write/Erase
Cycles Before Refresh
— 10M — E/W
D144 TRETDD Characteristic Retention 40 — — Year Provided no other specifications are
violated
D145 IDDPD Supply Current During
Programming
—7 —mA
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
PIC24F16KA102 FAMILY
DS39927C-page 230 2008-2011 Microchip Technology Inc.
TABLE 29-13: COMPARATOR DC SPECIFICATIONS
TABLE 29-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
TABLE 29-15: INTERNAL VOLTAGE REFERENCES
Operating Condit ions : 2.0V < VDD < 3.6V
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage*—20 40mV
D301 VICM Input Common Mode Voltage*0—VDD V
D302 CMRR Common Mode Rejection
Ratio*
55 — — dB
* Parameters are characterized but not tested.
Operating Condit ions : 2.0V < VDD < 3.6V
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Comments
VRD310 CVRES Resolution VDD/24 — VDD/32 LSb
VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb
VRD312 CVRUR Unit Resistor Value (R) — 2k —
Operating Condit ions : 2.0V < VDD < 3.6V
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Comments
VBG Internal Band Gap Reference 1.14 1.2 1.26 V
TIRVST Internal Reference Stabilization Time — 200 250 s
TABLE 29-16: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
IOUT1 CTMU Current Source,
Base Range
— 550 — nA CTMUICON<1:0> = 01
IOUT2 CTMU Current Source,
10x Range
—5.5—A CTMUICON<1:0> = 10
IOUT3 CTMU Current Source,
100x Range
—55—A CTMUICON<1:0> = 11
Note 1: Nominal value at the center point of the current trim range (CTMUICON<7:2> = 000000).
2008-2011 Microchip Technology Inc. DS39927C-page 231
PIC24F16KA102 FAMILY
29.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24F16KA102 family AC characteristics and timing parameters.
TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 29-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 29-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Cond itions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Operating voltage VDD range as described in Sectio n 29.1 “ DC Charac teristics ”.
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
DO50 COSC2 OSCO/CLKO pin — — 15 pF In XT and HS modes when
external clock is used to drive
OSCI
DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode
DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL= 464
CL= 50 pF for all pins except OSCO
15 pF for OSCO output
Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO
PIC24F16KA102 FAMILY
DS39927C-page 232 2008-2011 Microchip Technology Inc.
FIGURE 29-5: EXTERN AL CLOCK TIMING
OSCI
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
OS20
OS25
OS30 OS30
OS40 OS41
OS31
OS31
Q1 Q2 Q3 Q4 Q2 Q3
TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS St andard Operating Conditions: 1.8 to 3.6V (unless otherwise st ated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
OS10 FOSC External CLKI Frequency
(External clocks allowed
only in EC mode)(2)
DC
4
—
—
32
8
MHz
MHz
EC
ECPLL
Oscillator Frequency(2)0.2
4
4
31
—
—
—
—
4
25
8
33
MHz
MHz
MHz
kHz
XT
HS
HSPLL
SOSC
OS20 T
OSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC
value
OS25 T
CY Instruction Cycle Time(3)62.5 — DC ns
OS30 TosL,
To s H
External Clock in (OSCI)
High or Low Time
0.45 x TOSC ——nsEC
OS31 TosR,
To s F
External Clock in (OSCI)
Rise or Fall Time
——20nsEC
OS40 TckR CLKO Rise Time(4) —610ns
OS41 TckF CLKO Fall Time(4)—610ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Refer to Figure 29-1 for the minimum voltage at a given frequency.
3: Instruction cycle period (T
CY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
4: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 T
CY) and high for the Q3-Q4 period (1/2 TCY).
2008-2011 Microchip Technology Inc. DS39927C-page 233
PIC24F16KA102 FAMILY
TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V)
AC CHARACTERISTICS
St andard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Sym Characteristic(1)Min Typ(2)Max Units Conditions
OS50 FPLLI PLL Input Frequency
Range
4 — 8 MHz ECPLL, HSPLL modes,
-40°C T
A +85°C
OS51 FSYS PLL Output Frequency
Range
16 — 32 MHz -40°C TA +85°C
OS52 TLOCK PLL Start-up Time
(Lock Time)
—1 2ms
OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over a 100 ms
period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 29-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
Internal FRC Accur acy @ 8 MHz(1)
F20 FRC -1 — +1 % +25°C 3.0V VDD 3.6V
-3 — +3 % -40°C T
A +85°C
-5 — +5 % -40°C TA +85°C 1.8V VDD 3.6V
-10 — +10 % -40°C TA +125°C
F21 LPRC @ 31 kHz(2)
-15 — 15 % +25°C
1.8V VDD 3.6V-15 — 15 % -40°C TA +85°C
-30 — +30 % -40°C TA +125°C
Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
2: Change of LPRC frequency as VDD changes.
PIC24F16KA102 FAMILY
DS39927C-page 234 2008-2011 Microchip Technology Inc.
TABLE 29-22: AC SPECIFICATIONS
TABLE 29-23: A/D CONVERSION TIMING REQUIREMENTS(1)
Symbol Characteristics Min Typ Max Units
TLW BCLKx High Time 20 TCY/2 —ns
THW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 —ns
TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns
TBHD BCLKx Rising Edge Delay from UxTX TCY/2 – 50 —TCY/2 + 50 ns
TWAK Min. Low on UxRX Line to Cause Wake-up —1—s
T
CTS Min. Low on UxCTS Line to Start
Transmission
TCY ——ns
T
SETUP Start bit Falling Edge to System Clock Rising
Edge Setup Time
3——ns
T
STDELAY Maximum Delay in the Detection of the
Start bit Falling Edge
——TCY + TSETUP ns
A/D CHARACTERISTICS
St andard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Clock Parameters
AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3
is in the default state
AD51 TRC A/D Internal RC Oscillator Period — 250 — ns
Conversion Rate
AD55 TCONV Conversion Time — 12 — TAD
AD56 FCNV Throughput Rate — — 500 ksps AVDD 2.7V
AD57 TSAMP Sample Time — 1 — TAD
AD58 TACQ Acquisition Time 750 — — ns (Note 2)
AD59 TSWC Switching Time from Convert to
Sample
——(Note 3)
AD60 TDIS Discharge Time 0.5 — — TAD
Clock Parameters
AD61 TPSS Sample Start Delay from Setting
Sample bit (SAMP)
2— 3 TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD).
3: On the following cycle of the device clock.
2008-2011 Microchip Technology Inc. DS39927C-page 235
PIC24F16KA102 FAMILY
TABLE 29-24: A/D MODULE SPECIFICATIONS
A/D CHARACTERIST ICS St andard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply Greater of
VDD – 0.3
or 1.8
— Lesser of
VDD + 0.3
or 3.6
V
AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V
Reference I npu ts
AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V
AD06 VREFL Reference Voltage Low AVSS —AVDD – 1.7 V
AD07 VREF Absolute Reference
Voltage
AVSS – 0.3 — AVDD + 0.3 V
AD08 IVREF Reference Voltage Input
Current
——200AVREF+ = 3.3V; sampling
——1.0mAVREF+ = 3.3V; converting
AD09 ZVREF Reference Input
Impedance
—10K— (Note 3)
Analog I npu t
AD10 VINH-VINL Full-Scale Input Span VREFL —VREFH V(Note 2)
AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD12 VINL Absolute VINL Input
Voltage
AVSS – 0.3 AVDD/2 V
AD17 RIN Recommended
Impedance of Analog
Voltage Source
— — 2.5K 10-bit
A/D Accuracy
AD20b NRResolution — 10 — bits
AD21b INL Integral Nonlinearity — ±1 ±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22b DNL Differential Nonlinearity — ±1 -1
+1.5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23b GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24b EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25b Monotonicity — — — — (Note 1)
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.
3: Impedance during sampling is at 3.3V, 25°C. This parameter is for design guidance only and is not tested.
PIC24F16KA102 FAMILY
DS39927C-page 236 2008-2011 Microchip Technology Inc.
FIGURE 29-6: CLKO AND I/O TIMING CHARACTERISTICS
Note: Refer to Figure 29-4 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
TABLE 29-25: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Sym Characteristic Min Typ(1)Max Units Conditions
DO31 TIOR Port Output Rise Time — 10 25 ns
DO32 TIOF Port Output Fall Time — 10 25 ns
DI35 TINP INTx pin High or Low
Time (output)
20 — — ns
DI40 TRBP CNx High or Low Time
(input)
2——TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2008-2011 Microchip Technology Inc. DS39927C-page 237
PIC24F16KA102 FAMILY
TABLE 29-26: COMPARATOR TIMINGS
TABLE 29-27: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Param
No. Symbol Characteristic Min Typ Max Units Comments
300 TRESP Response Time*(1)— 150 400 ns
301 TMC2OV Comparator Mode Change to
Output Valid*
—— 10s
* Parameters are characterized but not tested.
Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
Param
No. Symbol Characteristic Min Typ Max Units Comments
VR310 TSET Settling Time(1)——10s
Note 1: Settling time is measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.
PIC24F16KA102 FAMILY
DS39927C-page 238 2008-2011 Microchip Technology Inc.
FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
SYSRST
System
Clock
Watchdog
Timer Reset
SY10
SY20
SY13
I/O Pins
SY13
SY35
SY11
SY12
2008-2011 Microchip Technology Inc. DS39927C-page 239
PIC24F16KA102 FAMILY
FIGURE 29-8: BAUD RATE GENERATOR OUTPUT TIMING
TABLE 29-28: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TI MING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ(1)Max. Units Conditions
SY10 TmcL MCLR Pulse Width (low) 2 — — s
SY11 TPWRT Power-up Timer Period 50 64 90 ms
SY12 TPOR Power-on Reset Delay 1 5 10 s
SY13 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
——100ns
SY20 TWDT Watchdog Timer Time-out Period 0.85 1.0 1.15 ms 1.32 prescaler
3.4 4.0 4.6 ms 1:128 prescaler
SY25 TBOR Brown-out Reset Pulse Width 1 — — s
SY35 TFSCM Fail-Safe Clock Monitor Delay — 2 2.3 s
SY45 TRST Configuration Update Time — 20 — s
SY55 TLOCK PLL Start-up Time — 1 — ms
SY65 TOST Oscillator Start-up Time — 1024 — TOSC
SY75 TFRC Fast RC Oscillator Start-up Time — 1 1.5 s
SY85 TLPRC Low-Power Oscillator Start-up
Time
——100s
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
BCLKx
UxTX
TBLD
TBHD
BRGx + 1 * TCY TLW THW
PIC24F16KA102 FAMILY
DS39927C-page 240 2008-2011 Microchip Technology Inc.
FIGURE 29-9: I 2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
TABLE 29-29: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE)
FIGURE 29-10 : I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial)
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Max Units Conditions
IM30 TSU:STA Start Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s Only relevant for
Repeated Start
condition
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM31 THD:STA Start Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1) — s After this period, the
first clock pulse is
generated
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM33 TSU:STO Stop Condition
Setup Time
100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2)TCY/2 (BRG + 1) — ns
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When
Operating as a Bus Master” for details.
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
SCLx
SDAx
Start
Condition
Stop
Condition
Note: Refer to Figure 29-4 for load conditions.
IM31
IM30
IM34
IM33
SCLx
SDAx
In
SDAx
Out
Note: Refer to Figure 29-4 for load conditions.
IM11
IM10
IM40
IM26 IM25
IM20
IM21
IM45
2008-2011 Microchip Technology Inc. DS39927C-page 241
PIC24F16KA102 FAMILY
TABLE 29-30: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1)Max Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode T
CY/2 (BRG + 1) — s
1 MHz mode(2)TCY/2 (BRG + 1) — s
IM20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)—100ns
IM21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)—300ns
IM25 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(2)TBD — ns
IM26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
1 MHz mode(2)TBD — ns
IM40 TAA:SCL Output Valid
From Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(2)——ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode(2)TBD — s
IM50 CBBus Capacitive Loading — 400 pF
Legend: TBD = To Be Determined
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating
as a B us M as ter” for details.
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
PIC24F16KA102 FAMILY
DS39927C-page 242 2008-2011 Microchip Technology Inc.
FIGURE 29-11: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 29-12 : I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
TABLE 29-31: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C (Industrial)
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min Max Units Conditions
IS30 TSU:STA Start Condition
Setup Time
100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS31 THD:STA Start Condition
Hold Time
100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS33 T
SU:STO Stop Condition
Setup Time
100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
1 MHz mode(1)0.6 — s
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 — ns
1 MHz mode(1)250 — ns
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
SCLx
SDAx
Start
Condition
Stop
Condition
IS31
IS30
IS34
IS33
SCLx
SDAx
In
SDAx
Out
IS11
IS10
IS20
IS25
IS40
IS21
IS26
IS45
2008-2011 Microchip Technology Inc. DS39927C-page 243
PIC24F16KA102 FAMILY
TABLE 29-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
FIGURE 29-13: START BIT EDGE DETECTION
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min Max Units Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 100 ns
IS21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)— 300 ns
IS25 T
SU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(1)100 — ns
IS26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
1 MHz mode(1)00.3s
IS40 T
AA:SCL Output Valid From
Clock
100 kHz mode 0 3500 ns
400 kHz mode 0 1000 ns
1 MHz mode(1)0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1)0.5 — s
IS50 CBBus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
BRGx
Cycle
Clock
UxRX
Any Value
T
STDELAY
TSETUP
TCY Start bit Detected, BRGx Started
PIC24F16KA102 FAMILY
DS39927C-page 244 2008-2011 Microchip Technology Inc.
FIGURE 29-14: INPUT CAPTURE TIMINGS
TABLE 29-33: INPUT CAPTURE
TABLE 29-34: OUTPUT CAPTURE
FIGURE 29-15: OUTPUT COMPARE TIMINGS
Param.
No. Symbol Characteristic Min Max Units Conditions
IC10 TccL ICx Input Low Time –
Synchronous Timer
No Prescaler TCY + 20 — ns Must also meet
Parameter IC15
With Prescaler 20 — ns
IC11 TccH ICx Input Low Time –
Synchronous Timer
No Prescaler TCY + 20 — ns Must also meet
Parameter IC15
With Prescaler 20 — ns
IC15 TccP ICx Input Period – Synchronous Timer 2 * TCY + 40
N
—nsN = prescale
value (1, 4, 16)
Param.
No. Symbol Characteristic Min Max Units Conditions
OC11 TCCR OC1 Output Rise Time — 10 ns
— —ns
OC10 TCCF OC1 Output Fall Time — 10 ns
—— ns
ICx pin
(Input Capture Mode)
IC10 IC11
IC15
OCx
OC11 OC10
(Output Compare or PWM Mode)
2008-2011 Microchip Technology Inc. DS39927C-page 245
PIC24F16KA102 FAMILY
FIGURE 29-16: PWM MODULE TIMING REQUIREM ENTS
TABLE 29-35: PWM TIMING REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ†Max Units Conditions
OC15 TFD Fault Input to PWM I/O
Change
— — 25 ns VDD = 3.0V, -40C to +125C
OC20 TFH Fault Input Pulse Width 50 — — ns VDD = 3.0V, -40C to +125C
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
OCFx
PWM
OC20
OC15
PIC24F16KA102 FAMILY
DS39927C-page 246 2008-2011 Microchip Technology Inc.
FIGURE 29-17: SPIx MODULE MAST ER MODE TIMING CHARACTERISTICS (CK E = 0)
TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0)
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
SP10 TscL SCKx Output Low Time(2)TCY/2 — — ns
SP11 TscH SCKx Output High Time(2)TCY/2 — — ns
SP20 TscF SCKx Output Fall Time(3) —1025ns
SP21 TscR SCKx Output Rise Time(3)—1025ns
SP30 TdoF SDOx Data Output Fall Time(3)—1025ns
SP31 TdoR SDOx Data Output Rise Time(3)—1025ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— — 30 ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20 — — ns
Note1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP11 SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
SP30
SP31
MSb In
2008-2011 Microchip Technology Inc. DS39927C-page 247
PIC24F16KA102 FAMILY
FIGURE 29-18: SPIx MODULE MAST ER MODE TIMING CHARACTERISTICS (CK E = 1)
TABLE 29- 37: SP Ix MO DULE MAS TER MO DE TIMING REQUIREMENTS (CKE = 1)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated )
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
SP10 TscL SCKx Output Low Time(2)TCY/2 — — ns
SP11 TscH SCKx Output High Time(2)TCY/2 — — ns
SP20 TscF SCKx Output Fall Time(3)—1025ns
SP21 TscR SCKx Output Rise Time(3)—1025ns
SP30 TdoF SDOx Data Output Fall Time(3)—1025ns
SP31 TdoR SDOx Data Output Rise Time(3)—1025ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
——30ns
SP36 TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20 — — ns
Note1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP36
SP30,SP31
SP35
MSb Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
LSb
SP11 SP10
SP21
SP20
SP41
MSb In
SP40
SP20
SP21
PIC24F16KA102 FAMILY
DS39927C-page 248 2008-2011 Microchip Technology Inc.
FIGURE 29-19: SPIx MODULE SLAVE MO DE TIMING CHARACTERISTICS (C KE = 0)
TABLE 29- 38: SPIx MO DULE SL AVE MO DE TIMING REQUIREMENTS (CKE = 0)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
SP70 TscL SCKx Input Low Time 30 — — ns
SP71 TscH SCKx Input High Time 30 — — ns
SP72 TscF SCKx Input Fall Time(2)—1025ns
SP73 TscR SCKx Input Rise Time(2)—1025ns
SP30 TdoF SDOx Data Output Fall Time(2)—1025ns
SP31 TdoR SDOx Data Output Rise Time(2)—1025ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— — 30 ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20 — — ns
SP41 TscH2diL,
Ts c L 2 di L
Hold Time of SDIx Data Input
to SCKx Edge
20 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output High-Impedance(3)10 — 50 ns
SP52 TscH2ssH
Ts c L 2 ss H
SSx after SCKx Edge 1.5 TCY + 40 — — ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are
not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate
this specification.
3: Assumes 50 pF load on all SPIx pins.
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDI
SP50
SP40
SP41
SP30,SP31 SP51
SP35
SDIx
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP71 SP70
MSb In
2008-2011 Microchip Technology Inc. DS39927C-page 249
PIC24F16KA102 FAMILY
FIGURE 29-20: SPIx MODULE SLAVE MO DE TIMING CHARACTERISTICS (C KE = 1)
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SP60
SDIx
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
Bit 14 - - - -1 LSb In
SP35
SP52
SP52
SP73
SP72
SP72
SP73
SP71 SP70
SP40
SP41
SP50
MSb In
TABLE 29- 39: SP Ix MO DULE SL AV E MODE TIMING REQUIREMENTS (CKE = 1)
AC CHARACTERISTICS
Standard Oper ating Condit ions: 2.0V t o 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1)Max Units Conditions
SP70 TscL SCKx Input Low Time 30 — — ns
SP71 TscH SCKx Input High Time 30 — — ns
SP72 TscF SCKx Input Fall Time(2)—1025ns
SP73 TscR SCKx Input Rise Time(2)—1025ns
SP30 TdoF SDOx Data Output Fall Time(2)—1025ns
SP31 TdoR SDOx Data Output Rise Time(2)—1025ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after SCKx Edge — — 30 ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input to
SCKx Edge
20 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input to
SCKx Edge
20 — — ns
SP50 TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input 120 — — ns
SP51 TssH2doZ SSx to SDOx Output High-Impedance(3)10 — 50 ns
SP52 TscH2ssH
TscL2ssH
SSx after SCKx Edge 1.5 TCY + 40 — — ns
SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not
tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this
specification.
3: Assumes 50 pF load on all SPIx pins.
PIC24F16KA102 FAMILY
DS39927C-page 250 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 251
PIC24F16KA102 FAMILY
30.0 PACKAGING INFORMATION
30.1 Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC24F16KA102
1110017
3
e
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC24F08KA
102-I/SS
1110017
3
e
20-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC24F16KA
101-I/SS
1110017
3
e
-I/SP
Legend: XX...X Product-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
-I/P
PIC24F16KA101
1110017
3
e
PIC24F16KA102 FAMILY
DS39927C-page 252 2008-2011 Microchip Technology Inc.
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
24F16KA
102-I/ML
1110017
3
e
28-Lead SOIC (.300”)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
20-Lead SOIC (.300”)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
Example
PIC24F16KA101
-I/SO
1110017
3
e
20-Lead QFN Example
3
e
XXXXXX
XXXXXX
YYWWNNN
XXXXXX
PIC24F
16KA101
1110017
-I/MQ
PIC24F16KA102
-I/SO
1110017
3
e
2008-2011 Microchip Technology Inc. DS39927C-page 253
PIC24F16KA102 FAMILY
30.2 Package Details
The following sections give the technical details of the packages.
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2008-2011 Microchip Technology Inc. DS39927C-page 255
PIC24F16KA102 FAMILY
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PIC24F16KA102 FAMILY
DS39927C-page 256 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 257
PIC24F16KA102 FAMILY
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DS39927C-page 258 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 259
PIC24F16KA102 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC24F16KA102 FAMILY
DS39927C-page 260 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 261
PIC24F16KA102 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC24F16KA102 FAMILY
DS39927C-page 262 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 263
PIC24F16KA102 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC24F16KA102 FAMILY
DS39927C-page 264 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 265
PIC24F16KA102 FAMILY
20-Lead Plastic Quad Flat, No Lead Package (MQ)  5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-120A
PIC24F16KA102 FAMILY
DS39927C-page 266 2008-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2011 Microchip Technology Inc. DS39927C-page 267
PIC24F16KA102 FAMILY
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DEXPOSED D2
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TOP VIEW BOTTOM VIEW
PAD
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DS39927C-page 268 2008-2011 Microchip Technology Inc.
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2008-2011 Microchip Technology Inc. DS39927C-page 269
PIC24F16KA102 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (November 2008)
Original data sheet for the PIC24F16KA102 family of
devices.
Revision B (March 2009)
Section 29.0 “Electrical Characteristics” was
revised and minor text edits were made throughout the
document.
Revision C (October 2011)
• Changed all instances of DSWSRC to DSWAKE.
• Corrected Example 5-2.
• Corrected Example 5-4.
• Corrected Example 6-1.
• Corrected Example 6-3.
• Added a comment to Example 6-5.
• Corrected Figure 9-1 to connect the SOSCI and
SOSCO pins to the Schmitt trigger correctly.
• Added register descriptions for PMD1, PMD2,
PMD3 and PMD4.
• Added note that RTCC will run in Reset.
• Corrected time values of ADCS
(AD1CON3<5:0>).
• Corrected CH0SB and CH0SA (AD1CHS<11:8>
and AD1CHS<3:0>) to correctly reference AVDD
and AN3.
• Added description of PGCF15 and PGCF14
(AD1PCFG<15:14>).
•Edited Figure 22-2 to correctly reference RIC and
the A/D capacitance.
• Changed all references from CTEDG1 to CTED1.
• Changed all references from CTEDG2 to CTED2.
• Changed description of CMIDL: it used to say it
disables all comparators in Idle, now only disables
interrupts in Idle mode.
• Changed all references of RTCCKSEL to
RTCOSC.
• Changed all references of DSLPBOR to
DSBOREN.
• Changed all references of DSWCKSEL to
DSWDTOSC
• Imported Figure 40-9 from PIC24F FRM,
Section 40.
• Added spec for BOR hysteresis.
• Edited Note 1 for Table 29-5 to further describe
LPBOR.
• Edited max values of DC20d and DC20e on
Table 29-6.
• Edited typical value for DC61-DC61c in
Table 29-8.
• Edited Note 2 of Ta b l e 2 9 - 8 .
• Added Note 5 to Table 29-9.
• Added Table 29-15.
• Added AD08 and AD09 in Table 29-26.
• Added Note 3 to Table 29-26.
• Imported Figure 40.10 from PIC24F FRM,
Section 40.
• Deleted TVREG spec.
• Imported Figure 15-5 from PIC24F FRM,
Section 15.
• Imported Table 15-4 from PIC24F FRM,
Section 15.
• Imported Figure 16-22 from PIC24F FRM,
Section 16.
• Imported Table 16-9 from PIC24F FRM,
Section 16.
• Imported Figure 16-23 from PIC24F FRM,
Section 16.
• Imported Table 16-10 from PIC24F FRM,
Section 16.
• Imported Figure 21-24 from PIC24F FRM.
Section 21.
• Imported Figure 21-25 from PIC24F FRM,
Section 21.
• Imported Table 21-5 from PIC24F FRM,
Section 21.
• Imported Figure 23-17 from PIC24F FRM,
Section 23.
• Imported Table 23-3 from PIC24F FRM,
Section 23.
• Imported Figure 23-18 from PIC24F FRM,
Section 23.
• Imported Table 23-4 from PIC24F FRM,
Section 23.
• Imported Figure 23-19 from PIC24F FRM,
Section 23.
• Imported Table 23-5 from PIC24F FRM,
Section 23.
• Imported Figure 23-20 from PIC24F FRM,
Section 23.
• Imported Table 23-6 from PIC24F FRM,
Section 23.
• Imported Figure 24-33 from PIC24F FRM,
Section 24.
• Imported Table 24-6 from PIC24F FRM,
Section 24.
• Imported Figure 24-34 from PIC24F FRM,
Section 24.
• Imported Table 24-7 from PIC24F FRM,
Section 24.
• Imported Figure 24-35 from PIC24F FRM,
Section 24.
• Imported Table 24-8 from PIC24F FRM,
Section 24.
• Imported Figure 24-36 from PIC24F FRM,
Section 24.
• Imported Table 24-9 from PIC24F FRM,
Section 24.
PIC24F16KA102 FAMILY
DS39927C-page 270 2008-2011 Microchip Technology Inc.
NOTES:
2008-2011 Microchip Technology Inc. DS39927C-page 271
PIC24F16KA102 FAMILY
INDEX
A
A/D
10-Bit High-Speed A/D Converter ............................ 173
A/D Characteristics
Conversion Timing Requirements ............................ 234
Module Specifications .............................................. 235
A/D Converter
Analog Input Model .................................................. 181
Transfer Function ..................................................... 182
AC Characteristics
Capacitive Loading Requirements on
Output Pins ...................................................... 231
Comparator Timings ................................................ 237
Comparator Voltage Reference Settling
Time Specifications .......................................... 237
Input Capture ........................................................... 244
Internal RC Accuracy ............................................... 233
Load Conditions for Device Timing
Specifications ................................................... 231
Output Capture ........................................................ 244
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Timing Requirements ....................................... 239
Specifications ........................................................... 234
Assembler
MPASM Assembler .................................................. 204
B
Baud Rate Generator
Setting as a Bus Master ........................................... 141
Block Diagrams
10-Bit High-Speed A/D Converter ............................ 174
16-Bit Timer1 ........................................................... 115
Accessing Program Memory with
Table Instructions .............................................. 43
CALL Stack Frame ..................................................... 41
Comparator Module ................................................. 183
Comparator Voltage Reference ............................... 187
CPU Programmer’s Model ......................................... 25
CRC Reconfigured for Polynomial ........................... 168
CRC Shifter Details .................................................. 167
CTMU Connections and Internal Configuration for
Capacitance Measurement .............................. 189
CTMU Typical Connections and Internal
Configuration for Pulse Delay Generation ....... 190
CTMU Typical Connections and Internal
Configuration for Time Measurement .............. 190
Data Access from Program Space
Address Generation ........................................... 42
Data EEPROM Addressing with TBLPAG,
NVM Address Registers .................................... 53
High/Low-Voltage Detect (HLVD) ............................ 171
I2C Module ............................................................... 140
Individual Comparator Configurations ...................... 184
Input Capture ........................................................... 123
Output Compare ...................................................... 128
PIC24F CPU Core ..................................................... 24
PIC24F16KA102 Family (General) ............................ 12
PSV Operation ........................................................... 44
Reset System ............................................................ 57
RTCC ....................................................................... 155
Shared I/O Port Structure ........................................ 113
Simplified UART ...................................................... 147
SPI1 Module (Enhanced Buffer Mode) .................... 133
SPI1 Module (Standard Buffer Mode) ..................... 132
System Clock ............................................................. 91
Timer2 (16-Bit Synchronous Mode) ......................... 119
Timer2/3 (32-Bit Mode) ............................................ 118
Timer3 (16-Bit Synchronous Mode) ......................... 119
Watchdog Timer (WDT) ........................................... 201
Brown-out Reset (BOR) ..................................................... 61
C
C Compilers
MPLAB C18 ............................................................. 204
Charge Time Measurement Unit. See CTMU.
Code Examples
Data EEPROM Bulk Erase ........................................ 55
Data EEPROM Unlock Sequence ............................. 51
Erasing a Program Memory Row,
‘C’ Language Code ............................................ 48
Erasing a Program Memory Row,
Assembly Language Code ................................ 48
I/O Port Write/Read ................................................. 114
Initiating a Programming Sequence,
‘C’ Language Code ............................................ 50
Initiating a Programming Sequence,
Assembly Language Code ................................ 50
Loading the Write Buffers, ‘C’ Language Code ......... 49
Loading the Write Buffers, Assembly
Language Code ................................................. 49
PWRSAV Instruction Syntax ................................... 101
Reading Data EEPROM Using the
TBLRD Command ............................................. 56
Sequence for Clock Switching ................................... 98
Setting the RTCWREN Bit ....................................... 156
Single-Word Erase .................................................... 54
Single-Word Write to Data EEPROM ........................ 55
Code Protection ............................................................... 202
Comparator ...................................................................... 183
Comparator Voltage Reference ....................................... 187
Configuration ........................................................... 187
Configuration Bits ............................................................ 193
Core Features ...................................................................... 9
CPU
Arithmetic (Logic Unit (ALU) ...................................... 27
Control Registers ....................................................... 26
Core Registers ........................................................... 24
Programmer’s Model ................................................. 23
CRC
Operation in Power Save Modes ............................. 168
User Interface .......................................................... 168
CTMU
Measuring Capacitance ........................................... 189
Measuring Time ....................................................... 190
Pulse Generation and Delay .................................... 190
Customer Change Notification Service ............................ 275
Customer Notification Service ......................................... 275
Customer Support ............................................................ 275
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D
Data EEPROM
Bulk Erase ..................................................................55
Erasing ....................................................................... 54
Operations ................................................................. 53
Programming
Reading Data EEPROM .................................... 56
Single-Word Write .............................................. 55
Data Memory
Address Space ........................................................... 31
Memory Map ..............................................................31
Near Data Space .......................................................32
Organization, Alignment ............................................. 32
SFR Space ................................................................. 32
Software Stack ...........................................................41
Space Width ...............................................................31
DC Characteristics
Brown-out Reset Trip Points .................................... 219
Comparator Specifications .......................................230
Comparator Voltage Reference Specifications ........ 230
CTMU Current Source Specifications ...................... 230
Data EEPROM Memory ...........................................229
High/Low-Voltage Detect .........................................218
I/O Pin Input Specifications ...................................... 227
I/O Pin Output Specifications ................................... 228
Idle Current IIDLE ......................................................222
Internal Voltage References .................................... 230
Operating Current IDD .............................................. 220
Power-Down Current IPD .........................................224
Program Memory .....................................................229
Temperature and Voltage Specifications ................. 218
Thermal Operating Conditions ................................. 217
Thermal Packaging Characteristics .........................217
Deep Sleep
Checking, Clearing Status ....................................... 104
Entering .................................................................... 102
Sequence ................................................. 102, 103
Exiting ...................................................................... 103
I/O Pins ....................................................................103
POR ......................................................................... 104
Sequence Summary ................................................ 104
WDT .........................................................................104
Deep Sleep BOR (DSBOR) ............................................... 61
Development Support ...................................................... 203
Device Features (Summary) .............................................. 11
Doze Mode ....................................................................... 107
E
Electrical Characteristics
Absolute Maximum Ratings ..................................... 215
V/F Graphs (Industrial, Extended) ........................... 216
V/F Graphs (Industrial) ............................................. 216
Equations
A/D Conversion Clock Period .................................. 181
Baud Rate Reload Calculation ................................. 141
Calculating the PWM Period .................................... 126
Calculation for Maximum PWM Resolution .............. 126
CRC ......................................................................... 167
Device and SPI Clock Speed Relationship .............. 138
UART Baud Rate with BRGH = 0 ............................148
UART Baud Rate with BRGH = 1 ............................148
Errata ................................................................................... 8
Examples
Baud Rate Error Calculation (BRG) ......................... 148
PWM Frequencies, Resolutions at 16 MIPS ............ 127
PWM Frequencies, Resolutions at 4 MIPS .............. 127
PWM Period, Duty Cycle Calculations ..................... 127
F
Flash and Data EEPROM
Programming
Control Registers ............................................... 51
Flash and Data EEPROM Programming
Control Registers
NVM Address Registers (NVMADRU,
NVMADR ................................................... 53
NVMCON ........................................................... 51
NVMKEY ........................................................... 51
Flash Program Memory
Control Registers ....................................................... 46
Enhanced ICSP Operation ........................................ 46
Programming Algorithm ............................................. 48
Programming Operations ........................................... 46
RTSP Operation ........................................................ 46
Table Instructions ...................................................... 45
H
High/Low-Voltage Detect (HLVD) .................................... 171
I
I/O Ports
Analog Pins Configuration ....................................... 114
Input Change Notification ........................................ 114
Open-Drain Configuration ........................................ 114
Parallel (PIO) ........................................................... 113
I2C
Clock Rates ............................................................. 141
Communicating as Master in Single Master
Environment .................................................... 139
Pin Remapping Options ........................................... 139
Reserved Addresses ............................................... 141
Slave Address Masking ........................................... 141
In-Circuit Debugger .......................................................... 202
In-Circuit Serial Programming (ICSP) .............................. 202
Input Capture ................................................................... 123
Instruction Set
Opcode Symbols ..................................................... 208
Overview .................................................................. 209
Summary ................................................................. 207
Inter-Integrated Circuit. See I2C.
Internet Address .............................................................. 275
Interrupts
Alternate Interrupt Vector Table (AIVT) ..................... 63
Control and Status Registers ..................................... 66
Implemented Vectors ................................................. 65
Interrupt Service Routine (ISR) .................................. 90
Interrupt Vector Table (IVT) ....................................... 63
Reset Sequence ........................................................ 63
Setup and Service Procedures .................................. 90
Trap Service Routine (TSR) ...................................... 90
Trap Vectors .............................................................. 65
Vector Table .............................................................. 64
2008-2011 Microchip Technology Inc. DS39927C-page 273
PIC24F16KA102 FAMILY
M
Microchip Internet Web Site ............................................. 275
MPLAB ASM30 Assembler, Linker, Librarian .................. 204
MPLAB Integrated Development
Environment Software .............................................. 203
MPLAB PM3 Device Programmer ................................... 206
MPLAB REAL ICE In-Circuit Emulator System ................ 205
MPLINK Object Linker/MPLIB Object Librarian ............... 204
N
Near Data Space ............................................................... 32
O
Oscillator Configuration
Bit Values for Clock Selection .................................... 92
Clock Switching .......................................................... 97
Sequence ........................................................... 97
CPU Clocking Scheme .............................................. 92
Initial Configuration on POR ...................................... 92
Reference Clock Output ............................................. 98
Output Compare
Continuous Output Pulse Generation ...................... 125
Single Output Pulse Generation .............................. 125
P
Packaging
Details ...................................................................... 253
Marking .................................................................... 251
Pinout Descriptions ...................................................... 13–16
Power-Saving Features ................................................... 101
Clock Frequency, Clock Switching ........................... 101
Instruction-Based Modes ......................................... 101
Deep Sleep ...................................................... 102
Idle ................................................................... 102
Sleep ................................................................ 101
Product Identification System .......................................... 277
Program and Data Memory
Access Using Table Instructions ................................ 43
Program Space Visibility ............................................ 44
Program and Data Memory Spaces
Interfacing, Addressing .............................................. 41
Program Memory
Address Space ........................................................... 29
Configuration Word Addresses .................................. 30
Memory Map .............................................................. 29
Program Verification ........................................................ 202
Programmable Cyclic Redundancy Check (CRC)
Generator ................................................................. 167
Pulse-Width Modulation. See PWM.
R
Reader Response ............................................................ 276
Register Maps
A/D ............................................................................. 38
Clock Control ............................................................. 40
CPU Core ................................................................... 33
CRC ........................................................................... 39
CTMU ......................................................................... 38
Deep Sleep ................................................................ 40
Dual Comparator ........................................................ 39
I2C .............................................................................. 36
ICN ............................................................................. 34
Input Capture ............................................................. 35
Interrupt Controller ..................................................... 34
NVM ........................................................................... 40
Output Compare ........................................................ 35
Pad Configuration ...................................................... 37
PMD ........................................................................... 40
PORTA ...................................................................... 37
PORTB ...................................................................... 37
RTCC ......................................................................... 39
SPI ............................................................................. 36
Timer ......................................................................... 35
UART ......................................................................... 36
Registers
AD1CHS (A/D Input Select) ..................................... 178
AD1CON1 (A/D Control 1) ....................................... 175
AD1CON2 (A/D Control 2) ....................................... 176
AD1CON3 (A/D Control 3) ....................................... 177
AD1CSSL (A/D Input Scan Select, Low) ................. 180
AD1PCFG (A/D Port Configuration) ........................ 179
ALCFGRPT (Alarm Configuration) .......................... 159
ALMINSEC (Alarm Minutes and
Seconds Value) ............................................... 163
ALMTHDY (Alarm Month and Day Value) ............... 162
ALWDHR (Alarm Weekday and Hours Value) ........ 162
CLKDIV (Clock Divider) ............................................. 95
CMSTAT (Comparator Status) ................................ 186
CMxCON (Comparator x Control) ........................... 185
CORCON (CPU Control) ..................................... 27, 68
CRCCON (CRC Control) ......................................... 169
CRCXOR (CRC XOR Polynomial) .......................... 170
CTMUCON (CTMU Control) .................................... 191
CTMUICON (CTMU Current Control) ...................... 192
CVRCON (Comparator Voltage
Reference Control) .......................................... 188
DEVID (Device ID) ................................................... 200
DEVREV (Device Revision) ..................................... 200
DSCON (Deep Sleep Control) ................................. 105
DSWAKE (Deep Sleep Wake-up Source) ............... 106
FBS (Boot Segment Configuration) ......................... 193
FDS (Deep Sleep Configuration) ............................. 199
FGS (General Segment Configuration) ................... 194
FICD (In-Circuit Debugger Configuration) ............... 198
FOSC (Oscillator Configuration) .............................. 195
FOSCSEL (Oscillator Selection Configuration) ....... 194
FPOR (Reset Configuration) ................................... 197
FWDT (Watchdog Timer Configuration) .................. 196
HLVDCON (High/Low-Voltage Detect Control) ....... 172
I2C1CON (I2C1 Control) ......................................... 142
I2C1MSK (I2C1 Slave Mode Address Mask) .......... 146
I2C1STAT (I2C1 Status) .......................................... 144
IC1CON (Input Capture 1 Control) .......................... 124
IEC0 (Interrupt Enable Control 0) .............................. 75
IEC1 (Interrupt Enable Control 1) .............................. 76
IEC3 (Interrupt Enable Control 3) .............................. 77
IEC4 (Interrupt Enable Control 4) .............................. 78
IFS0 (Interrupt Flag Status 0) .................................... 71
IFS1 (Interrupt Flag Status 1) .................................... 72
IFS3 (Interrupt Flag Status 3) .................................... 73
IFS4 (Interrupt Flag Status 4) .................................... 74
INTCON1 (Interrupt Control 1) .................................. 69
INTCON2 (Interrupt Control 2) .................................. 70
INTTREG Interrupt Control and Status ...................... 89
IPC0 (Interrupt Priority Control 0) .............................. 79
IPC1 (Interrupt Priority Control 1) .............................. 80
IPC15 (Interrupt Priority Control 15) .......................... 86
IPC16 (Interrupt Priority Control 16) .......................... 87
IPC18 (Interrupt Priority Control 18) .......................... 88
IPC19 (Interrupt Priority Control 19) .......................... 88
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DS39927C-page 274 2008-2011 Microchip Technology Inc.
IPC2 (Interrupt Priority Control 2) .............................. 81
IPC3 (Interrupt Priority Control 3) .............................. 82
IPC4 (Interrupt Priority Control 4) .............................. 83
IPC5 (Interrupt Priority Control 5) .............................. 84
IPC7 (Interrupt Priority Control 7) .............................. 85
MINSEC (RTCC Minutes and Seconds Value) ........ 161
MTHDY (RTCC Month and Day Value) ................... 160
NVMCON (Flash Memory Control) ............................47
NVMCON (Nonvolatile Memory Control) ...................52
OC1CON (Output Compare 1 Control) .................... 129
OSCCON (Oscillator Control) .................................... 93
OSCTUN (FRC Oscillator Tune) ................................96
PADCFG1 (Pad
Configuration Control) ...................... 130, 146, 158
PMD1 (Peripheral Module Disable 1) ...................... 108
PMD2 (Peripheral Module Disable 2) ...................... 109
PMD3 (Peripheral Module Disable 3) ...................... 110
PMD4 (Peripheral Module Disable 4) ...................... 111
RCFGCAL (RTCC Calibration and
Configuration) .................................................. 157
RCON (Reset Control) ............................................... 58
REFOCON (Reference Oscillator Control) ................. 99
SPI1CON1 (SPI1 Control 1) .................................... 136
SPI1CON2 (SPI1 Control 2) .................................... 137
SPI1STAT (SPI1 Status and Control) ...................... 134
SR (ALU STATUS) .............................................. 26, 67
T1CON (Timer1 Control) ..........................................116
T2CON (Timer2 Control) ..........................................120
T3CON (Timer3 Control) ..........................................121
UxMODE (UARTx Mode) ......................................... 150
UxRXREG (UARTx Receive) ................................... 154
UxSTA (UARTx Status and Control) ........................ 152
UxTXREG (UARTx Transmit) .................................. 154
WKDYHR (RTCC Weekday and Hours Value) ........ 161
YEAR (RTCC Year Value) ....................................... 160
Resets
Clock Source Selection .............................................. 60
Delay Times for Various Device Resets .................... 60
Device Times ............................................................. 60
RCON Flags Operation .............................................. 59
SFR States ................................................................. 61
Revision History ...............................................................269
RTCC ............................................................................... 155
Alarm Configuration .................................................164
Alarm Mask Settings (figure) .................................... 165
Calibration ................................................................ 164
Register Mapping ..................................................... 156
Source Clock ............................................................ 155
Selection .......................................................... 156
Write Lock ................................................................ 156
S
Selective Peripheral Power Control ................................. 107
Serial Peripheral Interface. See SPI.
SFR Space ......................................................................... 32
Software Simulator (MPLAB SIM) ....................................205
Software Stack ................................................................... 41
T
Timer1 .............................................................................. 115
Timer2/3 ........................................................................... 117
Timing Diagrams
Baud Rate Generator Output ........................... 239, 240
Brown-out Reset Characteristics ............................. 219
CLKO and I/O Timing .............................................. 236
External Clock .......................................................... 232
I2C Bus Data (Master Mode) ................................... 240
I2C Bus Data (Slave Mode) ..................................... 242
I2C Bus Start/Stop Bits (Master Mode) .................... 240
I2C Bus Start/Stop Bits (Slave Mode) ...................... 242
Input Capture ........................................................... 244
Output Compare ...................................................... 244
PWM Requirements ................................................. 245
Reset, Watchdog Timer. Oscillator Start-up
Timer, Power-up Timer Characteristics ........... 238
SPIx Master Mode (CKE = 0) .................................. 246
SPIx Master Mode (CKE = 1) .................................. 247
SPIx Slave Mode (CKE = 0) .................................... 248
SPIx Slave Mode (CKE = 1) .................................... 249
Start Bit Edge Detection .......................................... 243
Timing Requirements
CLKO and I/O .......................................................... 236
External Clock .......................................................... 232
I2C Bus Data (Master Mode) ........................... 240, 241
I2C Bus Data (Slave Mode) ..................................... 243
I2C Bus Start/Stop Bit (Slave Mode) ........................ 242
PLL Clock Specifications ......................................... 233
PWM ........................................................................ 245
SPIx Master Mode (CKE = 0) .................................. 246
SPIx Master Mode (CKE = 1) .................................. 247
SPIx Slave Mode (CKE = 0) .................................... 248
SPIx Slave Mode (CKE = 1) .................................... 249
U
UART ............................................................................... 147
Baud Rate Generator (BRG) ................................... 148
Break and Sync Transmit Sequence ....................... 149
IrDA Support ............................................................ 149
Operation of UxCTS and UxRTS Control Pins ........ 149
Receiving in 8-Bit or 9-Bit Data Mode ...................... 149
Transmitting in 8-Bit Data Mode .............................. 149
Transmitting in 9-Bit Data Mode .............................. 149
W
Watchdog Timer
Deep Sleep (DSWDT) ............................................. 202
Watchdog Timer (WDT) ................................................... 201
Windowed Operation ............................................... 201
WWW Address ................................................................ 275
WWW, On-Line Support ...................................................... 8
2008-2011 Microchip Technology Inc. DS39927C-page 275
PIC24F16KA102 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
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To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
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Customers should contact their distributor,
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Technical suppo rt is avail able throug h the we b site
at: http://microchip.com/support
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READER RESP ONSE
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DS39927CPIC24F16KA102 Family
1. What are the best features of this document?
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PIC24F16KA102 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture 24 = 16-bit modified Harvard without DSP
Flash Memory Family F = Flash program memory
Product Group KA1 = General purpose microcontrollers
Pin Count 01 = 20-pin
02 = 28-pin
Temperature Range I = -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package SP = SPDIP
SO = SOIC
SS = SSOP
ML = QFN
P=PDIP
Pattern Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES = Engineering Sample
Examples:
a) PIC24F16KA102-I/ML: General purpose,
16-Kbyte program memory, 28-pin, Industrial
temp., QFN package.
Microchip T rademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Coun t
Temperature Range
Package
Pattern
PIC 24 F 16 KA1 02 T - I / PT - XXX
Tape and Reel Flag (if applicable)
DS39927C-page 278 2008-2011 Microchip Technology Inc.
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