© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 10
1Publication Order Number:
NCP360/D
NCP360, NCV360
USB Positive Overvoltage
Protection Controller with
Internal PMOS FET and
Status FLAG
The NCP360 disconnects systems at its output when wrong VBUS
operating conditions are detected at its input. The system is positive
overvoltage protected up to +20 V.
Thanks to an integrated PMOS FET, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP360 is able to instantaneously disconnect the output from
the input if the input voltage exceeds the overvoltage threshold
(OVLO).
The NCP360 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1 mF or larger capacitor.
Features
•Very Fast Protection, Up to 20 V, with 25 mA Current Consumption
•On−chip PMOS Transistor
•Overvoltage Lockout (OVLO)
•Undervoltage Lockout (UVLO)
•Alert FLAG Output
•EN Enable Pin
•Thermal Shutdown
•Compliance to IEC61000−4−2 (Level 4)
8 kV (Contact)
15 kV (Air)
•ESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 2
•6 Lead UDFN 2x2 mm Package
•5 Lead TSOP 3x3 mm Package
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These are Pb−Free Devices
Applications
•USB Devices
•Mobile Phones
•Peripheral
•Personal Digital Applications
•MP3 Players
UDFN6
MU SUFFIX
CASE 517AB
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MARKING
DIAGRAMS
Q
xx M
G
1
1
5
1
xxxAYWG
G
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
TSOP−5
SN SUFFIX
CASE 483
M = Date Code
G= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 11 of this data sheet.
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PIN CONNECTIONS
IN
GND
FLAGEN
OUT
OUT
1
2
3
6
5
4
IN
GND
EN
OUT
FLAG
1
2
3
5
4
TSOP−5
UDFN6
PAD1
(Top Views)
PIN FUNCTION DESCRIPTION (UDFN6 Package)
Pin No. Name Type Description
1 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
2 GND POWER Ground
3 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
4, 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins.
The two OUT pins must be hardwired to common supply.
6 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
−PAD1 POWER Exposed Pad. Can be connected to GND or isolated plane. Must be used to thermal dissipation.
PIN FUNCTION DESCRIPTION (TSOP−5 Package)
Pin No. Name Type Description
1 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
2 GND POWER Ground
3 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
4 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin.
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Figure 1. Typical Application Circuit (UDFN Pinout)
INPUT
FLAG
R1
1M
C1
1 mF 25 V X5R 0603
OUTPUT
1
2J2
FLAG_State
FLAG Power
IN
GND
OUT
NCP360
FLAG
C2
OUT
34
5
61
2
EN
1 mF 25 V X5R 0603
Figure 2. Functional Block Diagram
INPUT
LDO VREF
UVLO
OVLO
Soft Start
OUTPUT
FLAGV
(2 out pins in
UDFN package)
Thermal Shutdown
EN
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MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage (IN to GND) Vminin −0.3 V
Minimum Voltage (All others to GND) Vmin −0.3 V
Maximum Voltage (IN to GND) Vmaxin 21 V
Maximum Voltage (All others to GND) Vmax 7.0 V
Maximum Current from Vin to Vout (PMOS) (Note 1) Imax 600 mA
Thermal Resistance, Junction−to−Air (Note 2) TSOP−5
UDFN
RqJA 305
260
°C/W
Operating Ambient Temperature Range TA−40 to +85 °C
Storage Temperature Range Tstg −65 to +150 °C
Junction Operating Temperature TJ150 °C
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2 (Note 3)
Machine Model (MM) Model = B (Note 4)
Vesd 15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity MSL Level 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. With minimum PCB area. By decreasing RqJA, the current capability increases. See PCB recommendation page 9.
2. RqJA is highly dependent on the PCB heat sink area (connected to PAD1, UDFN). See PCB Recommendations.
3. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
4. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
5. Compliant with JEDEC Latch−up Test, up to maximum voltage range.
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5
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic Symbol Conditions Min Typ Max Unit
Input Voltage Range Vin 1.2 20 V
Undervoltage Lockout Threshold UVLO Vin falls below UVLO threshold 2.85 3.0 3.15 V
Undervoltage Lockout
Hysteresis
UVLOhyst MU/SN, SNAE
SNAF, SNAI
50
30
70
50
90
70
mV
Overvoltage Lockout Threshold OVLO Vin rises above OVLO threshold MU/SN
SNAE
SNAF
SNAI
5.43
6.0
6.75
7.0
5.675
6.25
7.07
7.2
5.9
6.5
7.4
7.4
V
Overvoltage Lockout Hysteresis OVLOhyst 50 100 125 mV
Vin versus Vout Dopout Vdrop Vin = 5 V, I charge = 500 mA 105 200 mV
Supply Quiescent Current Idd No Load, Vin = 5.25 V 24 35 mA
OVLO Supply Current Iddovlo Vin = 7 V MU/SN, SNAE
Vin = 8 V SNAF, SNAI
50
50
85
85
mA
Output Off State Current Istd Vin = 5.25 V, EN = 1.2 V 26 37 mA
FLAG Output Low Voltage Volflag Vin > OVLO, Sink 1 mA on FLAG pin 400 mV
FLAG Leakage Current FLAGleak FLAG level = 5 V 5.0 nA
EN Voltage High Vih Vin from 3.3 V to 5.25 V 1.2 V
EN Voltage Low Vil Vin from 3.3 V to 5.25 V 0.4 V
EN Leakage Current ENleak EN = 5.5 V or GND 170 nA
TIMINGS
Start Up Delay ton From Vin: (0 to (OVLO − 300 mV) < Vin < OVLO)
to Vout = 0.8xVin, Rise time<4ms See Figures 3&9
4.0 15 ms
FLAG going up Delay tstart From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 10 3.0 ms
Output Turn Off Time toff From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11
Vin increasing from normal operation to >OVLO at
1V/ms. No output capacitor.
0.8 1.5 ms
Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 & 12
Vin increasing from normal operation to >OVLO at
1V/ms
1.0 2.0 ms
Disable Time tdis From EN 0.4 to 1.2V to Vout ≤ 0.3V, See Fig 5 & 13
Vin = 4.75 V. No output capacitor.
2.0 ms
Thermal Shutdown Temperature Tsd 150 °C
Thermal Shutdown Hysteresis Tsdhyst 30 °C
NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design.
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1.2 V
FLAG
Vout
Vin > 1.2V UVLO
tstart
0.8 Vin
ton
<OVLO
Vin − RDS(on) x I
Figure 3. Start Up Sequence Figure 4. Shutdown on Over Voltage Detection
Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1
1.2 V
FLAG
Vout
tdis
Vin − RDS(on) x I
EN
0.3 V
1.2 V
FLAG
Vin
EN
3 ms
UVLO
OVLO
FLAG
Vout
Vin
OVLO
toff
0.3 V
tstop 0.4 V
Vin − (RDS(on) I)
Voltage Detection
IN OUT VIN > OVLO or VIN < UVLO
CONDITIONS
Figure 7.
Voltage Detection
IN OUT UVLO < VIN < OVLO
CONDITIONS
Figure 8.
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TYPICAL OPERATING CHARACTERISTICS
Figure 9. Startup
Vin = Ch1, Vout = Ch3
Figure 10. FLAG Going Up Delay
Vin = Ch1, FLAG = Ch3
Figure 11. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 12. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 13. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
Figure 14. Thermal Shutdown
Vin = Ch1, Vout = Ch2, FLAG = Ch3
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TYPICAL OPERATING CHARACTERISTICS
Figure 15. Direct Output Short Circuit Figure 16. RDS(on) vs. Temperature
(Load = 500 mA)
Figure 17. Supply Quiescent Current vs. Vin
300
0−50 50 100 150
RDS(on) (mW)
TEMPERATURE (°C)
250
200
150
100
50
0
Vin = 3.6 V
450
Vin = 5 V
120
135791113
IQ, SUPPLY QUIESCENT CURRENT (mA)
Vin, INPUT VOLTAGE (V)
100
80
60
40
20
0
−40°C
140
350
400
160
180
15 17 19 21
125°C
25°C
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In Operation
NCP360 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the Vout pin, against positive
over−voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lock out (UVLO)
circuit. During Vin positive going slope, the output remains
disconnected from input until Vin voltage is above 3.2 V
nominal. The FLAGV output is pulled to low as long as Vin
does not reach UVLO threshold. This circuit has a UVLO
hysteresis to provide noise immunity to transient condition.
Figure 18. Output Characteristic vs. Vin
Vin (V)
20 V
OVLO
UVLO
0
Vout
OVLO
UVLO
0
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO −
Hysteresis.
FLAG output is tied to low until Vin is higher than
OVLO. This circuit has a OVLO hysteresis to provide noise
immunity to transient conditions.
FLAG Output
NCP360 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded When Vin level recovers normal condition,
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 MW− Minimum 10 kW) must
be provided to Vbattery. FLAG pin is an open drain output.
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
NCP360 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
RDSon, during normal operation, will create low losses on
Vout pin, characterized by Vin versus Vout dropout. (See
Figure 16).
ESD Tests
NCP360 fully support the IEC61000−4−2, level 4 (Input
pin, 1 mF mounted on board).
That means, in Air condition, Vin has a ±15 kV ESD
protected input. In Contact condition, Vin has ±8 kV ESD
protected input.
Please refer to Fig 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Figure 19.
PCB Recommendations
The NCP360 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
By increasing PCB area, the RqJA of the package can be
decreased, allowing higher charge current to fill the battery.
Taking into account that internal bondings (wires
between package and silicon) can handle up to 1 A (higher
than thermal capability), the following calculation shows
two different example of current capability, depending on
PCB area:
•With 305°C/W (without PCB area), allowing DC
current is 500 mA
•With 260°C/W (200 mm2), the charge DC current
allows with a 85°C ambient temperature is:
I = √(TJ-TA)/(RqJA x RDSON)
I = 625 mA
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10
In every case, we recommend to make thermal
measurement on final application board to make sure of the
final Thermal Resistance.
80
130
180
230
280
330
380
0 100 200 300 400 500 600 700
Copper heat spreader area (mm^2)
Theta JA (C/W)
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
% Delta DFN vs TSOP−5
TSOP−5 1.0 oz
TSOP−5 2.0 oz
DFN 2x2.2 1.0 oz
DFN 2x2.2 2.0 oz
% Delta DFN vs TSOP−5
Figure 20. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness
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11
ORDERING INFORMATION
Device Marking Package Shipping†
NCP360MUTBG ZD UDFN6
(Pb−Free)
3000 / Tape & Reel
NCP360MUTXG ZD UDFN6
(Pb−Free)
10000 / Tape & Reel
NCP360SNT1G SYA TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCP360SNAET1G AAP TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCP360SNAFT1G AA5 TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCP360SNAIT1G ACE TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCV360SNT1G* VUE TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCV360SNAET1G* VEY TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCV360SNAFT1G* VUM TSOP−5
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements
SELECTION GUIDE
The NCP360 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
a
NCP360xxxxTxG
bc d
Code Contents
a Package
MU = UDFN
SN = TSOP5
bUVLO Typical Threshold
b: − = 3.0 V
b: A = 3.0 V
cOVLO Typical Threshold
c: − = 5.675 V
c: E = 6.25 V
c: F = 7.07 V
c: I = 7.2 V
dTape & Reel Type (parts per reel)
d: 1 = 3000
d: B = 3000
d: X = 10000
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PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB
ISSUE B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.47
0.40
0.65
1.70
2.30
1
DIMENSIONS: MILLIMETERS
6X
0.95
PITCH
6X
ÍÍÍ
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
C
A
SEATING
PLANE
D
B
E
0.10 C
A3
A
A1
2X
2X 0.10 C
DIM
A
MIN MAX
MILLIMETERS
0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b0.25 0.35
D2.00 BSC
D2 1.50 1.70
0.80 1.00
E2.00 BSC
E2
e0.65 BSC
K
0.25 0.35
L
PIN ONE
REFERENCE
0.08 C
0.10 C
6X
A0.10 C
Le
E2
b
B
3
6
6X
1
K4
6X
6X
0.05 C
4X
D2
BOTTOM VIEW
0.20 ---
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13
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
DIM MIN MAX
MILLIMETERS
A3.00 BSC
B1.50 BSC
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
L1.25 1.55
M0 10
S2.50 3.00
123
54 S
A
G
L
B
D
H
C
J
__
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
T
SEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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NCP360/D
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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