33 × 17, 1.5 Gbps Digital
Crosspoint Switch
AD8150
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low cost
33 × 17, fully differential, nonblocking array
>1.5 Gbps per port NRZ data rate
Wide power supply range: +5 V, +3.3 V, −3.3 V, −5 V
Low power
400 mA (outputs enabled)
30 mA (outputs disabled)
PECL and ECL compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter: <50 ps p-p
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and building
Larger arrays
Double row latch
Buffered inputs
Available in 184-lead LQFP
APPLICATIONS
HD and SD digital video
Fiber optic network switching
GENERAL DESCRIPTION
AD8150 is a member of the Xstream line of products and is a
breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W.
Additionally, it operates at data rates in excess of 1.5 Gbps per
port, making it suitable for HDTV applications. Further, the
pricing of the AD8150 makes it affordable enough to be used
for SD applications. The AD8150 is also useful for OC-24
optical network switching.
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is
CMOS/TTL compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings. The
AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
FUNCTIONAL BLOCK DIAGRAM
OUTP
OUTN
INP INN
CS
RE
WE
D
A
UPDATE
RESET
FIRST
RANK
17
7-BIT
LATCH
SECOND
RANK
17
7-BIT
LATCH
INPUT
DECODERS
OUTPUT
ADDRESS
DECODER
33 17
DIFFERENTIAL
SWITCH
MATRIX
17
17
33 33
7
5
AD8150
01074-001
Figure 1. Functional Block Diagram
100ps/DIV
500mV
–
500mV
100mV/
DIV
01074-002
Figure 2. Output Eye Pattern, 1.5 Gbps
AD8150
Rev. A | Page 2 of 44
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Maximum Power Dissipiation.................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 9
Test Circuit ...................................................................................... 13
Control Interface............................................................................. 14
Control Interface Truth Tables ................................................. 14
Control Interface Timing Diagrams ........................................ 15
Control Interface Programming Example .............................. 20
Control Interface Description................................................... 21
Control Pin Description ............................................................ 21
Control Interface Translators.................................................... 22
Circuit Description......................................................................... 23
High Speed Data Inputs (INxxP, INxxN)................................ 23
High Speed Data Outputs (OUTyyP, OUTyyN) .................... 23
Output Current Set Pin (REF).................................................. 24
Power Supplies............................................................................ 25
Power Dissipation....................................................................... 27
Heat Sinking................................................................................ 28
Applications..................................................................................... 29
AD8150 Input and Output Busing........................................... 29
Evaluation Board ............................................................................ 30
Configuration Programming.................................................... 30
Power Supplies............................................................................ 30
Software Installation .................................................................. 30
Software Operation.................................................................... 31
PCB Layout...................................................................................... 32
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
9/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Absolute Maximum Ratings......................................... 4
Changes to Maximum Power Dissipation Section....................... 4
Change to Figure 3 ........................................................................... 4
Changes to Figure 40...................................................................... 26
Updated Outline Dimensions....................................................... 42
Changes to Ordering Guide .......................................................... 42
Revision 0: Initial Version
AD8150
Rev. A | Page 3 of 44
SPECIFICATIONS
At 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 25), IOUT = 16 mA, unless otherwise noted.
Table 1
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ) 1.5 Gbps
Channel Jitter Data rate < 1.5 Gbps 50 ps p-p
RMS Channel Jitter VCC = 5 V 10 ps
Propagation Delay Input to output 650 ps
Propagation Delay Match 50 100 ps
Output Rise/Fall Time 20% to 80% 100 ps
INPUT CHARACTERISTICS
Input Voltage Swing Differential 200 1000 mV p-p
Input Voltage Range Common mode VCC − 2 VCC V
Input Bias Current 2 μA
Input Capacitance 2 pF
Input VIN High VCC − 1.2 VCC − 0.2 V
Input VIN Low VCC − 2.4 VCC − 1.4 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Differential (see Figure 25) 800 mV p-p
Output Voltage Range VCC − 1.8 VCC V
Output Current 5 25 mA
Output Capacitance 2 pF
POWER SUPPLY
Operating Range
PECL, VCC V
EE = 0 V 3.3 5 V
ECL, VEE V
CC = 0 V −5 −3.3 V
VDD 3 5 V
VSS 0 V
Quiescent Current
VDD 2 mA
VEE All outputs enabled, IOUT = 16 mA 400 mA
T
MIN to TMAX 450 mA
All outputs disabled 30 mA
THERMAL CHARACTERISTICS
Operating Temperature Range 0 85 °C
θJA 30 °C/W
LOGIC INPUT CHARACTERISTICS VDD = 3 V dc to 5 V dc
Input VIN High 1.9 VDD V
Input VIN Low 0 0.9 V
AD8150
Rev. A | Page 4 of 44
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VDD − VEE 10.5 V
Internal Power Dissipation1
AD8150 184-Lead Plastic LQFP (ST) 4.2 W
Differential Input Voltage VCC − VEE
Output Short-Circuit Duration Observe power
derating curves
Storage Temperature Range2 −65°C to +125°C
1 Specification is for device in free air (TA = 25°C):
184-lead plastic LQFP (ST): θJA = 30°C/W.
2 Maximum reflow temperatures are to JEDEC industry standard J-STD-020.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPIATION
The maximum power that can be safely dissipated by the
AD8150 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 125°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
125°C for an extended period can result in device failure.
While the AD8150 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (125°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
6
1
2
3
4
5
–10 9080706050403020100
01074-003
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
T
J
= 150°C
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8150
Rev. A | Page 5 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
IN20P
VEE VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEEA0
VEE
VCC
VEE
IN19N
IN19P
IN18N
IN18P
IN17N
IN17P
IN16N
IN16P
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
REF
IN15N
IN15P
IN14N
IN14P
IN13N
IN13P
VEE
VEE
VEE
VEE
VEE
VSS
VCC
VEE
VEE
VEE
VEE
VEEREF
VCC
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEEA16
VCC
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
OUT16N
OUT16P
IN12N
IN12P
IN11N
IN11P
IN10N
IN10P
IN09N
IN09P
IN08N
IN08P
IN07N
IN07P
IN06N
IN06P
IN05N
IN05P
IN04N
IN04P
IN03N
IN03P
IN02N
IN02P
IN01N
IN01P
IN00N
IN00P
OUT00P
OUT00N
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
INDICATOR
AD8150
184L LQFP
TOP VIEW
(Not to Scale)
OUT15N
OUT15P
OUT14N
OUT14P
OUT13N
OUT13P
OUT12N
OUT12P
OUT11N
OUT11P
OUT10N
OUT10P
OUT09N
OUT09P
OUT08N
OUT08P
OUT07N
OUT07P
OUT06N
OUT06P
OUT05N
OUT05P
OUT04N
OUT04P
OUT03N
OUT03P
OUT02N
OUT02P
OUT01N
OUT01P
VEE
VEEA15
VEEA14
VEEA13
VEEA12
VEEA11
VEEA10
VEEA9
VEEA8
VEEA7
VEEA6
VEEA5
VEEA4
VEEA3
VEEA2
VEEA1
01074-004
Figure 4. Pin Configuration
AD8150
Rev. A | Page 6 of 44
Table 3. Pin Function Descriptions
Pin No. Mnemonic Type Description
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99, 102,
105, 108, 111, 114, 117, 120, 123,
126, 129, 132, 135, 138, 139, 142,
145, 148, 172, 175, 178, 181, 184
VEE Power supply Most Negative PECL Supply (common with other points labeled VEE)
2 IN20P PECL High Speed Input
3 IN20N PECL High Speed Input Complement
5 IN21P PECL High Speed Input
6 IN21N PECL High Speed Input Complement
8 IN22P PECL High Speed Input
9 IN22N PECL High Speed Input Complement
11 IN23P PECL High Speed Input
12 IN23N PECL High Speed Input Complement
14 IN24P PECL High Speed Input
15 IN24N PECL High Speed Input Complement
17 IN25P PECL High Speed Input
18 IN25N PECL High Speed Input Complement
20 IN26P PECL High Speed Input
21 IN26N PECL High Speed Input Complement
23 IN27P PECL High Speed Input
24 IN27N PECL High Speed Input Complement
26 IN28P PECL High Speed Input
27 IN28N PECL High Speed Input Complement
29 IN29P PECL High Speed Input
30 IN29N PECL High Speed Input Complement
32 IN30P PECL High Speed Input
33 IN30N PECL High Speed Input Complement
35 IN31P PECL High Speed Input
36 IN31N PECL High Speed Input Complement
38 IN32P PECL High Speed Input
39 IN32N PECL High Speed Input Complement
41, 98, 149, 171 VCC Power supply Most Positive PECL Supply (common with other points labeled VCC)
43 OUT16N PECL High Speed Output Complement
44 OUT16P PECL High Speed Output
45 VEEA16 Power supply Most Negative PECL Supply (unique to this output)
48 OUT15N PECL High Speed Output Complement
49 OUT15P PECL High Speed Output
50 VEEA15 Power supply Most Negative PECL Supply (unique to this output)
51 OUT14N PECL High Speed Output Complement
52 OUT14P PECL High Speed Output
53 VEEA14 Power supply Most Negative PECL Supply (unique to this output)
54 OUT13N PECL High Speed Output Complement
55 OUT13P PECL High Speed Output
56 VEEA13 Power supply Most Negative PECL Supply (unique to this output)
57 OUT12N PECL High Speed Output Complement
58 OUT12P PECL High Speed Output
59 VEEA12 Power supply Most Negative PECL Supply (unique to this output)
60 OUT11N PECL High Speed Output Complement
61 OUT11P PECL High Speed Output
62 VEEA11 Power supply Most Negative PECL Supply (unique to this output)
63 OUT10N PECL High Speed Output Complement
64 OUT10P PECL High Speed Output
AD8150
Rev. A | Page 7 of 44
Pin No. Mnemonic Type Description
65 VEEA10 Power supply Most Negative PECL Supply (unique to this output)
66 OUT09N PECL High Speed Output Complement
67 OUT09P PECL High Speed Output
68 VEEA9 Power supply Most Negative PECL Supply (unique to this output)
69 OUT08N PECL High Speed Output Complement
70 OUT08P PECL High Speed Output
71 VEEA8 Power supply Most Negative PECL Supply (unique to this output)
72 OUT07N PECL High Speed Output Complement
73 OUT07P PECL High Speed Output
74 VEEA7 Power supply Most Negative PECL Supply (unique to this output)
75 OUT06N PECL High Speed Output Complement
76 OUT06P PECL High Speed Output
77 VEEA6 Power supply Most Negative PECL Supply (unique to this output)
78 OUT05N PECL High Speed Output Complement
79 OUT05P PECL High Speed Output
80 VEEA5 Power supply Most Negative PECL Supply (unique to this output)
81 OUT04N PECL High Speed Output Complement
82 OUT04P PECL High Speed Output
83 VEEA4 Power supply Most Negative PECL Supply (unique to this output)
84 OUT03N PECL High Speed Output Complement
85 OUT03P PECL High Speed Output
86 VEEA3 Power supply Most Negative PECL Supply (unique to this output)
87 OUT02N PECL High Speed Output Complement
88 OUT02P PECL High Speed Output
89 VEEA2 Power supply Most Negative PECL Supply (unique to this output)
90 OUT01N PECL High Speed Output Complement
91 OUT01P PECL High Speed Output
94 VEEA1 Power supply Most Negative PECL Supply (unique to this output)
95 OUT00N PECL High Speed Output Complement
96 OUT00P PECL High Speed Output
97 VEEA0 Power supply Most Negative PECL Supply (unique to this output)
100 IN00P PECL High Speed Input
101 IN00N PECL High Speed Input Complement
103 IN01P PECL High Speed Input
104 IN01N PECL High Speed Input Complement
106 IN02P PECL High Speed Input
107 IN02N PECL High Speed Input Complement
109 IN03P PECL High Speed Input
110 IN03N PECL High Speed Input Complement
112 IN04P PECL High Speed Input
113 IN04N PECL High Speed Input Complement
115 IN05P PECL High Speed Input
116 IN05N PECL High Speed Input Complement
118 IN06P PECL High Speed Input
119 IN06N PECL High Speed Input Complement
121 IN07P PECL High Speed Input
122 IN07N PECL High Speed Input Complement
124 IN08P PECL High Speed Input
125 IN08N PECL High Speed Input Complement
127 IN09P PECL High Speed Input
128 IN09N PECL High Speed Input Complement
130 IN10P PECL High Speed Input
AD8150
Rev. A | Page 8 of 44
Pin No. Mnemonic Type Description
131 IN10N PECL High Speed Input Complement
133 IN11P PECL High Speed Input
134 IN11N PECL High Speed Input Complement
136 IN12P PECL High Speed Input
137 IN12N PECL High Speed Input Complement
140 IN13P PECL High Speed Input
141 IN13N PECL High Speed Input Complement
143 IN14P PECL High Speed Input
144 IN14N PECL High Speed Input Complement
146 IN15P PECL High Speed Input
147 IN15N PECL High Speed Input Complement
150 VEEREF R-program
Connection Point for Output Logic Pull-Down Programming Resistor
(must be connected to VEE)
151 REF R-program Connection Point for Output Logic Pull-Down Programming Resistor
152 VSS Power supply Most Negative Control Logic Supply
153 D6 TTL
Enable/DISABLE Output
154 D5 TTL (32) MSB Input Select
155 D4 TTL (16)
156 D3 TTL (8)
157 D2 TTL (4)
158 D1 TTL (2)
159 D0 TTL (1) LSB Input Select
160 A4 TTL (16) MSB Output Select
161 A3 TTL (8)
162 A2 TTL (4)
163 A1 TTL (2)
164 A0 TTL (1) LSB Output Select
165 UPDATE TTL Second-Rank Program
166 WE TTL First-Rank Program
167 RE TTL Enable Readback
168 CS TTL Enable Chip to Accept Programming
169 RESET TTL Disable All Outputs (Hi-Z)
170 VDD Power supply Most Positive Control Logic Supply
173 IN16P PECL High Speed Input
174 IN16N PECL High Speed Input Complement
176 IN17P PECL High Speed Input
177 IN17N PECL High Speed Input Complement
179 IN18P PECL High Speed Input
180 IN18N PECL High Speed Input Complement
182 IN19P PECL High Speed Input
183 IN19N PECL High Speed Input Complement
AD8150
Rev. A | Page 9 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
RMS
PK-PK
V
OH
(V)
JITTER (ps)
100
80
60
40
20
00 –0.2 –0.6 –0.8 –1.0 –1.2–0.4 –1.4
01074-005
V
EE
= –3.3V (V
OH
– V
OL
= 800mV)
Figure 5. Jitter vs. VOH 1.5 Gbps, PRBS 23
RMS
PK-PK
V
IN
(V)
JITTER (ps)
100
80
60
40
20
0
–2.0 –1.5 –0.5 0–1.0 0.5
01074-006
V
EE
= –3.3V (V
IH
– V
IL
= 800mV)
Figure 6. Jitter vs. VIH 1.5 Gbps, PRBS 23
RMS
PK-PK
DATA RATE (Gbps)
JITTER (ps)
100
80
60
40
20
00.1 1.51.31.10.90.70.50.3
01074-007
V
EE
= –3.3V
Figure 7. Jitter vs. Data Rate, PRBS 23
RMS
PK-PK
V
OH
(V)
JITTER (ps)
100
80
60
40
20
00 –0.2 –0.6 –0.8 –1.0 –1.2–0.4 –1.4
01074-008
V
EE
= –5V (V
OH
– V
OL
= 800mV)
Figure 8. Jitter vs. VOH 1.5 Gbps, PRBS 23
RMS
PK-PK
V
IN
(V)
JITTER (ps)
100
80
60
40
20
0
–2.0 –1.5 –0.5 0–1.0 0.5
01074-009
V
EE
= –5V (V
IH
– V
IL
= 800mV)
Figure 9. Jitter vs. VIH 1.5 Gbps, PRBS 23
RMS
PK-PK
DATA RATE (Gbps)
JITTER (ps)
100
80
60
40
20
00.1 1.51.31.10.90.70.50.3
01074-010
V
EE
= –5V
Figure 10. Jitter vs. Data Rate, PRBS 23
AD8150
Rev. A | Page 10 of 44
RMS
PK-PK
I
OUT
(mA)
JITTER (ps)
100
80
60
40
20
00 5 10 15 20 25
01074-011
V
EE
= –3.3V
Figure 11. Jitter vs. IOUT 1.5 Gbps, PRBS 23
RMS
PK-PK
TEMPERATURE (°C)
JITTER (ps)
100
80
60
40
20
0
–25 0 25 50 75 125100
01074-012
V
EE
= –3.3V
Figure 12. Jitter vs. Temperature 1.5 Gbps, PRBS 23
TIME DOMAIN
2
23
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) ×100 / DATA_PERIOD
TIME DOMAIN
V
INNER
100 / V
INNER
@500Mbps
VOLTAGE (INNER EYE)
VOLTAGE (INNER EYE)
DATA RATE (Mbps)
PERCENT
100
80
60
40
20
00 500 1000 1500
01074-013
V
EE
= –3.3V
Figure 13. AC Performance
RMS
PK-PK
I
OUT
(mA)
JITTER (ps)
100
80
60
40
20
00 5 10 15 20 25
01074-014
V
EE
= –5V
Figure 14. Jitter vs. IOUT 1.5 Gbps, PRBS 23
RMS
PK-PK
TEMPERATURE (°C)
JITTER (ps)
100
80
60
40
20
0
–25 0 25 50 75 125100
01074-015
V
EE
= –5V
Figure 15. Jitter vs. Temperature 1.5 Gbps, PRBS 23
TIME DOMAIN
2
23
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) ×100 / DATA_PERIOD
TIME DOMAIN
V
INNER
100 / V
INNER
@500Mbps
VOLTAGE (INNER EYE)
VOLTAGE (INNER EYE)
DATA RATE (Mbps)
PERCENT
100
80
60
40
20
00 500 1000 1500
01074-016
V
EE
= –5V
Figure 16. AC Performance
AD8150
Rev. A | Page 11 of 44
DELAY (ps)
FREQUENCY
100
80
60
40
20
0
560 580 620600 640 660 680 700 710
01074-017
Figure 17. Variation in Channel-to-Channel Delay, All 561 Points
VEE (V)
IOUT (mA)
17.0
16.5
16.0
15.5
15.0
14.5
–3.3 –3.6 –3.9 –4.2 –4.7 –5.0
01074-018
Figure 18. IOUT vs. Supply, VEE
200ps/DIV
200mV/DIV
1V
–1V
01074-019
95.55 RISE
96.32 FALL
20% PROXIMAL
80% DISTAL
Figure 19. Rise/Fall Times, VEE = −3.3 V
TEMPERATURE (
°
C)
PROPAGTION DELAY (ps)
150
100
50
0
–50
–100
–25 0 25 50 75 100
01074-020
Figure 20. Propagation Delay, Normalized at 25°C vs. Temperature
RMS
PK-PK
SUPPLY VOLTAGE (V
CC
, V
EE
)
JITTER (ps)
100
80
60
40
20
03.0 3.5 4.0 4.5 5.0
01074-021
Figure 21. Jitter vs. Supply 1.5 Gbps, PRBS 23
200ps/DIV
200mV/DIV
1V
–1V
01074-022
87.11 RISE
87.36 FALL
20% PROXIMAL
80% DISTAL
Figure 22. Rise/Fall Times, VEE = −5 V
AD8150
Rev. A | Page 12 of 44
200ps/DIV
100mV/DIV
500mV
–500mV
01074-023
Figure 23. Eye Pattern, VEE = −3.3 V, 1.5 Gbps PRBS 23
100ps/DIV
100mV/DIV
500mV
–500mV
01074-025
Figure 24. Eye Pattern, VEE = −5 V, 1.5 Gbps PRBS 23
AD8150
Rev. A | Page 13 of 44
TEST CIRCUIT
01074-024
1.65kΩR
L
= 50Ω
R
L
= 50Ω
50Ω
50Ω
V
CC
V
CC
V
TT
1.65kΩ
105Ω
HP8133A
PRBS
GENERATOR
TEKTRONIX
11801B
SD22
SAMPLING
HEAD
AD8150
IN OUT
P
N
P
N
V
EE
V
EE
V
TT
V
CC
= 0V, V
EE
= –3.3V OR –5V, V
TT
= –1.6V
R
SET
= 1.54kΩ, I
OUT
= 16mA, V
OH
= –0.8V, V
OL
= –1.8V
INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK
Figure 25. Eye Pattern Test Circuit
AD8150
Rev. A | Page 14 of 44
CONTROL INTERFACE
CONTROL INTERFACE TRUTH TABLES
The following are truth tables for the control interface.
Table 4. Basic Control Functions
Control Pins
RESET CS WE RE UPDATE Function
0 X X X X Global Reset. Reset all second-rank enable bits to 0 (disable all outputs).
1 1 X X X Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D[6:0] are high
impedance.
1 0 0 X X Single Output Preprogram. Write input configuration data from Data Bus D[6:0] into first rank of
latches for the output selected by the Output Address Bus A[4:0].
1 0 X 0 X Single Output Readback. Readback input configuration data from second rank of latches onto Data
Bus D[6:0] for the single output selected by the Output Address Bus A[4:0].
1 0 X X 0 Global Update. Copy input configuration data from all 17 first-rank latches into second rank of
latches, updating signal matrix connections for all outputs.
1 0 0 1 0 Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies logic
when synchronous signal matrix updating is not necessary.
Table 5. Address Data Examples
Output Address Pins
MSB to LSB
Enable
Bit
Input Address Pins
MSB to LSB
A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function
0 0 0 0 0 X 0 0 0 0 0 0 Lower Address/Data Range. Connect Output 00
(A[4:0] = 00000) to Input 00 (D[5:0] = 000000).
1 0 0 0 0 X 1 0 0 0 0 0 Upper Address/Data Range. Connect Output 16
(A[4:0] = 10000) to Input 32 (D[5:0] = 100000).
<Binary Output Number1> 1 <Binary Input Number> Enable Output. Connect selected output (A[4:0] = 0 to 16) to
designated input (D[5:0] = 0 to 32) and enable output
(D6 = 1).
<Binary Output Number1> 0 X X X X X X Disable Output. Disable specified output (D6 = 0).
1 0 0 0 1 X <Binary Input Number> Broadcast Connection. Connect all 17 outputs to the same
designated input and set all 17 enable bits to the value of
D6. Readback is not possible with the broadcast address.
1 0 0 1 0 X 1 0 0 0 0 1 Reserved. Any address or data code greater or equal to these
are reserved for future expansion or factory testing.
1 The binary output number may also be the broadcast connection designator, 10001X.
AD8150
Rev. A | Page 15 of 44
CONTROL INTERFACE TIMING DIAGRAMS
01074-026
A[4:0] INPUTS
t
CSW
t
ASW
t
WP
t
DSW
t
DHW
t
AHW
t
CHW
CS INPUT
WE INPUT
D[6:0] INPUTS
Figure 26. First-Rank Write Cycle
Table 6. First-Rank Write Cycle
Symbol Parameter Conditions Min Typ Max Unit
tCSW Setup Time Chip select to write enable TA = 25°C 0 ns
tASW Address to write enable VDD = 5 V 0 ns
tDSW Data to write enable VCC = 5 V 15 ns
tCHW Hold Time Chip select from write enable 0 ns
tAHW Address from write enable 0 ns
tDHW Data from write enable 0 ns
tWP Width of Write Enable Pulse 15 ns
AD8150
Rev. A | Page 16 of 44
01074-027
CS INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 2
DATA FROM RANK 1
UPDATE INPUT
t
CHU
t
UW
t
UOT
t
UOD
t
UOE
t
CSU
Figure 27. Second-Rank Update Cycle
Table 7. Second-Rank Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
tCSU Setup Time Chip select to update TA = 25°C 0 ns
tCHU Hold Time Chip select from update VDD = 5 V 0 ns
tUOE Output Enable Times Update to output enable VCC = 5 V 25 40 ns
tUOT Output Toggle Times Update to output reprogram 25 40 ns
tUOD Output Disable Times Update to output disabled 25 30 ns
tUW Width of Update Pulse 15 ns
AD8150
Rev. A | Page 17 of 44
01074-028
CS INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS INPUT {DATA 2}INPUT {DATA 1}
INPUT {DATA 1}INPUT {DATA 0}
DISABLING
OUT[0:16][N:P]
OUTPUTS
UPDATE INPUT
WE INPUT
t
CSU
t
UOT
t
WOT
t
WOD
t
WHU
t
CHU
t
UOE
t
UW
Figure 28. First-Rank Write Cycle and Second-Rank Update Cycle
Table 8. First-Rank Write Cycle and Second-Rank Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
tCSU Setup Time Chip select to update TA = 25°C 0 ns
tCHU Hold Time Chip select from update VDD = 5 V 0 ns
tUOE Output Enable Times Update to output enable VCC = 5 V 25 40 ns
tWOE1 Write enable to output enable 25 40 ns
tUOT Output Toggle Times Update to output reprogram 25 30 ns
tWOT Write enable to output reprogram 25 30 ns
tUOD1 Output Disable Times Update to output disabled 25 30 ns
tWOD Write enable to output disabled 25 30 ns
tWHU Setup Time Write enable to update 10 ns
tUW Width of Update Pulse 15 ns
1 Not shown.
AD8150
Rev. A | Page 18 of 44
01074-029
D[6:0]
OUTPUTS
ADDR 1 ADDR 2
DATA
{ADDR 1} DATA
{ADDR 2}
CS INPUT
RE INPUT
A[4:0]
INPUTS
t
CSR
t
RDE
t
AA
t
RHA
t
CHR
t
RDD
Figure 29. Second-Rank Readback Cycle
Table 9. Second-Rank Readback Cycle
Symbol Parameter Conditions Min Typ Max Unit
tCSR Setup Time Chip select to read enable TA = 25°C 0 ns
tCHR Hold Time Chip select from read enable VDD = 5 V 0 ns
tRHA Address from read enable VCC = 5 V 5 ns
tRDE Enable Time Data from read enable 10 kΩ 15 ns
tAA Access Time Data from address 20 pF on D[6:0] 15 ns
tRDD Release Time Data from read enable Bus 15 30 ns
AD8150
Rev. A | Page 19 of 44
01074-030
RESET INPUT
DISABLING
OUT[0:16][N:P]
OUTPUTS
t
TOD
t
TW
Figure 30, Asynchronous Reset
Table 10. Asynchronous Reset
Symbol Parameter Conditions Min Typ Max Unit
tTOD Disable Time Output disable from reset TA = 25°C 25 30 ns
tTW Width of Reset Pulse VDD = 5 V 15 ns
V
CC = 5 V
AD8150
Rev. A | Page 20 of 44
CONTROL INTERFACE PROGRAMMING EXAMPLE
The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period, T0, is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.
Table 11. Basic Test Pattern
Vector No. RESET CS WE RE UPDATE A[4:0] D[6:0] Comments
0 0 1 1 1 1 xxxxx xxxxxxx Disable all outputs
1 1 1 1 1 1 xxxxx xxxxxxx
2 1 0 1 1 1 10001 1000111 All outputs to Input 07
3 1 0 0 1 1 10001 1000111 Write to first rank
4 1 0 1 1 1 10001 1000111
5 1 0 1 1 1 10000 1100000 Output 16 to Input 32
6 1 0 0 1 1 10000 1100000 Write to first rank
7 1 0 1 1 1 10000 1100000
8 1 0 1 1 0 xxxxx xxxxxxx Transfer to second rank
9 1 0 1 1 1 xxxxx xxxxxxx
10 1 1 1 1 1 xxxxx xxxxxxx Disable interface
01074-031
UPDATE
7
0
1
2
16
33
1 OF 17 DECODERS
WE
D[0:6]
A[0:4]
RANK1 RANK2
17 ROWS OF 7-BIT
LATCHES
RESET
733
733
733
7
7
7
7
0
1
2
16
7
7
7
7
7
7
7
7
7
TO 17
×
33
SWITCH
MATRIX
1 OF 33
DECODERS
RE
Figure 31. Control Interface (Simplified Schematic)
AD8150
Rev. A | Page 21 of 44
CONTROL INTERFACE DESCRIPTION
The AD8150 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data-word stored in each of
these latches indicates to which (if any) of the 33 inputs the
output will be connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second-rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system start-up. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level
translators. These translators allow programming and readback
of the control interface using logic levels different from those in
the signal matrix.
To facilitate multiple chip address decoding, there is a chip-
select pin. All logic signals except the reset pulse are ignored
unless the chip-select pin is active. The chip-select pin disables
only the control logic interface and does not change the
operation of the signal matrix. The chip-select pin does not
power down any of the latches, so any data programmed in the
latches is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
A[4:0] Inputs
Output address pins. The binary encoded address applied to
these five input pins determines which one of the 17 outputs is
being programmed (or being read back). The most significant
bit is A4.
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary
encoded data applied to Pins D[6:0] determine which one of 33
inputs is to be connected to the output specified with the A[4:0]
pins. The most significant bit is D5, and the least significant bit
is D0. Bit D6 is the enable bit, setting the specified output signal
pair to an enabled state if D6 is logic high, or to a disabled state,
high impedance, if D6 is logic low.
In readback mode, Pins D[6:0] are low impedance outputs,
indicating the data-word stored in the second rank for the
output specified with the A[4:0] pins. The readback drivers
were designed to drive high impedances only, so external
drivers connected to D[6:0] should be disabled during readback
mode.
WE Input
First-rank write enable. Forcing this pin to logic LOW allows
the data on Pins D[6:0] to be stored in the first-rank latch for
the output specified by Pins A[4:0]. The WE pin must be
returned to a logic high state after a write cycle to avoid
overwriting the first-rank data.
UPDATE Input
Second-rank write enable. Forcing this pin to logic low allows
the data stored in all 17 first-rank latches to be transferred to
the second-rank latches. The signal connection matrix will be
reprogrammed when the second-rank data is changed. This is a
global pin, transferring all 17 rows of data at once. It is not
necessary to program the address pins. It should be noted that
after initial power-up of the device, the first-rank data is
undefined. It may be desirable to preprogram all seventeen
outputs before performing the first update cycle.
AD8150
Rev. A | Page 22 of 44
RE Input
Second-rank read enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address
with the A[4:0] pins and forcing RE to logic low, the 7-bit data
stored in the second-rank latch for that output address will be
written to the D[6:0] pins. Data should not be written to the
D[6:0] pins externally while in readback mode. The RE and WE
pins are not exclusive and may be used at the same time, but
data should not be written to the D[6:0] pins from external
sources while in readback mode.
CS Input
Chip select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described below. This pin has no effect on the
signal pairs and does not alter any of the stored control data.
RESET Input
Global output disable pin. Forcing the RESET pin to logic low
will reset the enable bit, D6, in all 17 second-rank latches,
regardless of the state of any other pins. This has the effect of
immediately disabling the 17 output signal pairs in the matrix.
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8150 in a system that has multiple output
signal pairs connected together. Failure to do this may result in
several signal outputs contending after power-up. The reset pin
is not gated by the state of the chip-select pin, CS. It should be
noted that the RESET pin does not program the first rank,
which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply VDD and the
negative logic supply VSS must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers.
The signal matrix supplies, VCC and VEE, can be set independent
of the voltage on VDD and VSS, with the constraints that (VDD −
VEE) ≤ 10 V. These constraints will allow operation of the
control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or on −3.3 V or −5 V ECL.
AD8150
Rev. A | Page 23 of 44
CIRCUIT DESCRIPTION
The AD8150 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 1.5 Gbps per channel. The
AD8150 supports PECL-compatible input and output levels
when operated from a 5 V supply (VCC = 5 V, VEE = GND) or
ECL-compatible levels when operated from a −5 V supply (VCC
= GND, VEE = −5 V). To save power, the AD8150 can run from
a 3.3 V supply to interface with low voltage PECL circuits or a
−3.3 V supply to interface with low voltage ECL circuits. The
AD8150 utilizes differential current-mode outputs with
individual disable control, which facilitates busing together the
outputs of multiple AD8150s to assemble larger switch arrays.
This feature also reduces the system to assemble larger switch
arrays, reduces system crosstalk, and can greatly reduce power
dissipation in a large switch array. A single external resistor
programs the current for all enabled output stages, allowing for
user control over output levels with different output
termination schemes and transmission line characteristic
impedances.
HIGH SPEED DATA INPUTS (INxxP, INxxN)
The AD8150 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (VCC) down to include standard ECL or PECL
input levels (VCC − 2 V). The minimum differential input
voltage is less than 300 mV. Unused inputs may be connected
directly to any level within the allowed common-mode input
range. A simplified schematic of the input circuit is shown in
Figure 32.
01074-032
V
CC
V
EE
INxxP INxxN
Figure 32. Simplified Input Circuit
To maintain signal fidelity at the high data rates supported by
the AD8150, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure will depend primarily on the application
and the output circuit of the data source. Standard ECL
components have open emitter outputs that require pull-down
resistors. Three input termination networks suitable for this
type of source are shown in Figure 33. The characteristic
impedance of the transmission line is shown as ZO. The
resistors, R1 and R2, in the Thevenin termination are chosen to
synthesize a VTT source with an output resistance of ZO and an
open-circuit output voltage equal to VCC − 2 V. The load
resistors (RL) in the differential termination scheme are needed
to bias the emitter followers of the ECL source.
01074-033
(b)
INxxP
INxxN
ZO
ZO
R2 R2
R1
R1
ECL SOURCE
V
CC
V
CC
– 2V
V
EE
(a)
INxxP
INxxN
ECL SOURCE
V
CC
V
TT
= VCG2V
Z
O
Z
O
Z
O
Z
O
(c)
INxxP
INxxN
ECL SOURCE
V
CC
V
EE
R
L
R
L
Z
O
Z
O
2Z
O
Figure 33. AD8150 Input Termination from ECL/PECL Sources: a) Parallel
Termination Using VTT Supply; b) Thevenin Equivalent Termination; and
c) Differential Termination
If the AD8150 is driven from a current-mode output stage such
as another AD8150, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
HIGH SPEED DATA OUTPUTS (OUTyyP, OUTyyN)
The AD8150 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 34, is an open-collector NPN
current switch with resistor-programmable tail current and output
compliance extending from the positive supply voltage (VCC)
down to standard ECL or PECL output levels (VCC − 2 V). The
outputs may be disabled individually to permit outputs from
multiple AD8150’s to be connected directly. Since the output
currents of multiple enabled output stages connected in this
way sum, care should be taken to ensure that the output
compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
an inactive driver.
AD8150
Rev. A | Page 24 of 44
01074-034
V
CC
V
EE
V
CC
– 2V
I
OUT
V
EE
DISABLE
OUTyyP OUTyyN
Figure 34. Simplified Output Circuit
To ensure proper operation, all outputs (including unused
output) must be pulled high, using external pull-up networks,
to a level within the output compliance range. If outputs from
multiple AD8150s are wired together, a single pull-up network
may be used for each output bus. The pull-up network should
be chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100K- and 10K-compatible outputs are
shown in Figure 35. Alternatively, a separate supply can be used
to provide VCOM, making RCOM and DCOM unnecessary.
01074-035
OUTyyN
OUTyyP
AD8150
OUTyyN
OUTyyP
AD8150
V
CC
R
L
R
L
R
L
V
CC
R
L
V
COM
R
COM
V
COM
D
COM
Figure 35. Output Pull-Up Networks: a) ECL 100K, b) ECL 10K
The output levels are simply:
()
()
()
ModeDVVV
ModeRIVV
RIVVV
RIVV
VV
COMCCCOM
COM
OUT
CCCOM
L
OUT
OLOHSWING
L
OUT
COMOL
COMOH
K10
K100
−=
−=
=−=
−=
=
The common-mode adjustment element (RCOM or DCOM) may be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground.
When busing together the outputs of multiple AD8150s or
when running at high data rates, double termination of its
outputs is recommended to mitigate the impact of reflections
due to open transmission line stubs and the lumped capacitance
of the AD8150 output pins. A possible connection is shown in
Figure 36; the bypass capacitors provide an ac short from the
common nodes of the termination resistors to ground. To
maintain signal fidelity at high data rates, the stubs connecting
the output pins to the output transmission lines or load resistors
should be as short as possible.
01074-036
R
L
R
L
R
L
R
L
Z
O
Z
O
Z
O
Z
O
V
CC
R
COM
V
COM
OUTyyN
OUTyyP
AD8150
OUTyyN
OUTyyP
AD8150
RECEIVER
Figure 36. Double Termination of AD8150 Outputs
In this case, the output levels are:
(
)
()
()
L
OUT
OLOHSWING
L
OUT
COMOL
L
OUT
COMOH
RIVVV
RIVV
RIVV
21
43
41
=−=
−=
−
=
OUTPUT CURRENT SET PIN (REF)
A simplified schematic of the reference circuit is shown in
Figure 37. A single external resistor connected between the
REF pin and VEE determines the output current for all output
stages. This feature allows a choice of pull-up networks and
transmission line characteristic impedances while still achieving
a nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.
01074-037
R
SET
V
EE
V
CC
I
OUT
/25
AD8150
REF
1.25V
Figure 37. Simplified Reference Circuit
AD8150
Rev. A | Page 25 of 44
The resistor value current is given by the following expression:
OUT
SET I
R25
=
Example:
mA2.16k54.1 == OUTSET IforR
The minimum set resistor is RSET,min = 1 kΩ, resulting in IOUT,max =
25 mA. The maximum set resistor is RSET,max = 5 kΩ, resulting in
IOUT,min = 5 mA. Nominal 800 mV output swings can be achieved
in a 50 Ω load using RSET = 1.56 kΩ (IOUT = 16.2 mA) or in a
doubly terminated 75 Ω load using RSET = 1.17 kΩ (IOUT =
21.3 mA).
To minimize stray capacitance and avoid the pickup of
unwanted signals, the external set resistor should be located
close to the REF pin. Bypassing the set resistor is not
recommended.
POWER SUPPLIES
There are several options for the power supply voltages for the
AD8150, because there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. The voltage levels of these supplies can vary,
depending on the system architecture.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital
ground. VDD should be supplied at a voltage between 3.3 V and
5 V to match the supply voltage of the logic family that is used
to drive the logic inputs. VDD should be bypassed to ground
with a 0.1 µF ceramic capacitor. The absolute maximum voltage
from VDD to VSS is 5.5 V.
Data Path Supplies
The data path supplies have more options for their voltage
levels. The choices here will affect several other areas, such as
power dissipation, bypassing, and common-mode levels of the
inputs and outputs. The more positive voltage supply for the
data paths is VCC (Pins 41, 98, 149, and 171). The more negative
supply is VEE, which appears on many pins that will not be listed
here. The maximum allowable voltage across these supplies is
5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL (emitter-coupled logic) or
PECL (positive ECL). For ECL operation, VCC will be at ground
potential, and VEE will be at a negative supply between −3.3 V
and −5 V. This will make the common-mode voltage of the
inputs and outputs a negative voltage (see Figure 38).
01074-038
V
CC
V
DD
V
EE
V
SS
DATA
PATHS
CONTROL
LOGIC
3V TO 5V
3V TO 5V
GND
GND
0.1μF
0.1μF
(ONE FOR EVERY TWO V
EE
PINS)
AD8150
Figure 38. Power Supplies and Bypassing for ECL Operation
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
the part is to be ac coupled, it is not necessary to have the
input/output common mode at the same level as the other
system circuits, but it will probably be more convenient to use
the same supply rails for all devices.
For PECL operation, VEE will be at ground potential, and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
do not matter, see Figure 39.
01074-039
DATA
PATHS
CONTROL
LOGIC
V
CC
V
DD
V
EE
V
SS
0.1μF0.1μF
(ONE FOR EACH V
CC
PIN,
4 REQUIRED)
3V TO 5V 3V TO 5V
GND GND
AD8150
Figure 39. Power Supplies and Bypassing for PECL Operation
AD8150
Rev. A | Page 26 of 44
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
IN20P
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VCC
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
OUT16N
OUT16P
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VCC
VEE
IN12N
IN12P
IN11N
IN11P
IN10N
IN10P
IN09N
IN09P
IN08N
IN08P
IN07N
IN07P
IN06N
IN06P
IN05N
IN05P
IN04N
IN04P
IN03N
IN03P
IN02N
IN02P
IN01N
IN01P
IN00N
IN00P
OUT00P
OUT00N
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
INDICATOR
AD8150
184L LQFP
TOP VIEW
(Not to Scale)
IN19N
IN19P
IN18N
IN18P
IN17N
IN17P
IN16N
IN16P
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
IN15N
IN15P
IN14N
IN14P
IN13N
IN13P
VEE
VEE
VEE
VEE
VEE
VSS
VCC
VEE
VCC
VEE
VEE
VEE
VCC
VDD
OUT15N
OUT15P
OUT14N
OUT14P
OUT13N
OUT13P
OUT12N
OUT12P
OUT11N
OUT11P
OUT10N
OUT10P
OUT09N
OUT09P
OUT08N
OUT08P
OUT07N
OUT07P
OUT06N
OUT06P
OUT05N
OUT05P
OUT04N
OUT04P
OUT03N
OUT03P
OUT02N
OUT02P
OUT01N
OUT01P
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
01074-050
VCC
C31
0.01μF
VCC C32
0.01μF
VCC
C29
0.01μF
VCC
C4
0.01μF
VCC
C5
0.01μF
VEE
C12
0.01μF
VDD
C14
0.01μF
VCC
C6
0.01μF
VCC
C7
0.01μF
VEE
C13
0.01μFVCC
C30
0.01μF
VCC
C10
0.01μF
VEE
C9
0.01μF
VCC
C8
0.01μF
C11
0.01μF
VEE
C60
0.01μF
C15
0.01μF
R203
1.5kΩ
Figure 40. Bypassing Schematic
AD8150
Rev. A | Page 27 of 44
POWER DISSIPATION
For analysis, the power dissipation of the AD8150 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits, but can be dealt with
separately. The first of these, the control logic, is CMOS
technology and does not dissipate a significant amount of
power. This power will, of course, be greater when the logic
supply is 5 V than when it is 3 V, but overall it is not a significant
amount of power and can be ignored for thermal analysis.
01074-040
DATA
PATHS
CONTROL
LOGIC
V
CC
V
DD
V
EE
I
OUT
R
OUT
V
OUT
LOW – V
EE
V
SS
GND GND
AD8150
I, DATA PATH
LOGIC
Figure 41. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
40 percent in power dissipation.
The power dissipated in the data path outputs is affected by
several factors. The first is whether the outputs are enabled or
disabled. The worst case occurs when all of the outputs are
enabled. The current consumed by the data path logic can be
approximated by
()
[
]
()
enabledoutputsof
II OUT
CC
#
mA3mA20mA5.4mA30
×
×++=
This says that there will always be a minimum of 30 mA
flowing. ICC will increase by a factor that is proportional to both
the number of enabled outputs and the programmed output
current.
The power dissipated in this circuit section will simply be the
voltage of this section (VCC − VEE) times the current. For a worst
case, assume that VCC − VEE is 5.0 V, all outputs are enabled and
the programmed output current is 25 mA. The power dissipated
by the data path logic will be
()
[]
{
}
mW826
17mA3mA20mA25mA5.4mA25V0.5
=
××++=P
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE, and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output
current (and dissipate most of the power for that output), while
the complementary output of the pair will be high and draw
insignificant current. Thus, the power dissipation of the high
output can be ignored, and the output power dissipation for
each output can be assumed to occur in a single static low
output that sinks the full output-programmed current.
The voltage across which this current flows can also vary,
depending on the output circuit design and the supplies that are
used for the data path circuitry. In general, however, there will
be a voltage difference between a logic low signal and VEE. This
is the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs is
(
)
W49.117mA25V5.3 =
×
=
P
AD8150
Rev. A | Page 28 of 44
HEAT SINKING
Depending on several factors in its operation, the AD8150 can
dissipate 2 W or more. The part is designed to operate without
the need for an explicit external heat sink. However, the package
design offers enhanced heat removal via some of the package
pins to the PC board traces.
The VEE pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have finger extensions inside the package that
connect to the paddle on which the IC chip is mounted. These
pins provide a lower thermal resistance from the IC to the VEE
pins than pins that just have a bond wire. As a result, these pins
can be used to enhance the heat removal process from the IC to
the circuit board and ultimately to the ambient.
The VEE pins described above should be connected to a large
area of circuit board trace material to take the most advantage
of their lower thermal resistance. If there is a large area available
on an inner layer that is at VEE potential, then vias can be
provided from the package pin traces to this layer. There should
be no thermal-relief pattern when connecting the vias to the
inner layers for these VEE pins. Additional vias in parallel and
close to the pin leads can provide an even lower thermal
resistive path. If possible to use, 2 oz. copper foil will provide
better heat removal than 1 oz.
The AD8150 package has a specified thermal impedance, θJA, of
30°C/W. This is the worst case still-air value that can be
expected when the circuit board does not significantly enhance
the heat removal from the package. By using the concept
described above or by using forced-air circulation, the thermal
impedance can be lowered.
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and θJA of 30°C/W to yield a 60°C rise above the ambient. There
are many techniques described above that can mitigate this
situation. Most actual circuits will not result in such a high rise
of the junction temperature above the ambient.
AD8150
Rev. A | Page 29 of 44
APPLICATIONS
AD8150 INPUT AND OUTPUT BUSING
Although the AD8150 is a digital part, in any application that
runs at high speed, analog design details will have to be given
very careful consideration. At high data rates, the design of the
signal channels will have a strong influence on the data integrity
and its associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested
circuit board layout for any particular system configuration, this
is not something that can be practically realized. Systems come
in all shapes, sizes, speeds, performance criteria, and cost
constraints. Therefore, some general design guidelines will be
presented that can be used for all systems and judiciously
modified where appropriate.
High speed signals travel best, that is, maintain their integrity,
when they are carried by a uniform transmission line that is
properly terminated at either end. Any abrupt mismatches in
impedance or improper termination will create reflections that
will add to or subtract from parts of the desired signal. Small
amounts of this effect are unavoidable, but too much will distort
the signal to the point that the channel BER will increase. It is
difficult to fully quantify these effects because they are
influenced by many factors in the overall system design.
A constant-impedance transmission line is characterized by
having a uniform cross-sectional profile over its entire length.
In particular, there should be no stubs, which are branches that
intersect the main run of the transmission line. These can have
an electrical appearance that is approximated by a lumped
element, such as a capacitor, or if long enough, as another
transmission line. To the extent that stubs are unavoidable in a
design, their effect can be minimized by making them as short
as possible and as high an impedance as possible.
Figure 36 shows a differential transmission line that connects
two differential outputs from AD8150s to a generic receiver. A
more generalized system can have more outputs bused and
more receivers on the same bus, but the same concepts apply.
The inputs of the AD8150 can also be considered a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The individual outputs of the AD8150 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality,
each external pin of the AD8150 projects into the package and
has a bond wire connected to the chip inside. On-chip wiring
then connects to the collectors of the output transistors and to
ESD protection diodes.
Unlike some other high speed digital components, the AD8150
does not have on-chip terminations. While the location of such
terminations would be closer to the actual end of the
transmission line for some architectures, this concept can limit
system design options. In particular, it is not possible to bus
more than two inputs or outputs on the same transmission line
and it is not possible to change the value of these terminations
to use them for different impedance transmission lines. The
AD8150, with the added ability to disable its outputs, is much
more versatile in these types of architectures.
If the external traces are kept to a bare minimum, the output
will present a mostly lumped capacitive load of about 2 pF. A
single stub of 2 pF will not seriously adversely affect signal
integrity for most transmission lines, but the more of these
stubs, the more adverse their influence will be.
One way to mitigate this effect is to locally reduce the
capacitance of the main transmission line near the point of stub
intersection. Some practical means for doing this are to narrow
the PC board traces in the region of the stub and/or to remove
some of the ground plane(s) near this intersection. The effect of
these techniques will locally lower the capacitance of the main
transmission line at these points, while the added capacitance of
the AD8150 outputs will compensate for this reduction in
capacitance. The overall intent is to create as uniform a
transmission line as possible.
In selecting the location of the termination resistors, it is
important to keep in mind that, as their name implies, they
should be placed at either end of the line. There should be no,
or minimal, projection of the transmission line beyond the
point where the termination resistors connect to it.
AD8150
Rev. A | Page 30 of 44
EVALUATION BOARD
An evaluation board has been designed and is available to
rapidly test the main features of the AD8150. This board lets the
user analyze the analog performance of the AD8150 channels
and easily control the configuration of the board by a standard PC.
Differential inputs and outputs provide the interface for all
channels with the connections made by a 50 Ω SMB-type
connector. This type of connector was chosen for its rapid
mating and unmating action. The use of SMB-type connectors
minimizes the size and minimizes the effort of rearranging
interconnects that would be required if using SMA-type
connectors.
CONFIGURATION PROGRAMMING
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8150
programming via the parallel port of a PC. This requires a user-
supplied standard printer cable that has a DB-25 connector at
one end (parallel- or printer-port interface) and a Centronix-
type connector at the other that connects to P2 of the AD8150
evaluation board. The programming with this scheme is done
in a serial fashion, so it is not the fastest way to configure the
AD8150 matrix. However, the user interface makes it very
convenient to use this programming method.
If a high speed programming interface is desired, the AD8150
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment, such as
the Tektronix HFS-9000 digital test generator, or some other
user-supplied hardware that generates programming signals.
When using the PC interface, the jumper at W1 should be
installed and no connections should be made to P3. When
using the P3 interface, no jumper is installed at W1. There are
locations for termination resistors for the address and data
signals if these are necessary.
POWER SUPPLIES
The AD8150 is designed to work with standard ECL logic
levels. This means that VCC is at ground and VEE is at a negative
supply. The shells of the I/O SMB connectors are at VCC
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, because the test equipment will also have its connector
shells at ground potential.
Operating in PECL mode requires VCC to be at a positive
voltage while VEE is at ground. Since this would make the shells
of the I/O connectors at a positive voltage, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
so that a dangerous situation is not created. Refer to the test
equipment’s manual.
The voltage difference from VCC to VEE can range from 3 V to 5 V.
Power savings can be realized by operating at a lower voltage
without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower. Please consult elsewhere in the data sheet for
the specification for the limits of the VTT supply.
As a practical matter, current on the evaluation board will flow
from the VTT supply through the termination resistors and then
through the AD8150 from its outputs to the VEE supply. When
running in ECL mode, VTT will want to be at a negative supply.
Most power supplies will not allow their ground to connect to
VCC and will not allow their negative supply to connect to VTT.
This will require them to source current from their negative
supply, which will not return to the ground terminal. Thus, VTT
should be referenced to VEE when running in ECL mode, or a
true bipolar supply should be used.
The digital supply is provided to the AD8150 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V and should be matched to the supply voltage of
the logic used to control the AD8150. However, since PCs use 5 V
logic on their parallel port, VDD should be at 5 V when using a
PC to program the AD8150.
SOFTWARE INSTALLATION
The software to operate the AD8150 is provided on two 3.5"
floppy disks. The software is installed by inserting Disk 1 into
the floppy drive of a PC and running the setup.exe program.
This will routinely install the software and prompt the user to
change to Disk 2. The setup program will also prompt the user
to select the directory location to store the program.
After running the software, the user will be prompted to
identify which (of three) software driver is used with the PC’s
parallel port. The default is LPT1, which is most commonly
used. However, some laptops commonly use the PRN driver. It
is also possible that some systems are configured with the LPT2
driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen. This will show a full array of
buttons that allows the connection of any input to output of the
AD8150. All of the outputs should be in the output off state
immediately after the program starts running. Any of the active
buttons can be selected with a mouse click, which will send out
one burst of programming data.
AD8150
Rev. A | Page 31 of 44
After this, the PC keyboard’s left or right arrow key can be held
down to generate a steady stream of programming signals out of
the parallel port. The CLOCK test point on the AD8150
evaluation board can be monitored with an oscilloscope for any
activity (a user-supplied printer cable must be connected). If
there is a square wave present, then the proper software driver
is selected for the PC’s parallel port.
If there is no signal present, then another driver should be tried
by selecting the Parallel Port menu item from the File pull-
down menu selection under the title bar. Select a different
software driver and carry out the above test until signal activity
is present at the CLOCK test point.
SOFTWARE OPERATION
Any button can be clicked in the matrix to program the input-
to-output connection. This will send the proper programming
sequence out of the PC parallel port. Since only one input can
be programmed to a given output at a time, clicking a button in
a horizontal row will cancel previous selections in that row.
However, any number of outputs can share the same input.
Refer to Figure 42.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. After clicking on the Broadcast
Connection button, a window will appear that will prompt the
user to select which input should be connected to all outputs.
The user should type in an integer from 0 to 32 and then click
OK. This will send out the proper program data and return to
the main screen with a full column of buttons selected under
the chosen input.
The off column can be used to disable whichever output one
chooses. To disable all outputs, click the Global Reset button.
This will select the full column of OFF buttons.
Two scratchpad memories (Memory 1 and Memory 2) are
provided to conveniently save a particular configuration.
However, these registers are erased when the program is
terminated. For long-term storage of configurations, the disk’s
storage memory should be used. The Save and Load selections
can be accessed from the File pull-down menu under the title
bar.
01074-041
Figure 42. Evaluation Board Controller
AD8150
Rev. A | Page 32 of 44
PCB LAYOUT
01074-042
Figure 43. Component Side
AD8150
Rev. A | Page 33 of 44
01074-043
Figure 44. Circuit Side
AD8150
Rev. A | Page 34 of 44
01074-044
Figure 45. Silkscreen Top
AD8150
Rev. A | Page 35 of 44
01074-045
Figure 46. Solder Mask Top
AD8150
Rev. A | Page 36 of 44
01074-046
Figure 47. Silkscreen Bottom
AD8150
Rev. A | Page 37 of 44
01074-047
Figure 48. Solder Mask Bottom
AD8150
Rev. A | Page 38 of 44
01074-048
Figure 49. INT1 (VEE)
AD8150
Rev. A | Page 39 of 44
01074-049
Figure 50. INT2 (VCC)
AD8150
Rev. A | Page 40 of 44
P52
P53
R93
IN24P
IN24N
R94
R92
P16
P17
R39
IN06P
IN06N
R40
R38
V
CC
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
P4
P5
R20
IN00P
IN00N
R19
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
R21
P18
P19
R42
IN07P
IN07N
R41
R43
V
CC
V
EE
V
EE
V
CC
P6
P7
R24
IN01P
IN01N
R25
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
R23
V
CC
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
CC
V
CC
V
CC
V
CC
V
CC
P28
P29
R57
IN12P
IN12N
R58
R56
P40
P41
R90
IN18P
IN18N
R89
R91
P54
P55
R96
IN25P
IN25N
R95
R97
V
EE
V
EE
V
CC
V
CC
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
P42
P43
R87
IN19P
IN19N
R88
R86
P64
P65
R117
IN30P
IN30N
R116
R118
V
EE
V
CC
105Ω
1.65kΩ
1.65kΩ
P66
P67
R114
IN31P
IN31N
R115
R113
P56
P57
R99
IN26P
IN26N
R98
R100
P20
P21
R45
IN08P
IN08N
R44
R46
P8
P9
R27
IN02P
IN02N
R28
R26
P32
P33
R63
IN14P
IN14N
R62
R64
P44
P45
R84
IN20P
IN20N
R85
R83
P68
P69
R111
IN32P
IN32N
R112
R110
P60
P61
R105
IN28P
IN28N
R104
R106
P24
P25
R51
IN10P
IN10N
R50
R52
P12
P13
R33
IN04P
IN04N
R34
R32
P36
P37
R69
IN16P
IN16N
R68
R70
P48
P49
R78
IN22P
IN22N
R79
R77
P30
P31
R60
IN13P
IN13N
R59
R61
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
V
CC
V
EE
V
EE
V
CC
P22
P23
R48
IN09P
IN09N
R47
R49
P10
P11
R30
IN03P
IN03N
R31
R29
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
V
EE
V
EE
V
CC
V
CC
P58
P59
R102
IN27P
IN27N
R101
R103
P46
P47
R81
IN21P
IN21N
R82
R80
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
V
CC
V
EE
V
EE
V
CC
P26
P27
R54
IN11P
IN11N
R53
R55
P14
P15
R36
IN05P
IN05N
R37
R35
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
V
EE
V
EE
V
CC
V
CC
P62
P63
R108
IN29P
IN29N
R107
R109
P50
P51
R75
IN23P
IN23N
R76
R74
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
105Ω
1.65kΩ
1.65kΩ
P34
P35
R66
IN15P
IN15N
R65
R67
P38
P39
R72
IN17P
IN17N
R71
R73
P103
P102
R121
OUT00N R122
OUT00P
P87
R160
OUT08N R162
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
V
TT
V
TT
49.9Ω
49.9Ω
49.9Ω
49.9Ω
P86
OUT08P
V
CC
V
TT
C16
0.01μF
0.01μF
0.01μF
V
CC
V
TT
C82
V
CC
V
TT
C83
P71
R200
49.9Ω
OUT16N R198
49.9ΩP70
OUT16P V
TT
OUT15N
OUT15P R190
R192 OUT07N
OUT07P R155
R153
P91
R150
OUT06N R152
P90
OUT06P
P75
R195
OUT14N R193
P74
OUT14P
P89
P88
P73
P72
P93
P92
P77
P76
P97
P96
P81
P80
P101
P100
P85
P84
R180
OUT13N R182
OUT13P R145
OUT05N R143
OUT05P
P95
R140
OUT04N R142
P94
OUT04P
P79
R185
OUT12N R183
P78
OUT12P
R170
OUT11N R172
OUT11P R135
OUT03N R133
OUT03P
P99
R130
OUT02N R132
P98
OUT02P
P83
R175
OUT10N R173
P82
OUT10P
R165
OUT09N R163
OUT09P R125
OUT01N R127
OUT01P
01074-051
Figure 51. Input/Output Connections and Bypassing
AD8150
Rev. A | Page 41 of 44
+
P1 6
P1 1
P1 2
P1 3
P1 4
P1 7
P1 5
+
+C2
10μF
C1
10μF
C3
10μF
P104
P105
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
READ P2 7
RESET P2 3
WRITE P2 8
UPDATE P2 4
CHIP_SELECT P2 2
WRITE P3 13
RESET P3 7
READ P3 11
D0 P3 27
A4 P3 25
A3 P3 23
A2 P3 21
A1 P3 19
A0 P3 17
D6 P3 39
D5 P3 37
D4 P3 35
D3 P3 33
D2
D1 P3 29
UPDATE P3 15
CHIP_SELECT P3 9
VDD P3 5
VSS
VDD
VSS VSS
VSS
VSS
VSS
VSS
P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
A2
DATA P2 5
CLK P2 6
CLK
DATA
P2 25
R7
49Ω
R8
49Ω
R9
49Ω
R10
49Ω
R11
49Ω
R12
49Ω
R13
49Ω
R14
49Ω
R15
49Ω
R16
49Ω
R17
49Ω
R18
49Ω
R1
20kΩ
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
P3 31
A4
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
A3
TP5
TP4
TP6
TP7
TP8
CHIP_SELECT
168
UPDATE
165
WRITE
166
RESET
169
READ
167
A4
74HC132
74HC132
1
24
5
W1
74HC14
A1
74HC14
A1
74HC14
A1
12
3456
74HC74 74HC74
160A4
161A3
162A2
163A1
164A0
TP9
TP10
TP11
TP12
TP13
TP20
TP14
TP15
TP16
TP17
TP18
TP19
153D6
154D5
155D4
156D3
157D2
158D1
159D0
36
VSS VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDD
VCC
VCC
9
10 8
A4
A1
11 10
A1
13 12
12
13 11
A4
74HC14
A1
98
74HC14
74HC14
74HC132
74HC132
VDD
VTT
VCC
VTT
VTT
VCC
VCC
VEE
VEE
VDD
VSS
A1, 4 PIN 14 IS TIED TO VDD.
A1, 4 PIN 7 IS TIED TO VSS.
C86
0.1μFC87
0.1μFC88
0.1μFC89
0.1μF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VEE
VDD
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R2
49kΩ
R3
49kΩ
R4
49kΩ
R5
49kΩ
R6
49kΩ
01074-052
VCC VEE
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
VCC VEE
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43
J44
J45
J46
J47
J48
J49
J50
Figure 52. Control Logic and Bypassing
AD8150
Rev. A | Page 42 of 44
OUTLINE DIMENSIONS
139
138
47
46 92
93
184
TOP VIEW
(PINS DOWN)
1
0.40
BSC
LEAD PITCH
0.23
0.18
0.13
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
22.20
22.00 SQ
21.80
20.20
20.00 SQ
19.80
Figure 53. 184-Lead Low Profile Quad Flat Package [LQFP]
(ST-184)
Dimensions shown in millimeters
ORDERING GUIDE1
Model Temperature Range Package Description Package Option
AD8150AST 0°C to 85°C 184-Lead Low Profile Quad Flat Package [LQFP] ST-184
AD8150ASTZ2 0°C to 85°C 184-Lead Low Profile Quad Flat Package [LQFP] ST-184
AD8150-EVAL Evaluation Board
1 Details of lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package.
2 Z = Pb-free part.
AD8150
Rev. A | Page 43 of 44
NOTES
AD8150
Rev. A | Page 44 of 44
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01074–0–9/05(A)
