STM32F303xB STM32F303xC Arm(R)-based Cortex(R)-M4 32b MCU+FPU, up to 256KB Flash+ 48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V Datasheet - production data Features * Core: Arm(R) Cortex(R)-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit) LQFP48 (7 x 7 mm) LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) * Operating conditions: - VDD, VDDA voltage range: 2.0 V to 3.6 V * Memories - 128 to 256 Kbytes of Flash memory - Up to 40 Kbytes of SRAM, with HW parity check implemented on the first 16 Kbytes. - Routine booster: 8 Kbytes of SRAM on instruction and data bus, with HW parity check (CCM) * CRC calculation unit * Reset and supply management - Power-on/power-down reset (POR/PDR) - Programmable voltage detector (PVD) - Low-power modes: Sleep, Stop and Standby - VBAT supply for RTC and backup registers * Clock management - 4 to 32 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 8 MHz RC with x 16 PLL option - Internal 40 kHz oscillator * Up to 87 fast I/Os - All mappable on external interrupt vectors - Several 5 V-tolerant * Interconnect matrix * 12-channel DMA controller * Four ADCs 0.20 S (up to 39 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, single ended/differential input, separate analog supply from 2 to 3.6 V * Two 12-bit DAC channels with analog supply from 2.4 to 3.6 V October 2018 This is information on a product in full production. WLCSP100 (0.4 mm pitch) * Seven fast rail-to-rail analog comparators with analog supply from 2 to 3.6 V * Four operational amplifiers that can be used in PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V * Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors * Up to 13 timers - One 32-bit timer and two 16-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - Two 16-bit 6-channel advanced-control timers, with up to 6 PWM channels, deadtime generation and emergency stop - One 16-bit timer with 2 IC/OCs, 1 OCN/PWM, deadtime generation and emergency stop - Two 16-bit timers with IC/OC/OCN/PWM, deadtime generation and emergency stop - Two watchdog timers (independent, window) - SysTick timer: 24-bit downcounter - Two 16-bit basic timers to drive the DAC * Calendar RTC with Alarm, periodic wakeup from Stop/Standby * Communication interfaces - CAN interface (2.0B Active) - Two I2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from STOP DS9118 Rev 14 1/149 www.st.com STM32F303xB STM32F303xC - Up to five USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control) - Up to three SPIs, two with multiplexed half/full duplex I2S interface, 4 to 16 programmable bit frames - USB 2.0 full speed interface - Infrared transmitter * Serial wire debug, Cortex(R)-M4 with FPU ETM, JTAG * 96-bit unique ID Table 1. Device summary Reference Part number STM32F303xB STM32F303CB, STM32F303RB, STM32F303VB STM32F303xC STM32F303CC, STM32F303RC, STM32F303VC 2/149 DS9118 Rev 14 STM32F303xB STM32F303xC Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Arm(R) Cortex(R)-M4 core with FPU with embedded Flash and SRAM . . . . 14 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.2 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 22 3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DS9118 Rev 14 3/149 5 Contents STM32F303xB STM32F303xC 3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24 3.17.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25 3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27 3.21 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27 3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28 3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.25 Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.27.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.27.2 Embedded trace macrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 4/149 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 61 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 61 DS9118 Rev 14 STM32F303xB STM32F303xC 7 Contents 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.1 LQFP100 - 14 x 14 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.2 LQFP64 - 10 x 10 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.3 LQFP48 - 7 x 7 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.4 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 135 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 140 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DS9118 Rev 14 5/149 5 List of tables STM32F303xB STM32F303xC List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 6/149 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 12 External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 17 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32F303xB/STM32F303xC I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32F303xB/STM32F303xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 30 No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices . 30 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32F303xB/STM32F303xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 54 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 61 Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 64 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 65 Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 66 Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 66 Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 67 Typical current consumption in Run mode, code with data processing running from Flash 68 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 69 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DS9118 Rev 14 STM32F303xB STM32F303xC Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. List of tables EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 95 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ADC accuracy - limited test conditions, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . 109 ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 113 ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 LQPF100 - 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 126 LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 129 LQFP48 - 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 132 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 137 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DS9118 Rev 14 7/149 7 List of figures STM32F303xB STM32F303xC List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 8/149 STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F303xB/STM32F303xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32F303xB/STM32F303xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32F303xB/STM32F303xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32F303xB/STM32F303xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32F303xB/STM32F303xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = '00') . . . . . . . . . . . 67 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 81 TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 89 Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 89 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . 121 OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP100 - 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 126 LQFP100 - 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 127 LQFP100 - 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 128 LQFP64 - 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 129 LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 130 LQFP64 - 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 131 LQFP48 - 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 132 LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 133 LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 134 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale DS9118 Rev 14 STM32F303xB STM32F303xC Figure 49. Figure 50. List of figures package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 WLCSP100, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DS9118 Rev 14 9/149 9 Introduction 1 STM32F303xB STM32F303xC Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xB/STM32F303xC microcontrollers. This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-M4 core with FPU, refer to: * Cortex(R)-M4 with FPU Technical Reference Manual, available from the http://www.arm.com website. * STM32F3xxx and STM32F4xxx Cortex(R)-M4 programming manual (PM0214) available from our website www.st.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 10/149 DS9118 Rev 14 STM32F303xB STM32F303xC 2 Description Description The STM32F303xB/STM32F303xC family is based on the high-performance Arm(R) Cortex(R)M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash memory, up to 40 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I2Cs, up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL. The STM32F303xB/STM32F303xC family operates in the -40 to +85 C and -40 to +105 C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F303xB/STM32F303xC family offers devices in four packages ranging from 48 pins to 100 pins. The set of included peripherals changes with the device chosen. DS9118 Rev 14 11/149 55 Description STM32F303xB STM32F303xC Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts Peripheral STM32F303Cx STM32F303Rx STM32F303Vx Flash (Kbytes) 128 256 128 256 128 256 SRAM (Kbytes) on data bus 32 40 32 40 32 40 CCM (Core Coupled Memory) RAM (Kbytes) Timers 8 Advanced control 2 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 2 (16-bit) PWM channels (all) (1) 31 33 PWM channels (except complementary) 22 24 SPI (I2S)(2) I Communication USART interfaces UART GPIOs 3(2) 2C 2 3 0 2 CAN 1 USB 1 Normal I/Os (TC, TTa) 20 27 45 in LQFP100 37 in WLCSP100 5-volt tolerant I/Os (FT, FTf) 17 25 42 in LQFP100 40 in WLCSP100 DMA channels Capacitive sensing channels 12 17 15 22 12-bit DAC channels 2 Analog comparator 7 Operational amplifiers 4 CPU frequency Packages 39 in LQFP100 32 in WLCSP100 72 MHz Operating voltage Operating temperature 24 4 12-bit ADCs Number of channels 18 2.0 to 3.6 V Ambient operating temperature: - 40 to 85 C / - 40 to 105 C Junction temperature: - 40 to 125 C LQFP48 LQFP64 LQFP100 WLCSP100 1. This total number considers also the PWMs generated on the complementary output channels 2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode. 12/149 DS9118 Rev 14 STM32F303xB STM32F303xC Description Figure 1. STM32F303xB/STM32F303xC block diagram TPIU ETM SWJTAG Trace/Trig OBL Ibus Cortex M4 CPU Flash interface Voltage reg. 3.3 V to 1.8V MPU/FPU Fmax: 72 MHz System NVIC CCM RAM 8KB POR Supply Supervision Reset Int. POR /PDR NRESET VDDA VSSA PVD SRAM 40 KB @VDDA @VDDA GP DMA1 7 channels RC HS 8MHz GP DMA2 5 channels PLL @VDDIO RC LS XTAL OSC 4 -32 MHz Ind. WDG32K Standby interface AHBPCLK Temp. sensor APBP1CLK 12-bit ADC1 IF Reset & clock control AHB3 VREF+ VREF- VDDIO = 2 to 3.6 V VSS @VDDIO FLASH 256 KB 64 bits Dbus 12-bit ADC2 Power VDD18 BusMatrix TRADECLK TRACED[0-3] as AF JTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO As AF 12-bit ADC3 IF 12-bit ADC4 APBP2CLK HCLK FCLK OSC_IN OSC_OUT VBAT = 1.65V to 3.6V @VSW XTAL 32kHz Backup RTC Reg AWU (64Byte) Backup interface USARTCLK I2CCLK ADC SAR 1/2/3/4 CLK OSC32_IN OSC32_OUT ANTI-TAMP TIMER2 (32-bit/PWM) 4 Channels, ETR as AF GPIO PORT B TIMER 3 4 Channels, ETR as AF PC[15:0] GPIO PORT C TIMER 4 4 Channels, ETR as AF PD[15:0] GPIO PORT D SPI2/I2S MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF PE[15:0] GPIO PORT E SPI3/I2S PF[7:0] GPIO PORT F MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF USART2 RX, TX, CTS, RTS, as AF USART3 RX, TX, CTS, RTS, as AF PB[15:0] XX Groups of 4 channels as AF CRC APB1 Fmax = 36 MHz GPIO PORT A AHB2 PA[15:0] Touch Sensing Controller AHB2 APB2 AHB2 APB1 UART4 RX, TX as AF UART5 RX, TX as AF I2C1 SCL, SDA, SMBA as AF I2C2 SCL, SDA, SMBA as AF WinWATCHDOG EXT.IT WKUP TIMER 15 1 Channel, 1 Comp Channel, BRK as AF TIMER 16 1 Channel, 1 Comp Channel, BRK as AF TIMER 17 4 Channels, 4 Comp channels, ETR, BRK as AF 4 Channels, 4 Comp channels, ETR, BRK as AF TIMER 1 / PWM TIMER7 RX, TX, CTS, RTS, SmartCard as AF USART1 DAC1_CH1 as AF IF 12bit DAC1 @VDDA SYSCFG CTL SPI1 USB_DP, USB_DM TIMER6 TIMER 8 / PWM MOSI, MISO, SCK,NSS as AF CAN TX, CAN RX USB 2.0 FS INTERFACE 2 Channels,1 Comp Channel, BRK as AF bx CAN & 512B SRAM USB SRAM 512B APB2 fmax = 72 MHz XX AF DAC1_CH2 as AF OpAmp1 INxx / OUTxx OpAmp2 INxx / OUTxx OpAmp3 INxx / OUTxx OpAmp4 INxx / OUTxx @VDDA GP Comparator p 7 GP Comparator... GP Comparator 1 Xx Ins, 7 OUTs as AF @VDDA MS18960V4 1. AF: alternate function on I/O pins. DS9118 Rev 14 13/149 55 Functional overview STM32F303xB STM32F303xC 3 Functional overview 3.1 Arm(R) Cortex(R)-M4 core with FPU with embedded Flash and SRAM The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm core, the STM32F303xB/STM32F303xC family is compatible with all Arm tools and software. Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family devices. 3.2 Memory protection unit (MPU) The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3 Embedded Flash memory All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 14/149 DS9118 Rev 14 STM32F303xB STM32F303xC 3.4 Functional overview Embedded SRAM STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM). * 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of CCM RAM). * 3.5 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM). Boot modes At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options: * Boot from user Flash * Boot from system memory * Boot from embedded SRAM The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device firmware upgrade). 3.6 Cyclic redundancy check (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. DS9118 Rev 14 15/149 55 Functional overview STM32F303xB STM32F303xC 3.7 Power management 3.7.1 Power supply schemes * VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins. * VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied to VDDA differs from one analog peripheral to another. Table 3 provides the summary of the VDDA ranges for analog peripherals. The VDDA voltage level must be always greater or equal to the VDD voltage level and must be provided first. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Table 3. External analog supply values for analog peripherals 3.7.2 Analog peripheral Minimum VDDA supply Maximum VDDA supply ADC / COMP 2.0 V 3.6 V DAC / OPAMP 2.4 V 3.6V Power supply supervision The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. * The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. * The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR), and power-down. * The MR mode is used in the nominal regulation mode (Run) * The LPR mode is used in Stop mode. * The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The voltage regulator is always enabled after reset. It is disabled in Standby mode. 16/149 DS9118 Rev 14 STM32F303xB STM32F303xC 3.7.4 Functional overview Low-power modes The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC alarm, COMPx, I2Cx or U(S)ARTx. * Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or an RTC alarm occurs. Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode. 3.8 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix Interconnect source Interconnect destination Interconnect action TIMx Timers synchronization or chaining ADCx DAC1 Conversion triggers DMA Memory to memory transfer trigger Compx Comparator output blanking COMPx TIMx Timer input: OCREF_CLR input, input capture ADCx TIMx Timer triggered by analog watchdog TIMx DS9118 Rev 14 17/149 55 Functional overview STM32F303xB STM32F303xC Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued) Interconnect source Interconnect destination Interconnect action GPIO RTCCLK HSE/32 MC0 TIM16 Clock source used as input channel for HSI and LSI calibration CSS CPU (hard fault) COMPx PVD GPIO TIM1, TIM8, TIM15, 16, 17 Timer break TIMx External trigger, timer break GPIO ADCx DAC1 Conversion external trigger DAC1 COMPx Comparator inverting input Note: For more details about the interconnect actions, please refer to the corresponding sections in the reference manual (RM0316). 3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz. 18/149 DS9118 Rev 14 STM32F303xB STM32F303xC Functional overview Figure 2. Clock tree FLITFCLK to Flash programming interface HSI to I2Cx (x = 1,2) SYSCLK I2SSRC SYSCLK to I2Sx (x = 2,3) Ext. clock I2S_CKIN USB prescaler /1,1.5 8 MHz HSI HSI RC USBCLK to USB interface /2 HCLK PLLSRC PLLMUL PLL x2,x3,.. x16 SW HSI PLLCLK HSE /8 AHB AHB prescaler /1,2,..512 APB1 prescaler /1,2,4,8,16 SYSCLK OSC_OUT OSC_IN OSC32_IN OSC32_OUT PCLK1 SYSCLK HSI LSE 4-32 MHz HSE OSC APB2 prescaler /1,2,4,8,16 /32 LSE OSC 32.768kHz RTCCLK LSI MCO Main clock output MCO PLLCLK HSI LSI HSE SYSCLK to U(S)ARTx (x = 2..5) to APB2 peripherals If (APB2 prescaler =1) x1 else x2 PCLK2 SYSCLK HSI LSE IWDGCLK to IWDG /2 PCLK2 to TIM 2,3,4,6,7 to RTC LSE RTCSEL[1:0] LSI RC 40kHz PCLK1 If (APB1 prescaler =1) x1 else x2 CSS /2,/3,... /16 to AHB bus, core, memory and DMA to cortex System timer FHCLK Cortex free running clock to APB1 peripherals x2 ADC Prescaler /1,2,4 ADC Prescaler /1,2,4,6,8,10,12,16, 32,64,128,256 DS9118 Rev 14 to TIM 15,16,17 to USART1 TIM1/8 to ADCxy (xy = 12, 34) MS19989V5 19/149 55 Functional overview 3.10 STM32F303xB STM32F303xC General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allows I/O toggling up to 36 MHz. 3.11 Direct memory access (DMA) The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC. 3.12 Interrupts and events 3.12.1 Nested vectored interrupt controller (NVIC) The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller (NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels. The NVIC benefits are the following: * Closely coupled NVIC gives low latency interrupt processing * Interrupt entry vector table address passed directly to the core * Closely coupled NVIC core interface * Allows early processing of interrupts * Processing of late arriving higher priority interrupts * Support for tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 20/149 DS9118 Rev 14 STM32F303xB STM32F303xC 3.13 Functional overview Fast analog-to-digital converter (ADC) four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up to 39 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4. Channels can be configured to be either single-ended input or differential input. The ADCs can perform conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADCs have also internal channels: Temperature sensor connected to ADC1 channel 16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 4 ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4 connected to ADC4 channel 17. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold * Single-shunt phase current reading techniques. The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.13.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. 3.13.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADCx_IN18, x=1...4 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. DS9118 Rev 14 21/149 55 Functional overview 3.13.3 STM32F303xB STM32F303xC VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.13.4 OPAMP reference voltage (VREFOPAMP) Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17, VREFOPAMP4 connected to ADC4 channel 17. 3.14 Digital-to-analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 3.15 * Two DAC output channels * 8-bit or 10-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability (for each channel) * External triggers for conversion Operational amplifier (OPAMP) The STM32F303xB/STM32F303xC embeds four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement. The operational amplifier features: 22/149 * 8.2 MHz bandwidth * 0.5 mA output capability * Rail-to-rail input/output * In PGA mode, the gain can be programmed to be 2, 4, 8 or 16. DS9118 Rev 14 STM32F303xB STM32F303xC 3.16 Functional overview Fast comparators (COMP) The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: * External I/O * DAC output pin * Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded internal reference voltage on page 63 for the value and precision of the internal reference voltage. All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator 3.17 Timers and watchdogs The STM32F303xB/STM32F303xC includes two advanced control timers, up to six generalpurpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Advanced TIM1, TIM8 16-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 Yes Generalpurpose TIM2 32-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Note: Capture/ Complementary compare outputs Channels TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz. DS9118 Rev 14 23/149 55 Functional overview 3.17.1 STM32F303xB STM32F303xC Advanced timers (TIM1, TIM8) The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for: * Input capture * Output compare * PWM generation (edge or center-aligned modes) with full modulation capability (0100%) * One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIM timers (described in Section 3.17.2 using the same architecture, so the advanced-control timers can work together with the TIM timers via the Timer Link feature for synchronization or event chaining. 3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) There are up to six synchronizable general-purpose timers embedded in the STM32F303xB/STM32F303xC (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. * TIM2, 3, and TIM4 These are full-featured general-purpose timers: - TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler - TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. * TIM15, 16 and 17 These three timers general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. - TIM15 has 2 channels and 1 complementary channel - TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.17.3 Basic timers (TIM6, TIM7) These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. 24/149 DS9118 Rev 14 STM32F303xB STM32F303xC 3.17.4 Functional overview Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.17.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.18 * A 24-bit down counter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0. * Programmable clock source Real-time clock (RTC) and backup registers The RTC and the 16 backup registers are supplied through a switch that takes power from either the VDD supply when present or the VBAT pin. The backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC is an independent BCD timer/counter.It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Automatic correction for 28, 29 (leap year), 30 and 31 days of the month. * Two programmable alarms with wake up from Stop and Standby mode capability. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stopand Standby modes on tamper event detection. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection. DS9118 Rev 14 25/149 55 Functional overview * STM32F303xB STM32F303xC 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability. The RTC clock sources can be: 3.19 * A 32.768 kHz external crystal * A resonator or oscillator * The internal low-power RC oscillator (typical frequency of 40 kHz) * The high-speed external clock divided by 32. Inter-integrated circuit interface (I2C) Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes. Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 6. Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller. Refer to Table 7 for the features available in I2C1 and I2C2. Table 7. STM32F303xB/STM32F303xC I2C implementation I2C features(1) 26/149 I2C1 I2C2 7-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s) X X Fast mode (up to 400 kbit/s) X X Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X Independent clock X X DS9118 Rev 14 STM32F303xB STM32F303xC Functional overview Table 7. STM32F303xB/STM32F303xC I2C implementation (continued) I2C features(1) I2C1 I2C2 SMBus X X Wakeup from STOP X X 1. X = supported. 3.20 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F303xB/STM32F303xC devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The USART interfaces are able to communicate at speeds of up to 9 Mbits/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. 3.21 Universal asynchronous receiver transmitter (UART) The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller. Refer to Table 8 for the features available in all U(S)ART interfaces. Table 8. USART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 Hardware flow control for modem X X X - - Continuous communication using DMA X X X X - Multiprocessor communication X X X X X Synchronous mode X X X - - Smartcard mode X X X - - Single-wire half-duplex communication X X X X X IrDA SIR ENDEC block X X X X X LIN mode X X X X X Dual clock domain and wakeup from Stop mode X X X X X Receiver timeout interrupt X X X X X Modbus communication X X X X X Auto baud rate detection X X X - - Driver Enable X X X - - 1. X = supported. DS9118 Rev 14 27/149 55 Functional overview 3.22 STM32F303xB STM32F303xC Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. Refer to Table 9 for the features available in SPI1, SPI2 and SPI3. Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation SPI features(1) SPI1 SPI2 SPI3 Hardware CRC calculation X X X Rx/Tx FIFO X X X NSS pulse mode X X X I2S mode - X X TI mode X X X 1. X = supported. 3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 3.24 Universal serial bus (USB) The STM32F303xB/STM32F303xC devices embed an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM memory for data transmission and reception. 28/149 DS9118 Rev 14 STM32F303xB STM32F303xC 3.25 Functional overview Infrared Transmitter The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13. To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels. Figure 3. Infrared transmitter TIMER 16 OC (for envelop) TIMER 17 PB9/PA13 OC (for carrier) MSv30365V1 3.26 Touch sensing controller (TSC) The STM32F303xB/STM32F303xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. DS9118 Rev 14 29/149 55 Functional overview STM32F303xB STM32F303xC Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices Group 1 2 3 4 Capacitive sensing signal name Pin name TSC_G5_IO1 PB3 TSC_G5_IO2 PB4 TSC_G5_IO3 PB6 PA3 TSC_G5_IO4 PB7 TSC_G2_IO1 PA4 TSC_G6_IO1 PB11 TSC_G2_IO2 PA5 TSC_G6_IO2 PB12 TSC_G2_IO3 PA6 TSC_G6_IO3 PB13 TSC_G2_IO4 PA7 TSC_G6_IO4 PB14 TSC_G3_IO1 PC5 TSC_G7_IO1 PE2 TSC_G3_IO2 PB0 TSC_G7_IO2 PE3 TSC_G3_IO3 PB1 TSC_G7_IO3 PE4 TSC_G3_IO4 PB2 TSC_G7_IO4 PE5 TSC_G4_IO1 PA9 TSC_G8_IO1 PD12 TSC_G4_IO2 PA10 TSC_G8_IO2 PD13 TSC_G4_IO3 PA13 TSC_G8_IO3 PD14 TSC_G4_IO4 PA14 TSC_G8_IO4 PD15 Capacitive sensing signal name Pin name TSC_G1_IO1 PA0 TSC_G1_IO2 PA1 TSC_G1_IO3 PA2 TSC_G1_IO4 Group 5 6 7 8 Table 11. No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices Number of capacitive sensing channels Analog I/O group 30/149 STM32F303Vx STM32F303Rx STM32F303Cx G1 3 3 3 G2 3 3 3 G3 3 3 2 G4 3 3 3 G5 3 3 3 G6 3 3 3 G7 3 0 0 G8 3 0 0 Number of capacitive sensing channels 24 18 17 DS9118 Rev 14 STM32F303xB STM32F303xC Functional overview 3.27 Development support 3.27.1 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.27.2 Embedded trace macrocellTM The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F303xB/STM32F303xC through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. DS9118 Rev 14 31/149 55 Pinouts and pin description 4 STM32F303xB STM32F303xC Pinouts and pin description PC14/OSC32_IN 1 2 3 PC15/OSC32_OUT 4 PF0/OSC_IN 5 6 PA14 PB4 PB3 PA15 PB5 PB6 BOOT0 PB7 PB8 VSS VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VDD PB11 VSS PA3 PA4 PA2 10 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PB10 PA1 28 27 26 9 PB2 PA0 8 PB1 VDDA 30 29 7 PA7 PB0 NRST VSSA/VREF- 33 32 31 LQFP48 PA6 PF1/OSC_OUT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PA5 VBAT PC13 PB9 VDD Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout MSv40448V1 32/149 DS9118 Rev 14 STM32F303xB STM32F303xC Pinouts and pin description VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 PF4 VBAT PC13 PC14/OSC32_IN PC15/OSC32_OUT PF0/OSC_IN PF1/OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA/VREFVDDA PA0 PA1 PA2 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VSS PB9 PB8 Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout MS40449V2 DS9118 Rev 14 33/149 55 Pinouts and pin description STM32F303xB STM32F303xC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS PF6 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 PF4 VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14/OSC32_IN PC15/OSC32_OUT PF9 PF10 PF0/OSC_IN PF1/OSC_OUT NRST PC0 PC1 PC2 PC3 PF2 VSSA/VREFVREF+ VDDA PA0 PA1 PA2 MS40450V1 34/149 DS9118 Rev 14 STM32F303xB STM32F303xC Pinouts and pin description Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout 1 2 3 4 5 6 7 8 9 10 PE1 VDD VDD A VSS VSS PC12 PD2 PB3 PB5 B VSS PA15 PD0 PD3 PB4 PB6 PE0 VDD PE5 VDD C PF6 PA14 PD1 PD4 PB7 PB9 VSS PE4 PC13 PC14 OSC32IN D PA12 VDD PC11 PD7 PB8 PE2 PE3 VBAT PC15 OSC32OUT PF9 E PA10 PA11 PA13 PC10 PA9 PE8 PE6 PF2 NRST PF10 F PC8 PC7 PC9 PC6 PA8 PC5 PA2 PE7 PF1 OSCOUT PF0 OSCIN G PD15 PD14 PD13 PD9 PE12 PC4 PA3 PC2 PC1 PC0 H PD12 PD11 PD10 PB15 PE11 PA6 PA5 VSSA PA0 PC3 J VSS PB14 PB13 PB12 VDD PB0 PA4 VREF+ PA1 VDDA VSS VSS PB11 PB10 PB2 PB1 PA7 VDD VSS VSS K BOOT0 MSv40453V1 DS9118 Rev 14 35/149 55 Pinouts and pin description STM32F303xB STM32F303xC Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type I/O structure S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.3V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes Pin functions Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 13. STM32F303xB/STM32F303xC pin definitions LQFP64 LQFP48 I/O structure Notes D6 1 - - PE2 I/O FT (1) TRACECK, TIM3_CH1, TSC_G7_IO1, EVENTOUT - D7 2 - - PE3 I/O FT (1) TRACED0, TIM3_CH2, TSC_G7_IO2, EVENTOUT - C8 3 - - PE4 I/O FT (1) TRACED1, TIM3_CH3, TSC_G7_IO3, EVENTOUT - B9 4 - - PE5 I/O FT (1) TRACED2, TIM3_CH4, TSC_G7_IO4, EVENTOUT - E7 5 - - PE6 I/O FT (1) TRACED3, EVENTOUT D8 6 1 1 VBAT 36/149 Pin name (function after reset) Pin type LQFP100 Pin functions WLCSP100 Pin number S - Alternate functions - DS9118 Rev 14 Additional functions WKUP3, RTC_TAMP3 Backup power supply STM32F303xB STM32F303xC Pinouts and pin description Table 13. STM32F303xB/STM32F303xC pin definitions (continued) 2 2 C10 8 3 3 PC13(2) Notes LQFP48 7 I/O structure LQFP64 C9 Pin name (function after reset) Pin type LQFP100 Pin functions WLCSP100 Pin number Alternate functions Additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT I/O TC - TIM1_CH1N PC14(2) OSC32_IN I/O TC (PC14) - - OSC32_IN - OSC32_OUT D9 9 4 4 PC15(2) OSC32_ OUT (PC15) D10 10 - - PF9 I/O FT (1) TIM15_CH1, SPI2_SCK, EVENTOUT - E10 11 - - PF10 I/O FT (1) TIM15_CH2, SPI2_SCK, EVENTOUT - F10 12 5 5 PF0OSC_IN (PF0) I/O FTf - TIM1_CH3N, I2C2_SDA, OSC_IN F9 13 6 6 PF1OSC_OUT I/O FTf (PF1) - I2C2_SCL OSC_OUT E9 14 7 7 NRST G10 15 8 - PC0 G9 16 9 - PC1 G8 17 10 - PC2 H10 18 11 - PC3 I/O TC - I/O RS T Device reset input / internal reset output (active low) I/O TTa (1) EVENTOUT I/O TTa (1) ADC12_IN6, COMP7_INM EVENTOUT (1) ADC12_IN7, COMP7_INP COMP7_OUT, EVENTOUT I/O TTa I/O TTa (1) TIM1_BKIN2, EVENTOUT EVENTOUT ADC12_IN9 ADC12_IN10 E8 19 - - PF2 H8 20 12 8 VSSA/ VREF- S - - Analog ground/Negative reference voltage J8 21 - - VREF+(3) S - - Positive reference voltage J10 22 - - VDDA S - - Analog power supply - - 13 9 VDDA/ VREF+ S - - Analog power supply/Positive reference voltage H9 23 14 10 PA0 I/O TTa (1) ADC12_IN8 USART2_CTS, ADC1_IN1, COMP1_INM, TIM2_CH1_ETR,TIM8_BKIN, I/O TTa (4) RTC_ TAMP2, WKUP1, TIM8_ETR,TSC_G1_IO1, COMP7_INP COMP1_OUT, EVENTOUT DS9118 Rev 14 37/149 55 Pinouts and pin description STM32F303xB STM32F303xC Table 13. STM32F303xB/STM32F303xC pin definitions (continued) Notes I/O structure Pin name (function after reset) Pin type Pin functions LQFP48 LQFP64 LQFP100 WLCSP100 Pin number Alternate functions Additional functions J9 24 15 11 PA1 USART2_RTS_DE, TIM2_CH2, TSC_G1_IO2, I/O TTa (4) TIM15_CH1N, RTC_REFIN, EVENTOUT F7 25 16 12 PA2 (4) USART2_TX, TIM2_CH3, I/O TTa (5) TIM15_CH1, TSC_G1_IO3, COMP2_OUT, EVENTOUT ADC1_IN3, COMP2_INM, OPAMP1_VOUT G7 26 17 13 PA3 USART2_RX, TIM2_CH4, I/O TTa (4) TIM15_CH2, TSC_G1_IO4, EVENTOUT ADC1_IN4, OPAMP1_VINP, COMP2_INP, OPAMP1_VINM - 27 18 - PF4 I/O TTa (4) COMP1_OUT, EVENTOUT K9, K10 - - - VSS S - - Digital ground K8 28 19 - VDD S - - Digital power supply J7 H7 H6 29 30 31 20 21 22 14 15 16 (1) ADC1_IN5 ADC2_IN1, DAC1_OUT1, OPAMP4_VINP, COMP1_INM, COMP2_INM, COMP3_INM, COMP4_INM, COMP5_INM, COMP6_INM, COMP7_INM PA4 SPI1_NSS, (4) SPI3_NSS,I2S3_WS, I/O TTa (5) USART2_CK, TSC_G2_IO1, TIM3_CH2, EVENTOUT PA5 ADC2_IN2, DAC1_OUT2 OPAMP1_VINP, OPAMP2_VINM, (4) SPI1_SCK, TIM2_CH1_ETR, OPAMP3_VINP I/O TTa (5) TSC_G2_IO2, EVENTOUT COMP1_INM, COMP2_INM, COMP3_INM, COMP4_INM, COMP5_INM, COMP6_INM, COMP7_INM PA6 SPI1_MISO, TIM3_CH1, TIM8_BKIN, TIM1_BKIN, I/O TTa (5) TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT (4) (4) SPI1_MOSI, TIM3_CH2, TIM17_CH1, TIM1_CH1N, TIM8_CH1N, TSC_G2_IO4, COMP2_OUT, EVENTOUT K7 32 23 17 PA7 I/O TTa G6 33 24 - PC4 I/O TTa (4) USART1_TX, EVENTOUT 38/149 ADC1_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP (1) DS9118 Rev 14 ADC2_IN3, OPAMP2_VOUT ADC2_IN4, COMP2_INP, OPAMP2_VINP, OPAMP1_VINP ADC2_IN5 STM32F303xB STM32F303xC Pinouts and pin description Table 13. STM32F303xB/STM32F303xC pin definitions (continued) LQFP100 LQFP64 LQFP48 F6 34 25 - PC5 USART1_RX, TSC_G3_IO1, I/O TTa (1) EVENTOUT J6 35 26 18 PB0 I/O TTa K6 36 27 19 PB1 (4) TIM3_CH4, TIM1_CH3N, I/O TTa (5) TIM8_CH3N, COMP4_OUT, TSC_G3_IO3, EVENTOUT ADC3_IN1, OPAMP3_VOUT- K5 37 28 20 PB2 I/O TTa ADC2_IN12, COMP4_INM, OPAMP3_VINM F8 38 - - PE7 I/O TTa (1) TIM1_ETR, EVENTOUT E6 39 - - PE8 I/O TTa Notes WLCSP100 Pin name (function after reset) I/O structure Pin functions Pin type Pin number - - (1) Alternate functions TIM3_CH3, TIM1_CH2N, TIM8_CH2N,TSC_G3_IO2, EVENTOUT TSC_G3_IO4, EVENTOUT TIM1_CH1N, EVENTOUT (4) Additional functions ADC2_IN11, OPAMP2_VINM, OPAMP1_VINM ADC3_IN12, COMP4_INP, OPAMP3_VINP, OPAMP2_VINP ADC3_IN13, COMP4_INP COMP4_INM, ADC34_IN6 - 40 - - PE9 I/O TTa (1) TIM1_CH1, EVENTOUT ADC3_IN2 - 41 - - PE10 I/O TTa (1) TIM1_CH2N, EVENTOUT ADC3_IN14 (1) H5 42 - - PE11 G5 43 - - PE12 TIM1_CH2, EVENTOUT I/O TTa I/O TTa (1) TIM1_CH3N, EVENTOUT ADC3_IN16 - 44 - - PE13 I/O TTa (1) TIM1_CH3, EVENTOUT ADC3_IN3 (4) ADC3_IN15 - 45 - - PE14 TIM1_CH4, TIM1_BKIN2, I/O TTa (1) EVENTOUT ADC4_IN1 - 46 - - PE15 (4) USART3_RX, TIM1_BKIN, I/O TTa (1) EVENTOUT ADC4_IN2 K4 47 29 21 PB10 I/O TTa - USART3_TX, TIM2_CH3, TSC_SYNC, EVENTOUT COMP5_INM, OPAMP4_VINM, OPAMP3_VINM K3 48 30 22 PB11 I/O TTa - USART3_RX, TIM2_CH4, TSC_G6_IO1, EVENTOUT COMP6_INP, OPAMP4_VINP K1, J1, K2 49 31 23 VSS S - - Digital ground J5 50 32 24 VDD S - - Digital power supply J4 51 33 25 PB12 SPI2_NSS,I2S2_WS,I2C2_S MBA, USART3_CK, I/O TTa (5) TIM1_BKIN, TSC_G6_IO2, EVENTOUT (4) DS9118 Rev 14 ADC4_IN3, COMP3_INM, OPAMP4_VOUT 39/149 55 Pinouts and pin description STM32F303xB STM32F303xC Table 13. STM32F303xB/STM32F303xC pin definitions (continued) 34 26 J2 53 35 27 PB13 PB14 Notes LQFP48 52 I/O structure LQFP64 J3 Pin name (function after reset) Pin type LQFP100 Pin functions WLCSP100 Pin number Alternate functions SPI2_SCK,I2S2_CK,USART3 ADC3_IN5, COMP5_INP, I/O TTa (4) _CTS, TIM1_CH1N, OPAMP4_VINP, TSC_G6_IO3, EVENTOUT OPAMP3_VINP I/O TTa (4) SPI2_MISO,I2S2ext_SD, USART3_RTS_DE, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4, EVENTOUT COMP3_INP, ADC4_IN4, OPAMP2_VINP (4) SPI2_MOSI, I2S2_SD, TIM1_CH3N, RTC_REFIN, TIM15_CH1N, TIM15_CH2, EVENTOUT ADC4_IN5, COMP6_INM H4 54 36 28 PB15 I/O TTa - 55 - - PD8 I/O TTa (1) USART3_TX, EVENTOUT G4 H3 56 57 - - PD9 PD10 Additional functions I/O TTa (1) USART3_RX, EVENTOUT I/O TTa (1) USART3_CK, EVENTOUT ADC4_IN12, OPAMP4_VINM ADC4_IN13 ADC34_IN7, COMP6_INM H2 58 - - PD11 I/O TTa (1) USART3_CTS, EVENTOUT ADC34_IN8, COMP6_INP, OPAMP4_VINP H1 59 - - PD12 USART3_RTS_DE, I/O TTa (1) TIM4_CH1, TSC_G8_IO1, EVENTOUT ADC34_IN9, COMP5_INP G3 60 - - PD13 TIM4_CH2, TSC_G8_IO2, I/O TTa (1) EVENTOUT ADC34_IN10, COMP5_INM G2 61 - - PD14 TIM4_CH3, TSC_G8_IO3, I/O TTa (1) EVENTOUT COMP3_INP, ADC34_IN11, OPAMP2_VINP G1 62 - - PD15 SPI2_NSS, TIM4_CH4, I/O TTa (1) TSC_G8_IO4, EVENTOUT COMP3_INM F4 63 37 - PC6 I/O FT (1) I2S2_MCK, COMP6_OUT, TIM8_CH1, TIM3_CH1, EVENTOUT - F2 64 38 - PC7 I/O FT (1) I2S3_MCK, TIM8_CH2, TIM3_CH2, COMP5_OUT, EVENTOUT - F1 65 39 - PC8 I/O FT (1) TIM8_CH3, TIM3_CH3, COMP3_OUT, EVENTOUT - F3 66 40 - PC9 I/O FT (1) TIM8_CH4, TIM8_BKIN2,TIM3_CH4, I2S_CKIN, EVENTOUT - 40/149 DS9118 Rev 14 STM32F303xB STM32F303xC Pinouts and pin description Table 13. STM32F303xB/STM32F303xC pin definitions (continued) F5 E5 E1 E2 D1 67 68 69 70 71 41 42 43 44 45 29 30 31 32 33 PA8 PA9 PA10 PA11 PA12 I/O FT I/O FTf I/O FTf I/O FT I/O FT Notes I/O structure Pin name (function after reset) Pin type Pin functions LQFP48 LQFP64 LQFP100 WLCSP100 Pin number Alternate functions Additional functions - I2C2_SMBA,I2S2_MCK, USART1_CK, TIM1_CH1, TIM4_ETR, MCO, COMP3_OUT, EVENTOUT - - I2C2_SCL,I2S3_MCK, USART1_TX, TIM1_CH2, TIM2_CH3, TIM15_BKIN, TSC_G4_IO1, COMP5_OUT, EVENTOUT - - I2C2_SDA, USART1_RX, TIM1_CH3, TIM2_CH4, TIM8_BKIN, TIM17_BKIN, TSC_G4_IO2, COMP6_OUT, EVENTOUT - - USART1_CTS, USB_DM, CAN_RX, TIM1_CH1N, TIM1_CH4, TIM1_BKIN2, TIM4_CH1, COMP1_OUT, EVENTOUT - - USART1_RTS_DE, USB_DP, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT - - USART3_CTS, TIM4_CH3, TIM16_CH1N, TSC_G4_IO3, IR_OUT, SWDIO-JTMS, EVENTOUT - E3 72 46 34 PA13 I/O FT C1 73 - - PF6 I2C2_SCL, I/O FTf (1) USART3_RTS_DE, TIM4_CH4, EVENTOUT A1, A2, B1 74 47 35 VSS S - - Ground D2 75 48 36 VDD S - - Digital power supply C2 76 49 37 PA14 I/O FTf - - I2C1_SDA, USART2_TX, TIM8_CH2,TIM1_BKIN, TSC_G4_IO4, SWCLK-JTCK, EVENTOUT DS9118 Rev 14 - 41/149 55 Pinouts and pin description STM32F303xB STM32F303xC Table 13. STM32F303xB/STM32F303xC pin definitions (continued) Notes I/O structure Pin name (function after reset) Pin type Pin functions LQFP48 LQFP64 LQFP100 WLCSP100 Pin number Alternate functions Additional functions I2C1_SCL, SPI1_NSS, SPI3_NSS, I2S3_WS, JTDI, USART2_RX, TIM1_BKIN, TIM2_CH1_ETR, TIM8_CH1, EVENTOUT - B2 77 50 38 PA15 I/O FTf - E4 78 51 - PC10 I/O FT (1) SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, TIM8_CH1N, EVENTOUT - D3 79 52 - PC11 I/O FT (1) SPI3_MISO, I2S3ext_SD, USART3_RX, UART4_RX, TIM8_CH2N, EVENTOUT - A3 80 53 - PC12 I/O FT (1) SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, TIM8_CH3N, EVENTOUT - B3 81 - - PD0 I/O FT (1) CAN_RX, EVENTOUT - C3 82 - - PD1 I/O FT (1) CAN_TX, TIM8_CH4, TIM8_BKIN2,EVENTOUT - A4 83 54 - PD2 I/O FT (1) UART5_RX, TIM3_ETR, TIM8_BKIN, EVENTOUT - B4 84 - - PD3 I/O FT (1) USART2_CTS, TIM2_CH1_ETR, EVENTOUT - C4 85 - - PD4 I/O FT (1) USART2_RTS_DE, TIM2_CH2, EVENTOUT - - 86 - - PD5 I/O FT (1) USART2_TX, EVENTOUT - - 87 - - PD6 I/O FT (1) USART2_RX, TIM2_CH4, EVENTOUT - D4 88 - - PD7 I/O FT (1) USART2_CK, TIM2_CH3, EVENTOUT - - SPI3_SCK, I2S3_CK, SPI1_SCK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM8_CH1N, TSC_G5_IO1, JTDOTRACESWO, EVENTOUT - A5 42/149 89 55 39 PB3 I/O FT DS9118 Rev 14 STM32F303xB STM32F303xC Pinouts and pin description Table 13. STM32F303xB/STM32F303xC pin definitions (continued) B5 A6 B6 90 91 92 56 57 58 40 41 42 PB4 PB5 PB6 C5 93 59 43 PB7 A7 94 60 44 BOOT0 D5 95 61 45 PB8 I/O FT I/O FT I/O FTf I/O FTf I B I/O FTf Notes I/O structure Pin name (function after reset) Pin type Pin functions LQFP48 LQFP64 LQFP100 WLCSP100 Pin number Alternate functions Additional functions - SPI3_MISO, I2S3ext_SD, SPI1_MISO, USART2_RX, TIM3_CH1, TIM16_CH1, TIM17_BKIN, TIM8_CH2N, TSC_G5_IO2, NJTRST, EVENTOUT - - SPI3_MOSI, SPI1_MOSI, I2S3_SD, I2C1_SMBA, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM8_CH3N, TIM17_CH1, EVENTOUT - - I2C1_SCL, USART1_TX, TIM16_CH1N, TIM4_CH1, TIM8_CH1,TSC_G5_IO3, TIM8_ETR, TIM8_BKIN2, EVENTOUT - - I2C1_SDA, USART1_RX, TIM3_CH4, TIM4_CH2, TIM17_CH1N, TIM8_BKIN, TSC_G5_IO4, EVENTOUT - - Boot memory selection - I2C1_SCL, CAN_RX, TIM16_CH1, TIM4_CH3, TIM8_CH2, TIM1_BKIN, TSC_SYNC, COMP1_OUT, EVENTOUT - I2C1_SDA, CAN_TX, TIM17_CH1, TIM4_CH4, TIM8_CH3, IR_OUT, COMP2_OUT, EVENTOUT - C6 96 62 46 PB9 I/O FTf - B7 97 - - PE0 I/O FT (1) USART1_TX, TIM4_ETR, TIM16_CH1, EVENTOUT - A8 98 - - PE1 I/O FT (1) USART1_RX, TIM17_CH1, EVENTOUT - C7 99 63 47 VSS S - - Ground A9, A10, 100 B10, B8 64 48 VDD S - - Digital power supply DS9118 Rev 14 43/149 55 Pinouts and pin description STM32F303xB STM32F303xC 1. Function availability depends on the chosen device. When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode. 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0316 reference manual. 3. The VREF+ functionality is available only on the 100 pin package. On the 64-pin and 48-pin packages, the VREF+ is internally connected to VDDA. 4. Fast ADC channel. 5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O. 44/149 DS9118 Rev 14 Port & Pin Name AF0 PA0 - PA1 RTC_ REFIN AF1 AF2 AF3 AF4 AF5 AF6 TIM2_ CH1_ ETR - TSC_ G1_IO1 - - TIM2_ CH2 - TSC_ G1_IO2 - AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15 - USART2_ COMP1 TIM8_ CTS _OUT BKIN TIM8_ ETR - - - EVENT OUT - - USART2_ RTS_DE TIM15_ CH1N - - - - EVENT OUT DS9118 Rev 14 - TIM2_ CH3 - TSC_ G1_IO3 - - - USART2_ COMP2 TIM15_ TX _OUT CH1 - - - - EVENT OUT PA3 - TIM2_ CH4 - TSC_ G1_IO4 - - - USART2_ RX - - - - - EVENT OUT PA4 - TIM3_ TSC_ CH2 G2_IO1 - SPI1_ NSS USART2_ CK - - - - - - EVENT OUT PA5 - TIM2_ CH1_ ETR TSC_ G2_IO2 - SPI1_ SCK - - - - - - - EVENT OUT PA6 - TIM16_ TIM3_ TSC_ TIM8_ CH1 CH1 G2_IO3 BKIN SPI1_ MISO TIM1_BKIN - COMP1 _OUT - - - - - EVENT OUT PA7 - TIM17_ TIM3_ TSC_ TIM8_ CH1 CH2 G2_IO4 CH1N SPI1_ MOSI TIM1_CH1N - COMP2 _OUT - - - - - EVENT OUT I2C2_ SMBA I2S2_ MCK TIM1_CH1 USART1_ COMP3 CK _OUT - TIM4_ ETR - - - EVENT OUT PA8 MCO - - - - - SPI3_NSS, I2S3_WS - TIM15_ CH2 PA9 - - - I2C2_ TSC_ G4_IO1 SCL I2S3_ MCK TIM1_CH2 USART1_ COMP5 TIM15_ TX _OUT BKIN TIM2_ CH3 - - - EVENT OUT PA10 - TIM17_ BKIN - TSC_ I2C2_ G4_IO2 SDA - TIM1_CH3 USART1_ COMP6 RX _OUT TIM2_ CH4 TIM8_BKIN - - EVENT OUT PA11 - - - - TIM1_CH1N USART1_ COMP1 TIM4_ CAN_RX CTS _OUT CH1 - - - TIM1_CH4 TIM1_ USB_ BKIN2 DM EVENT OUT 45/149 Pinouts and pin description PA2 STM32F303xB STM32F303xC Table 14. Alternate functions for port A Port & Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PA12 - TIM16_ CH1 - - - - TIM1_CH2N PA13 SWDIO TIM16_ -JTMS CH1N - TSC_ G4_IO3 - PA14 SWCLK -JTCK - TSC_ I2C1_ G4_IO4 SDA PA15 JTDI TIM2_ CH1_ ETR TIM8_ CH1 - I2C1_ SCL IR_ OUT AF7 AF8 AF9 AF10 USART1_ COMP2 TIM4_ CAN_TX RTS_DE _OUT CH2 AF11 TIM1_ETR AF12 - AF14 AF15 USB_ DP EVENT OUT USART3_ CTS - - TIM4_ CH3 - - - EVENT OUT TIM8_ TIM1_BKIN CH2 USART2_ TX - - - - - - EVENT OUT SPI1_ NSS USART2_ RX - - - - - EVENT OUT - SPI3_NSS, I2S3_WS TIM1_ BKIN Pinouts and pin description 46/149 Table 14. Alternate functions for port A (continued) DS9118 Rev 14 STM32F303xB STM32F303xC Port & Pin Name AF0 AF1 PB0 - - TIM3_ CH3 TSC_ G3_IO2 PB1 - - TIM3_ CH4 PB2 - - AF2 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 TIM8_ CH2N - TIM1_CH2N - - - - - EVENT OUT TSC_ G3_IO3 TIM8_ CH3N - TIM1_CH3N - COMP4_ OUT - - - EVENT OUT TSC_ G3_IO4 - - - - - - - - EVENT OUT TIM4_ ETR TSC_ G5_IO1 TIM8_ CH1N SPI1_ SCK SPI3_SCK, I2S3_CK USART2_ TX - - TIM3_ ETR - EVENT OUT - AF3 AF4 DS9118 Rev 14 JTDOTIM2_ TRACES CH2 WO PB4 NJTRST TIM16_ TIM3_ CH1 CH1 TSC_ G5_IO2 TIM8_ CH2N SPI1_ MISO SPI3_MISO, I2S3ext_SD USART2_ RX - - TIM17_ BKIN - EVENT OUT PB5 - TIM16_ TIM3_ BKIN CH2 TIM8_ CH3N I2C1_ SMBA SPI1_ MOSI SPI3_MOSI, I2S3_SD USART2_ CK - - TIM17_ CH1 - EVENT OUT PB6 - TIM16_ TIM4_ CH1N CH1 TSC_ G5_IO3 I2C1_SCL TIM8_CH1 TIM8_ ETR USART1_ TX - - TIM8_ BKIN2 - EVENT OUT PB7 - TIM17_ TIM4_ CH1N CH2 TSC_ G5_IO4 I2C1_ SDA TIM8_ BKIN - USART1_ RX - - TIM3_ CH4 - EVENT OUT PB8 - TIM16_ TIM4_ CH1 CH3 TSC_ SYNC I2C1_SCL - - - COMP1_ CAN_RX OUT TIM8_ CH2 PB9 - TIM17_ TIM4_ CH1 CH4 I2C1_ SDA - - COMP2_ CAN_TX OUT TIM8_ CH3 PB10 - TIM2_ CH3 - TSC_ SYNC - - - USART3_ TX - - PB11 - TIM2_ CH4 - TSC_ G6_IO1 - - - USART3_ RX - PB12 - - TSC_ G6_IO2 I2C2_ SMBA USART3_ CK - - SPI2_NSS, I2S2_WS IR_OUT TIM1_ BKIN TIM1_ BKIN EVENT OUT - EVENT OUT - - EVENT OUT - - - EVENT OUT - - - EVENT OUT Pinouts and pin description 47/149 PB3 STM32F303xB STM32F303xC Table 15. Alternate functions for port B Port & Pin Name AF0 AF1 AF2 AF3 AF4 PB13 - - - TSC_ G6_IO3 - SPI2_SCK, I2S2_CK PB14 - TIM15_ CH1 - TSC_ G6_IO4 - PB15 RTC_ REFIN TIM15_ TIM15_ CH2 CH1N - TIM1_ CH3N AF5 AF7 AF8 AF9 AF10 AF12 AF15 TIM1_ CH1N USART3_ CTS - - - - EVENT OUT SPI2_MISO, TIM1_ I2S2ext_SD CH2N USART3_ RTS_DE - - - - EVENT OUT - - - - - EVENT OUT SPI2_MOSI, I2S2_SD AF6 - Pinouts and pin description 48/149 Table 15. Alternate functions for port B (continued) DS9118 Rev 14 STM32F303xB STM32F303xC Port & Pin Name AF1 AF2 AF3 AF4 AF5 AF6 AF7 DS9118 Rev 14 PC0 EVENTOUT - - - - - - PC1 EVENTOUT - - - - - - PC2 EVENTOUT - - - - - PC3 EVENTOUT - - - - PC4 EVENTOUT - - - - - USART1_TX PC5 EVENTOUT - - - - USART1_RX PC6 EVENTOUT TIM3_CH1 - TIM8_CH1 - I2S2_MCK COMP6_OUT PC7 EVENTOUT TIM3_CH2 - TIM8_CH2 - I2S3_MCK COMP5_OUT PC8 EVENTOUT TIM3_CH3 - TIM8_CH3 - PC9 EVENTOUT TIM3_CH4 - TIM8_CH4 I2S_CKIN TIM8_BKIN2 PC10 EVENTOUT - - TIM8_CH1N UART4_TX SPI3_SCK, I2S3_CK USART3_TX PC11 EVENTOUT - - TIM8_CH2N UART4_RX SPI3_MISO, I2S3ext_SD USART3_RX PC12 EVENTOUT - - TIM8_CH3N UART5_TX SPI3_MOSI, I2S3_SD USART3_CK TIM1_CH1N COMP7_OUT TSC_G3_IO1 - - - PC14 - - - PC15 - - - - - COMP3_OUT - - - - - - - - - - - - 49/149 Pinouts and pin description PC13 TIM1_BKIN2 STM32F303xB STM32F303xC Table 16. Alternate functions for port C Port & Pin Name AF1 AF2 AF3 AF4 AF5 AF6 - - - AF7 DS9118 Rev 14 EVENTOUT - - PD1 EVENTOUT - - TIM8_CH4 PD2 EVENTOUT TIM3_ETR - TIM8_BKIN PD3 EVENTOUT TIM2_CH1_ETR - - - - USART2_CTS PD4 EVENTOUT TIM2_CH2 - - - - USART2_RTS_DE PD5 EVENTOUT - - - - - USART2_TX PD6 EVENTOUT TIM2_CH4 - - - - USART2_RX PD7 EVENTOUT TIM2_CH3 - - - - USART2_CK PD8 EVENTOUT - - - - - USART3_TX PD9 EVENTOUT - - - - - USART3_RX PD10 EVENTOUT - - - - - USART3_CK PD11 EVENTOUT - - - - - USART3_CTS PD12 EVENTOUT TIM4_CH1 TSC_G8_IO1 - - - USART3_RTS_DE PD13 EVENTOUT TIM4_CH2 TSC_G8_IO2 - - - - PD14 EVENTOUT TIM4_CH3 TSC_G8_IO3 - - - - PD15 EVENTOUT TIM4_CH4 TSC_G8_IO4 - - UART5_RX TIM8_BKIN2 - SPI2_NSS CAN_RX CAN_TX - - STM32F303xB STM32F303xC PD0 Pinouts and pin description 50/149 Table 17. Alternate functions for port D Port & Pin Name AF0 PE0 - EVENTOUT TIM4_ETR - TIM16_CH1 - USART1_TX PE1 - EVENTOUT - - TIM17_CH1 - USART1_RX AF1 AF2 AF3 AF4 AF6 AF7 PE2 TRACECK EVENTOUT TIM3_CH1 TSC_G7_IO1 - - - PE3 TRACED0 EVENTOUT TIM3_CH2 TSC_G7_IO2 - - - PE4 TRACED1 EVENTOUT TIM3_CH3 TSC_G7_IO3 - - - PE5 TRACED2 EVENTOUT TIM3_CH4 TSC_G7_IO4 - - - PE6 TRACED3 EVENTOUT - - - - DS9118 Rev 14 PE7 - EVENTOUT TIM1_ETR - - - - PE8 - EVENTOUT TIM1_CH1N - - - - PE9 - EVENTOUT TIM1_CH1 - - - - PE10 - EVENTOUT TIM1_CH2N - - - - PE11 - EVENTOUT TIM1_CH2 - - - - PE12 - EVENTOUT TIM1_CH3N - - - - PE13 - EVENTOUT TIM1_CH3 - - - - PE14 - EVENTOUT TIM1_CH4 - - PE15 - EVENTOUT TIM1_BKIN - - TIM1_BKIN2 - STM32F303xB STM32F303xC Table 18. Alternate functions for port E USART3_RX Pinouts and pin description 51/149 Port & Pin Name AF1 AF2 AF3 PF0 - - - I2C2_SDA - PF1 - - - I2C2_SCL - - - - - - - - - - - - - - - AF4 AF5 AF6 TIM1_CH3N AF7 - PF2 EVENTOUT PF4 EVENTOUT COMP1_OUT - PF6 EVENTOUT TIM4_CH4 - PF9 EVENTOUT - TIM15_CH1 - SPI2_SCK - - PF10 EVENTOUT - TIM15_CH2 - SPI2_SCK - - I2C2_SCL USART3_RTS_DE Pinouts and pin description 52/149 Table 19. Alternate functions for port F DS9118 Rev 14 STM32F303xB STM32F303xC STM32F303xB STM32F303xC 5 Memory mapping Memory mapping Figure 8. STM32F303xB/STM32F303xC memory map 0x5000 07FF AHB3 0xFFFF FFFF 7 Cortex-M4 with FPU Internal Peripherals 0xE000 0000 0x5000 0000 Reserved 0x4800 1800 AHB2 0x4800 0000 Reserved 6 0x4002 43FF AHB1 0xC000 0000 0x4002 0000 Reserved 5 0x4001 6C00 APB2 0xA000 0000 0x4001 0000 Reserved 4 0x4000 A000 APB1 0x8000 0000 0x4000 0000 3 0x1FFF FFFF Option bytes 0x6000 0000 0x1FFF F800 System memory 2 0x1FFF D800 Reserved 0x4000 0000 Peripherals 0x1000 2000 CCM RAM 0x1000 0000 Reserved 1 0x2000 0000 0 0x0804 0000 SRAM Flash memory 0x0800 0000 CODE Reserved 0x0004 0000 0x0000 0000 Reserved 0x0000 0000 Flash, system memory or SRAM, depending on BOOT configuration MSv30355V2 DS9118 Rev 14 53/149 55 Memory mapping STM32F303xB STM32F303xC Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses(1) Bus AHB3 AHB2 AHB1 APB2 54/149 Boundary address Size (bytes) Peripheral 0x5000 0400 - 0x5000 07FF 1K ADC3 - ADC4 0x5000 0000 - 0x5000 03FF 1K ADC1 - ADC2 0x4800 1800 - 0x4FFF FFFF ~132 M 0x4800 1400 - 0x4800 17FF 1K GPIOF 0x4800 1000 - 0x4800 13FF 1K GPIOE 0x4800 0C00 - 0x4800 0FFF 1K GPIOD 0x4800 0800 - 0x4800 0BFF 1K GPIOC 0x4800 0400 - 0x4800 07FF 1K GPIOB 0x4800 0000 - 0x4800 03FF 1K GPIOA 0x4002 4400 - 0x47FF FFFF ~128 M 0x4002 4000 - 0x4002 43FF 1K TSC 0x4002 3400 - 0x4002 3FFF 3K Reserved 0x4002 3000 - 0x4002 33FF 1K CRC 0x4002 2400 - 0x4002 2FFF 3K Reserved 0x4002 2000 - 0x4002 23FF 1K Flash interface 0x4002 1400 - 0x4002 1FFF 3K Reserved 0x4002 1000 - 0x4002 13FF 1K RCC 0x4002 0800 - 0x4002 0FFF 2K Reserved 0x4002 0400 - 0x4002 07FF 1K DMA2 0x4002 0000 - 0x4002 03FF 1K DMA1 0x4001 8000 - 0x4001 FFFF 32 K Reserved 0x4001 4C00 - 0x4001 7FFF 13 K Reserved 0x4001 4800 - 0x4001 4BFF 1K TIM17 0x4001 4400 - 0x4001 47FF 1K TIM16 0x4001 4000 - 0x4001 43FF 1K TIM15 0x4001 3C00 - 0x4001 3FFF 1K Reserved 0x4001 3800 - 0x4001 3BFF 1K USART1 0x4001 3400 - 0x4001 37FF 1K TIM8 0x4001 3000 - 0x4001 33FF 1K SPI1 0x4001 2C00 - 0x4001 2FFF 1K TIM1 0x4001 0800 - 0x4001 2BFF 9K Reserved 0x4001 0400 - 0x4001 07FF 1K EXTI 0x4001 0000 - 0x4001 03FF 1K SYSCFG + COMP + OPAMP DS9118 Rev 14 Reserved Reserved STM32F303xB STM32F303xC Memory mapping Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 8000 - 0x4000 FFFF 32 K Reserved 0x4000 7800 - 0x4000 7FFF 2K Reserved 0x4000 7400 - 0x4000 77FF 1K DAC (dual) 0x4000 7000 - 0x4000 73FF 1K PWR 0x4000 6800 - 0x4000 6FFF 2K Reserved 0x4000 6400 - 0x4000 67FF 1K bxCAN 0x4000 6000 - 0x4000 63FF 1K USB SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF 1K USB device FS 0x4000 5800 - 0x4000 5BFF 1K I2C2 0x4000 5400 - 0x4000 57FF 1K I2C1 0x4000 5000 - 0x4000 53FF 1K UART5 0x4000 4C00 - 0x4000 4FFF 1K UART4 0x4000 4800 - 0x4000 4BFF 1K USART3 0x4000 4400 - 0x4000 47FF 1K USART2 0x4000 4000 - 0x4000 43FF 1K I2S3ext 0x4000 3C00 - 0x4000 3FFF 1K SPI3/I2S3 0x4000 3800 - 0x4000 3BFF 1K SPI2/I2S2 0x4000 3400 - 0x4000 37FF 1K I2S2ext 0x4000 3000 - 0x4000 33FF 1K IWDG 0x4000 2C00 - 0x4000 2FFF 1K WWDG 0x4000 2800 - 0x4000 2BFF 1K RTC 0x4000 1800 - 0x4000 27FF 4K Reserved 0x4000 1400 - 0x4000 17FF 1K TIM7 0x4000 1000 - 0x4000 13FF 1K TIM6 0x4000 0C00 - 0x4000 0FFF 1K Reserved 0x4000 0800 - 0x4000 0BFF 1K TIM4 0x4000 0400 - 0x4000 07FF 1K TIM3 0x4000 0000 - 0x4000 03FF 1K TIM2 1. The gray color is used for reserved Flash memory addresses. DS9118 Rev 14 55/149 55 Electrical characteristics STM32F303xB STM32F303xC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = VDDA = 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 56/149 DS9118 Rev 14 MS19211V1 STM32F303xB STM32F303xC 6.1.6 Electrical characteristics Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (LSE, RTC, Wakeup logic, Backup registers) OUT GP I/Os IN Level shifter Power switch 1.65 - 3.6 V VDD I/O logic Kernel logic (CPU, digital & memories) 4 x VDD Regulator 4 x 100 nF + 1 x 4.7 F 4 x VSS VDDA VDDA VREF+ 10 nF + 1 F ADC/DAC VREF- Analog: RCs, PLL,comparators, OPAMP, .... VSSA MS19875V5 1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS9118 Rev 14 57/149 125 Electrical characteristics 6.1.7 STM32F303xB STM32F303xC Current consumption measurement Figure 12. Current consumption measurement scheme I DD_VBAT VBAT IDD VDD IDDA VDDA MS19213V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics, and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 21. Voltage characteristics(1) Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VBAT and VDD) -0.3 4.0 Allowed voltage difference for VDD > VDDA - 0.4 Allowed voltage difference for VREF+ > VDDA - 0.4 Input voltage on FT and FTf pins VSS -0.3 VDD + 4.0 Input voltage on TTa pins VSS -0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 Input voltage on Boot0 pin 0 9 Variations between different VDD power pins - 50 Variations between all the different ground pins(4) - 50 VDD-VDDA VREF+-VDDA(2) VIN(3) |VDDx| |VSSX - VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.12: Electrical sensitivity characteristics 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. The following relationship must be respected between VDDA and VDD: VDDA must power on before or at the same time as VDD in the power up sequence. VDDA must be greater than or equal to VDD. 58/149 DS9118 Rev 14 - STM32F303xB STM32F303xC Electrical characteristics 2. VREF+ must be always lower or equal than VDDA (VREF+ VDDA). If unused then it must be connected to VDDA. 3. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected current values. 4. Include VREF- pin. Table 22. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD power lines (source) 160 IVSS Total current out of sum of all VSS ground lines (sink) - 160 IVDD Maximum current into each VDD power line (source)(1) 100 IVSS (sink)(1) - 100 IIO(PIN) IIO(PIN) Maximum current out of each VSS ground line Output current sunk by any I/O and control pin 25 Output current source by any I/O and control pin -25 Total output current sunk by sum of all IOs and control pins(2) 80 Total output current sourced by sum of all IOs and control pins(2) - 80 Injected current on FT, FTf and B IINJ(PIN) pins(3) -5/+0 (4) 5 Injected current on TC and RST pin Injected current on TTa pins(5) IINJ(PIN) Unit mA 5 Total injected current (sum of all I/O and control pins)(6) 25 1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values. 5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note (2) below Table 70. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 23. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS9118 Rev 14 Value Unit -65 to +150 C 150 C 59/149 125 Electrical characteristics STM32F303xB STM32F303xC 6.3 Operating conditions 6.3.1 General operating conditions Table 24. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 2 3.6 2 3.6 VDD VDDA VBAT Analog operating voltage (OPAMP and DAC not used) Analog operating voltage (OPAMP and DAC used) Must have a potential equal to or higher than VDD 3.6 1.65 3.6 -0.3 VDD+0.3 -0.3 VDDA+0.3 -0.3 5.5 BOOT0 0 5.5 WLCSP100 - 500 LQFP100 - 488 LQFP64 - 444 LQFP48 - 364 -40 85 Low-power dissipation -40 105 Maximum power dissipation -40 105 -40 125 6 suffix version -40 105 7 suffix version -40 125 TC I/O VIN PD TTa I/O I/O input voltage FT and FTf Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2) Ambient temperature for 6 suffix version TA Ambient temperature for 7 suffix version TJ Junction temperature range I/O(1) Maximum power dissipation (3) Low-power dissipation(3) MHz V V 2.4 Backup operating voltage Unit V V mW C C C 1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). 3. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5: Thermal characteristics). 60/149 DS9118 Rev 14 STM32F303xB STM32F303xC 6.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 25 are derived from tests performed under the ambient temperature condition summarized in Table 24. Table 25. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.3 Conditions - VDDA fall time rate Min Max 0 20 0 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 26. Embedded reset and power control block characteristics Symbol VPOR/PDR(1) VPDRhyst (1) tRSTTEMPO(3) Parameter Conditions Power on/power down reset threshold Min Typ Max Unit Falling edge 1.8(2) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis - - 40 - mV POR reset temporization - 1.5 2.5 4.5 ms 1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector monitors only VDD. 2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 3. Guaranteed by design. DS9118 Rev 14 61/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 27. Programmable voltage detector characteristics Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 Min(1) Typ Max(1) Rising edge 2.1 2.18 2.26 Falling edge 2 2.08 2.16 Rising edge 2.19 2.28 2.37 Falling edge 2.09 2.18 2.27 Rising edge 2.28 2.38 2.48 Falling edge 2.18 2.28 2.38 Rising edge 2.38 2.48 2.58 Falling edge 2.28 2.38 2.48 Rising edge 2.47 2.58 2.69 Falling edge 2.37 2.48 2.59 Rising edge 2.57 2.68 2.79 Falling edge 2.47 2.58 2.69 Rising edge 2.66 2.78 2.9 Falling edge 2.56 2.68 2.8 Rising edge 2.76 2.88 3 Falling edge 2.66 2.78 2.9 Conditions V VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 VPVD7 PVD threshold 7 VPVDhyst(2) PVD hysteresis - - 100 - mV IDD(PVD) PVD current consumption - - 0.15 0.26 A 1. Guaranteed by characterization results. 2. Guaranteed by design. 62/149 Unit DS9118 Rev 14 STM32F303xB STM32F303xC 6.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 28. Embedded internal reference voltage Symbol Parameter VREFINT Internal reference voltage TS_vrefint VRERINT TCoeff Conditions Min Typ Max Unit -40 C < TA < +105 C 1.2 1.23 1.25 V (1) -40 C < TA < +85 C 1.2 1.23 ADC sampling time when reading the internal reference voltage - 2.2 - - s Internal reference voltage spread over the temperature range VDD = 3 V 10 mV - - 10(2) mV - - - 100(2) ppm/C Temperature coefficient 1.24 V 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 29. Internal reference voltage calibration values Calibration value name VREFINT_CAL 6.3.5 Description Raw data acquired at temperature of 30 C VDDA= 3.3 V Memory address 0x1FFF F7BA - 0x1FFF F7BB Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load) * All peripherals are disabled except when explicitly mentioned * The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz) * Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) * When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2 * When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or HSE (8 MHz) in bypass mode. DS9118 Rev 14 63/149 125 Electrical characteristics STM32F303xB STM32F303xC The parameters given in Table 30 to Table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24. Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V All peripherals enabled Symbol Parameter Conditions Supply current in Run mode, executing from Flash External clock (HSE bypass) Internal clock (HSI) IDD Max @ TA(1) Typ External clock (HSE bypass) Internal clock (HSI) Max @ TA(1) Typ 25 C 85 C 105 C 72 MHz 61.2 65.8 67.6 68.5 64 MHz 54.7 59.1 60.2 48 MHz 41.7 45.1 32 MHz 28.1 Unit 25 C 85 C 105 C 27.8 30.3 30.7 31.5 61.1 24.6 27.2 27.6 28.3 46.2 47.2 19.2 21.1 21.4 21.8 31.5 32.5 32.7 12.9 14.6 14.8 15.3 24 MHz 21.4 23.7 24.4 25.2 10.0 11.4 11.4 12.1 8 MHz 7.4 8.4 8.6 9.4 3.6 4.1 4.4 5.0 1 MHz 1.3 1.6 1.8 2.6 0.8 1.0 1.2 2.1 64 MHz 49.7 54.4 55.4 56.3 24.5 27.2 27.4 28.1 48 MHz 37.9 42.2 43.0 43.5 18.9 21.4 21.5 21.6 32 MHz 25.8 29.2 29.2 30.0 12.7 14.2 14.6 15.2 24 MHz 19.7 22.3 22.6 23.2 6.7 7.7 7.9 8.5 8 MHz 7.8 8.3 8.8 3.5 4.0 4.4 5.0 72 MHz 60.8 66.2 69.7 70.4(2) 27.4 31.7(2) 32.2 32.5(2) 64 MHz 54.3 59.1 62.2 63.3 24.3 28.3 28.7 28.8 48 MHz 41.0 45.6 47.3 47.9 18.3 21.6 21.9 22.1 32 MHz 27.6 32.4 32.4 32.9 12.3 15.0 15.2 15.4 24 MHz 20.8 23.9 24.3 25.0 9.3 11.3 11.4 12.0 8 MHz 6.9 7.8 8.7 9.0 3.1 3.7 4.2 4.9 1 MHz 0.9 1.2 1.5 2.3 0.4 0.6 1.0 1.8 64 MHz 49.2 53.9 55.2 57.4 23.9 27.8 28.2 28.4 48 MHz 37.3 40.8 41.4 44.1 18.2 21.0 21.6 21.9 32 MHz 25.1 27.6 29.1 30.1 12.0 14.0 14.5 15.1 24 MHz 19.0 21.6 22.1 22.9 6.3 7.2 7.7 8.1 8 MHz 7.3 7.9 8.4 3.0 3.5 4.0 4.7 6.9 (2) Supply current in Run mode, executing from RAM 64/149 fHCLK All peripherals disabled 6.4 DS9118 Rev 14 mA STM32F303xB STM32F303xC Electrical characteristics Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued) All peripherals enabled Symbol Parameter Conditions IDD Supply current in Sleep mode, executing from Flash or RAM External clock (HSE bypass) Internal clock (HSI) fHCLK Max @ TA(1) Typ All peripherals disabled Max @ TA(1) Typ 25 C 85 C 105 C 72 MHz 44.0 48.4 49.4 50.5 64 MHz 39.2 43.3 44.0 48 MHz 29.6 32.7 32 MHz 19.7 Unit 25 C 85 C 105 C 6.6 7.5 7.9 8.7 45.2 6.0 6.8 7.2 7.9 33.3 34.3 4.5 5.2 5.6 6.3 23.3 23.3 23.5 3.1 3.5 4.0 4.8 24 MHz 14.9 17.6 17.8 18.3 2.4 2.8 3.3 3.9 8 MHz 4.9 5.7 6.1 6.9 0.8 1.0 1.4 2.2 1 MHz 0.6 0.9 1.2 2.1 0.1 0.3 0.6 1.5 64 MHz 34.2 38.1 39.2 40.3 5.7 6.3 6.8 7.5 48 MHz 25.8 28.7 29.6 30.3 4.3 4.8 5.2 5.9 32 MHz 17.4 19.4 19.9 20.7 2.9 3.2 3.7 4.5 24 MHz 13.2 15.1 15.6 15.9 1.5 1.8 2.2 2.9 8 MHz 5.0 5.6 6.2 0.7 0.9 1.2 2.1 4.5 mA 1. Guaranteed by characterization results unless otherwise specified. 2. Data based on characterization results and tested in production with code executing from RAM. Table 31. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter IDDA Supply current in Run/Sleep mode, code executing from Flash or RAM Conditions (1) HSE bypass HSI clock fHCLK Typ VDDA = 3.6 V Max @ TA(2) 25 C 85 C 105 C Typ Max @ TA(2) 25 C Unit 85 C 105 C 72 MHz 225 276 289 297 245 302 319 329 64 MHz 198 249 261 268 216 270 284 293 48 MHz 149 195 204 211 159 209 222 230 32 MHz 102 145 152 157 110 154 162 169 24 MHz 80 119 124 128 86 126 131 135 8 MHz 2 3 4 6 3 4 5 9 1 MHz 2 3 5 7 3 4 6 9 64 MHz 270 323 337 344 299 354 371 381 48 MHz 220 269 280 286 244 293 309 318 32 MHz 173 218 228 233 193 239 251 257 24 MHz 151 194 200 204 169 211 219 225 8 MHz 73 97 99 103 88 105 110 116 A 1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the PLL is off, IDDA is independent from the frequency. 2. Guaranteed by characterization results. DS9118 Rev 14 65/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 32. Typical and maximum VDD consumption in Stop and Standby modes Symbol Parameter IDD Typ @VDD (VDD=VDDA) Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 C 85 C 105 C Conditions Regulator in run mode, 20.05 20.33 20.42 20.50 20.67 20.80 44.2(2) 350 Supply all oscillators OFF current in Stop mode Regulator in low-power 7.63 7.77 7.90 8.07 8.17 8.33 30.6(2) 335 mode, all oscillators OFF Supply current in Standby mode LSI ON and IWDG ON 0.80 0.96 1.09 1.23 1.37 1.51 - LSI OFF and IWDG OFF 0.60 0.74 0.83 0.93 1.02 1.11 5.0(2) Unit 735(2) 720(2) A - - 7.8 13.3(2) 1. Guaranteed by characterization results unless otherwise specified. 2. Data based on characterization results and tested in production. Table 33. Typical and maximum VDDA consumption in Stop and Standby modes IDDA Supply current in Standby mode Supply current in Stop mode Supply current in Standby mode VDDA monitoring OFF Supply current in Stop mode Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 C 85 C 105 C Conditions VDDA monitoring ON Symbol Parameter Typ @VDD (VDD = VDDA) Regulator in run mode, 1.81 1.95 2.07 2.20 2.35 2.52 all oscillators OFF 3.7 5.5 8.8 Regulator in low-power mode, all oscillators 1.81 1.95 2.07 2.20 2.35 2.52 OFF 3.7 5.5 8.8 - - - 3.5 5.4 9.2 Regulator in run mode, 1.05 1.08 1.10 1.15 1.22 1.29 all oscillators OFF - - - Regulator in low-power mode, all oscillators 1.05 1.08 1.10 1.15 1.22 1.29 OFF - - - LSI ON and IWDG ON 1.44 1.52 1.60 1.71 1.84 1.98 - - - LSI OFF and IWDG OFF - - - LSI ON and IWDG ON 2.22 2.42 2.59 2.78 LSI OFF and IWDG OFF 3.24 1.69 1.82 1.94 2.08 2.23 2.40 0.93 0.95 0.98 1.02 1.08 1.15 1. Guaranteed by characterization results. The total consumption is the sum of IDD and IDDA. 66/149 3.0 DS9118 Rev 14 Unit A STM32F303xB STM32F303xC Electrical characteristics Table 34. Typical and maximum current consumption from VBAT supply Symbol Para meter Max @VBAT = 3.6 V(2) Typ @VBAT Conditions (1) LSE & RTC ON; "Xtal mode" lower driving capability; Backup LSEDRV[1: domain 0] = '00' IDD_VBAT supply LSE & RTC current ON; "Xtal mode" higher driving capability; LSEDRV[1: 0] = '11' 1.65V 1.8V 2V 0.48 0.50 0.52 2.4V 2.7V 0.58 3V Unit TA = TA = TA = 3.3V 3.6V 25C 85C 105C 0.65 0.72 0.80 0.90 1.1 1.5 2.0 A 0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5 2.2 2.9 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization results. Figure 13. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = '00') 1.4 1.2 1.65 V 1.8 V 2V 0.8 2.4 V 0.6 2.7 V 0.4 3V I VBAT (A) 1 3.3 V 0.2 3.6 V 0 25C 60C 85C 105C TA (C) MS31124V1 DS9118 Rev 14 67/149 125 Electrical characteristics STM32F303xB STM32F303xC Typical current consumption The MCU is placed under the following conditions: * VDD = VDDA = 3.3 V * All I/O pins available on each package are in analog input configuration * The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON * When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB * PLL is used for frequencies greater than 8 MHz * AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz, 500 kHz and 125 kHz respectively. Table 35. Typical current consumption in Run mode, code with data processing running from Flash Typ Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash IDDA(1) (2) Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 61.3 28.0 64 MHz 54.8 25.4 48 MHz 41.9 19.3 32 MHz 28.5 13.3 24 MHz 21.8 10.4 16 MHz 14.9 7.2 8 MHz 7.7 3.9 4 MHz 4.5 2.5 2 MHz 2.8 1.7 1 MHz 1.9 1.3 500 kHz 1.4 1.1 125 kHz 1.1 0.9 72 MHz 240.3 239.5 64 MHz 210.9 210.3 48 MHz 155.8 155.6 32 MHz 105.7 105.6 24 MHz 82.1 82.0 16 MHz 58.8 58.8 8 MHz 2.4 2.4 4 MHz 2.4 2.4 2 MHz 2.4 2.4 1 MHz 2.4 2.4 500 kHz 2.4 2.4 125 kHz 2.4 2.4 Unit mA A 1. VDDA monitoring is ON. 2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. 68/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA(1) (2) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 44.1 7.0 64 MHz 39.7 6.3 48 MHz 30.3 4.9 32 MHz 20.5 3.5 24 MHz 15.4 2.8 16 MHz 10.6 2.0 8 MHz 5.4 1.1 4 MHz 3.2 1.0 2 MHz 2.1 0.9 1 MHz 1.5 0.8 500 kHz 1.2 0.8 125 kHz 1.0 0.8 72 MHz 239.7 238.5 64 MHz 210.5 209.6 48 MHz 155.0 155.6 32 MHz 105.3 105.2 24 MHz 81.9 81.8 16 MHz 58.7 58.6 8 MHz 2.4 2.4 4 MHz 2.4 2.4 2 MHz 2.4 2.4 1 MHz 2.4 2.4 500 kHz 2.4 2.4 125 kHz 2.4 2.4 Unit mA A 1. VDDA monitoring is ON. 2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. DS9118 Rev 14 69/149 125 Electrical characteristics STM32F303xB STM32F303xC I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 54: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (seeTable 38: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 70/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 37. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT +CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 47 pF C = CINT + CEXT+ CS I/O toggling frequency (fSW) Typ 2 MHz 0.90 4 MHz 0.93 8 MHz 1.16 18 MHz 1.60 36 MHz 2.51 48 MHz 2.97 2 MHz 0.93 4 MHz 1.06 8 MHz 1.47 18 MHz 2.26 36 MHz 3.39 48 MHz 5.99 2 MHz 1.03 4 MHz 1.30 8 MHz 1.79 18 MHz 3.01 36 MHz 5.99 2 MHz 1.10 4 MHz 1.31 8 MHz 2.06 18 MHz 3.47 36 MHz 8.35 2 MHz 1.20 4 MHz 1.54 8 MHz 2.46 18 MHz 4.51 36 MHz 9.98 Unit mA 1. CS = 5 pF (estimated value). DS9118 Rev 14 71/149 125 Electrical characteristics STM32F303xB STM32F303xC On-chip peripheral current consumption The MCU is placed under the following conditions: * all I/O pins are in analog input configuration * all peripherals are disabled unless otherwise mentioned * the given value is calculated by measuring the current consumption * - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature at 25C and VDD = VDDA = 3.3 V. Table 38. Peripheral current consumption Peripheral Typical consumption(1) Unit IDD BusMatrix (2) 12.6 DMA1 7.6 DMA2 6.1 CRC 2.1 GPIOA 10.0 GPIOB 10.3 GPIOC 2.2 GPIOD 8.8 GPIOE 3.3 GPIOF 3.0 TSC 5.5 ADC1&2 17.3 ADC3&4 18.8 APB2-Bridge (3) 3.6 SYSCFG 7.3 TIM1 40.0 SPI1 8.8 TIM8 36.4 USART1 23.3 TIM15 17.1 TIM16 10.1 TIM17 APB1-Bridge 72/149 11.0 (3) 6.1 TIM2 49.1 TIM3 38.8 TIM4 38.3 DS9118 Rev 14 A/MHz STM32F303xB STM32F303xC Electrical characteristics Table 38. Peripheral current consumption (continued) Peripheral Typical consumption(1) Unit IDD TIM6 9.7 TIM7 12.1 WWDG 6.4 SPI2 40.4 SPI3 40.0 USART2 41.9 USART3 40.2 UART4 36.5 UART5 30.8 I2C1 10.5 I2C2 10.4 USB 26.2 CAN 33.4 PWR 5.7 DAC 15.4 A/MHz 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections. 2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2). 3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus. DS9118 Rev 14 73/149 125 Electrical characteristics 6.3.6 STM32F303xB STM32F303xC Wakeup time from low-power mode The wakeup times given in Table 39 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep mode: the wakeup event is WFE. * WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 39. Low-power mode wakeup timings Symbol tWUSTOP Parameter Wakeup from Stop mode Typ @VDD, VDD = VDDA Conditions 2.4 V 2.7 V 3V 3.3 V 3.6 V Regulator in run mode 4.1 3.9 3.8 3.7 3.6 3.5 4.5 Regulator in low-power mode 7.9 6.7 6.1 5.7 5.4 5.2 9 69.2 60.3 56.4 53.7 51.7 50 100 tWUSTANDBY(1) Wakeup from LSI and Standby mode IWDG OFF tWUSLEEP Wakeup from Sleep mode - 6 1. Guaranteed by characterization results. 74/149 Max 2.0 V DS9118 Rev 14 - Unit s CPU clock cycles STM32F303xB STM32F303xC 6.3.7 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 14. Table 40. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 32 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD 15 - - - - 20 tw(HSEH) tw(HSEL) tr(HSE) tf(HSE) OSC_IN high or low - time(1) V ns OSC_IN rise or fall time(1) 1. Guaranteed by design. Figure 14. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tw(HSEL) t THSE MS19214V2 DS9118 Rev 14 75/149 125 Electrical characteristics STM32F303xB STM32F303xC Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15 Table 41. Low-speed external user clock characteristics Symbol Parameter Conditions fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSEH) tw(LSEL) OSC32_IN high or low time(1) tr(LSE) tf(LSE) Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD V - VSS - 0.3VDD 450 - ns OSC32_IN rise or fall time(1) - - 50 1. Guaranteed by design. Figure 15. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 76/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 42. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 42. HSE oscillator characteristics Symbol fOSC_IN RF Conditions(1) Min(2) Typ Max(2) Unit Oscillator frequency - 4 8 32 MHz Feedback resistor - - 200 - - 8.5 VDD=3.3 V, Rm= 30, CL=10 pF@8 MHz - 0.4 - VDD=3.3 V, Rm= 45, CL=10 pF@8 MHz - 0.5 - VDD=3.3 V, Rm= 30, CL=5 pF@32 MHz - 0.8 - VDD=3.3 V, Rm= 30, CL=10 pF@32 MHz - 1 - VDD=3.3 V, Rm= 30, CL=20 pF@32 MHz - 1.5 - Startup 10 - - mA/V VDD is stabilized - 2 - ms Parameter During startup IDD gm tSU(HSE)(4) HSE current consumption Oscillator transconductance Startup time (3) k mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DS9118 Rev 14 77/149 125 Electrical characteristics STM32F303xB STM32F303xC For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 16. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. 78/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 43. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 43. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol IDD gm tSU(LSE)(3) Parameter LSE current consumption Oscillator transconductance Startup time Conditions(1) Min(2) Typ Max(2) LSEDRV[1:0]=00 lower driving capability - 0.5 0.9 LSEDRV[1:0]=10 medium low driving capability - - 1 LSEDRV[1:0]=01 medium high driving capability - - 1.3 LSEDRV[1:0]=11 higher driving capability - - 1.6 LSEDRV[1:0]=00 lower driving capability 5 - - LSEDRV[1:0]=10 medium low driving capability 8 - - LSEDRV[1:0]=01 medium high driving capability 15 - - LSEDRV[1:0]=11 higher driving capability 25 - - VDD is stabilized - 2 - Unit A A/V s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 2. Guaranteed by design. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DS9118 Rev 14 79/149 125 Electrical characteristics STM32F303xB STM32F303xC Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.8 Internal clock source characteristics The parameters given in Table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24. High-speed internal (HSI) RC oscillator Table 44. HSI oscillator characteristics(1) Symbol fHSI TRIM DuCy(HSI) ACCHSI Parameter Conditions Min Typ - - Frequency IDDA(HSI) - MHz (2) - 1 % - 45(2) - 55(2) % TA = -40 to 105C -2.8(3) - 3.8(3) TA = -10 to 85C -1.9(3) - 2.3(3) TA = 0 to 85C -1.9(3) - 2(3) TA = 0 to 70C -1.3(3) - 2(3) TA = 0 to 55C -1(3) - 2(3) -1 - 1 - 2(2) s 80 100(2) A Duty cycle HSI oscillator startup time - 1(2) HSI oscillator power consumption - - 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. 80/149 8 - TA = 25C(4) tsu(HSI) Unit - HSI user trimming step Accuracy of the HSI oscillator Max DS9118 Rev 14 % STM32F303xB STM32F303xC Electrical characteristics Figure 18. HSI oscillator accuracy characterization results for soldered parts 4% MAX MIN 3% 2% 1% 0% -40 -20 0 20 40 60 80 100 T [C] 120 A -1% -2% -3% -4% MS30985V4 Low-speed internal (LSI) RC oscillator Table 45. LSI oscillator characteristics(1) Symbol fLSI Parameter Frequency Min Typ Max Unit 30 40 50 kHz tsu(LSI)(2) LSI oscillator startup time - - 85 s IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 A 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design. DS9118 Rev 14 81/149 125 Electrical characteristics 6.3.9 STM32F303xB STM32F303xC PLL characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24. Table 46. PLL characteristics Value Symbol fPLL_IN fPLL_OUT tLOCK Jitter Parameter Unit Min Typ Max PLL input clock(1) 1(2) - 24(2) PLL input clock duty cycle 40(2) - (2) PLL multiplier output clock (2) 16 - 72 MHz - - 200(2) s - 300(2) ps PLL lock time Cycle-to-cycle jitter - 60 MHz % 1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design. 6.3.10 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 47. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = -40 to +105 C 40 53.5 60 s Page (2 KB) erase time TA = -40 to +105 C 20 - 40 ms tME Mass erase time TA = -40 to +105 C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design. Table 48. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle(2) at TA = 105 C 10 10 kcycles (2) at TA = 55 C 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 82/149 Min(1) DS9118 Rev 14 20 Unit kcycles Years STM32F303xB STM32F303xC 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 49. They are based on the EMS levels and classes defined in the application note AN1709. Table 49. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP100, TA = +25C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25C, fHCLK = 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) DS9118 Rev 14 83/149 125 Electrical characteristics STM32F303xB STM32F303xC Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 50. EMI characteristics Symbol Parameter SEMI 6.3.12 Monitored frequency band Conditions Max vs. [fHSE/fHCLK] Unit 8/72 MHz 0.1 to 30 MHz VDD = 3.6 V, TA = 25 C, 30 to 130 MHz LQFP100 package Peak level compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 7 20 dBV 27 4 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1 standard. Table 51. ESD absolute maximum ratings Symbol Ratings Electrostatic VESD(HBM) discharge voltage (human body model) Conditions TA = +25 C, conforming to ANSI/ESDA/JEDEC JS-001 Electrostatic TA = +25 C, conforming VESD(CDM) discharge voltage to ANSI/ESDA/JEDEC JS-002 (charge device model) 1. Guaranteed by characterization results. 84/149 DS9118 Rev 14 Packages Class All 2 Maximum Unit value(1) 2000 V All C2a 500 STM32F303xB STM32F303xC Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 52. Electrical sensitivities Symbol LU 6.3.13 Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The test results are given in Table 53. DS9118 Rev 14 85/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 53. I/O current injection susceptibility Functional susceptibility Symbol IINJ Note: 86/149 Description Negative injection Positive injection Injected current on BOOT0 -0 NA Injected current on PC0, PC1, PC2, PC3, PF2, PA0, PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5, PB2 with induced leakage current on other pins from this group less than -50 A -5 - Injected current on PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than -50 A -5 - Injected current on PC0, PC1, PC2, PC3, PF2, PA0, PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5, PB2, PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than 400 A - +5 Injected current on any other FT and FTf pins -5 NA Injected current on any other pins -5 +5 mA It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DS9118 Rev 14 Unit STM32F303xB STM32F303xC 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 54 are derived from tests performed under the conditions summarized in Table 24. All I/Os are CMOS and TTL compliant. Table 54. I/O static characteristics Symbol VIL VIH Parameter Low level input voltage High level input voltage Conditions Min Vhys Ilkg Input leakage current (3) Max Unit (1) TC and TTa I/O - - 0.3 VDD+0.07 FT and FTf I/O - - 0.475 VDD-0.2 (1) BOOT0 - - 0.3 VDD-0.3 (1) All I/Os except BOOT0 - - 0.3 VDD (2) TC and TTa I/O 0.445 VDD+0.398 (1) - - FT and FTf I/O 0.5 VDD+0.2 (1) - - - - BOOT0 0.2 VDD+0.95 All I/Os except BOOT0 Schmitt trigger hysteresis Typ 0.7 VDD (2) (1) - V (1) - TC and TTa I/O - 200 FT and FTf I/O - 100 (1) - BOOT0 - 300 (1) - TC, FT and FTf I/O TTa I/O in digital mode VSS VIN VDD - - 0.1 TTa I/O in digital mode VDD VIN VDDA - - 1 TTa I/O in analog mode VSS VIN VDDA - - 0.2 FT and FTf I/O(4) VDD VIN 5 V - - 10 mV A RPU Weak pull-up equivalent resistor(5) VIN = VSS 25 40 55 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 25 40 55 k CIO I/O pin capacitance - - 5 - pF 1. Data based on design simulation. 2. Tested in production. 3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 53: I/O current injection susceptibility. 4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). DS9118 Rev 14 87/149 125 Electrical characteristics STM32F303xB STM32F303xC All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 19 and Figure 20 for standard I/Os. Figure 19. TC and TTa I/O input characteristics - CMOS port VIL/VIH (V) equir dard r stan MOS VIHmin 2.0 Tested ts VIH emen C uction in prod 1.3 min = D 0.7VD 98 ns +0.3 5V DD imulatio 0.44 s = n V IHmin on desig d Base ns 0.07imulatio D+ 0.3V Design s x= d a m V IL ed on Bas Area not determined CMOS standard requirements VILmax = 0.3VDD VILmax 0.7 0.6 tion roduc ted in p Tes 2.0 VDD (V) 2.7 3.0 3.3 3.6 MS30255V2 Figure 20. TC and TTa I/O input characteristics - TTL port VIL/VIH (V) TTL standard requirements V IHmin = 2V VIHmin 2.0 ns 7 +0.0 ulatio .3V DD ign sim 0 = V ILmax on des d Base 1.3 Area not determined VILmax 0.8 0.7 98 +0.3 lations 5V DD u 0.44 ign sim = V IHmin on des d Base TTL standard requirements V ILmax = 0.8V VDD (V) 2.0 2.7 3.0 3.3 3.6 MS30256V2 88/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port VIL/VIH (V) min ts VIH emen requir ndard sta MOS 0.2 ulations V DD+ = 0.5 sign sim e on d ased C 2.0 VDD = 0.7 V IHmin B -0.2 lations u 75V DD = 0.4 esign sim on d d e s a V ILmax B Area not determined 1.0 ax = 0.3VDD ments VILm rd require CMOS standa 0.5 VDD (V) 2.0 3.6 2.7 MS30257V3 Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port VIL/VIH (V) TTL standard requirements VIHmin = 2V 2.0 Area not determined 1.0 0.8 ns 0.2 V DD+ simulatio = 0.5 n V IHmin n desig do Base -0.2 tions 75V DD imula = 0.4design s in m V IL d on Base TTL standard requirements VILmax = 0.8V 0.5 VDD (V) 2.0 2.7 3.6 MS30258V2 DS9118 Rev 14 89/149 125 Electrical characteristics STM32F303xB STM32F303xC Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 22). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 22). Output voltage levels Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL compliant. Table 55. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL (1) Output low level voltage for an I/O pin VOH (3) Output high level voltage for an I/O pin VOL(1)(4) Output low level voltage for an I/O pin VOH(3)(4) Output high level voltage for an I/O pin VOL(1)(4) Output low level voltage for an I/O pin VOH(3)(4) Output high level voltage for an I/O pin VOLFM+(1)(4) Output low level voltage for an FTf I/O pin in FM+ mode Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD-0.4 - - 0.4 2.4 - - 1.3 VDD-1.3 - - 0.4 VDD-0.4 - - 0.4 TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V IIO = +20 mA 2.7 V < VDD < 3.6 V Unit V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (I/O ports and control pins) must not exceed IIO(PIN). 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (I/O ports and control pins) must not exceed IIO(PIN). 4. Data based on design simulation. 90/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 56, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 56. I/O AC characteristics(1) OSPEEDRy [1:0] value(1) x0 01 Symbol Parameter fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Conditions Min Max Unit - 2(3) MHz - 125(3) - 125 (3) - 10(3) - 25(3) - (3) 25 - 50(3) MHz - 30(3) MHz - 20(3) MHz CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) - 2(4) - 12(4) - 34(4) 10(3) - CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V fmax(IO)out Maximum CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 11 tf(IO)out tr(IO)out FM+ configuration(4) - Output high to low level fall time Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller MHz CL = 50 pF, VDD = 2 V to 3.6 V CL = 30 pF, VDD = 2.7 V to 3.6 V frequency(2) ns CL = 50 pF, VDD = 2 V to 3.6 V - ns ns MHz ns ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 23. 3. Guaranteed by design. 4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F303x STM32F313xx reference manual RM0316 for a description of FM+ I/O mode configuration. DS9118 Rev 14 91/149 125 Electrical characteristics STM32F303xB STM32F303xC Figure 23. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON 50pF tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131c 6.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 54). Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24. Table 57. NRST pin characteristics Symbol Parameter VIL(NRST)(1) NRST Input low level voltage Conditions Min Typ Max - - - 0.3VDD+ 0.07(1) - - Unit V VIH(NRST)(1) NRST Input high level voltage - 0.445VDD+ 0.398(1) Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 25 40 55 k - 100(1) ns - - ns RPU VF(NRST)(1) VNF(NRST)(1) Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse - (1) 500 1. Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 92/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Figure 24. Recommended NRST pin protection VDD External reset circuitry (1) RPU Internal reset NRST (2) Filter 0.1 F MS19878V1 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 57. Otherwise the reset will not be taken into account by the device. 6.3.16 Timer characteristics The parameters given in Table 58 are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 58. TIMx(1)(2) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER tMAX_COUNT Parameter Timer resolution time Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period Maximum possible count with 32-bit counter Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns fTIMxCLK = 144 MHz x=1.8 6.95 - ns 0 fTIMxCLK/2 MHz fTIMxCLK = 72 MHz 0 36 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 s fTIMxCLK = 144 MHz x=1.8 0.0069 455 s - - 65536 x 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.65 s fTIMxCLK = 144 MHz x=1.8 - 29.825 s - bit 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 timers. 2. Guaranteed by design. DS9118 Rev 14 93/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 59. IWDG min/max timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller's internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 60. WWDG min-max timeout value @72 MHz (PCLK)(1) Prescaler WDGTB Min timeout value Max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 1. Guaranteed by design. 94/149 DS9118 Rev 14 STM32F303xB STM32F303xC 6.3.17 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev.03 for: * Standard-mode (Sm) : with a bit rate up to 100 Kbits/s * Fast-mode (Fm) : with a bit rate up to 400 Kbits/s * Fast-mode Plus (Fm+) : with a bit rate up to 1Mbits/s The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port characteristics. All I2C I/Os embed an analog filter. refer to theTable 62: I2C analog filter characteristics. Table 61. I2C timings specification (see I2C specification, rev.03, June 2007)(1) Standard mode Symbol Fast mode Fast Mode Plus Parameter Unit Min Max Min Max Min Max 0 100 0 400 0 1000 KHz - 1.3 - 0.5 - s 0.26 - s fSCL SCL clock frequency tLOW Low period of the SCL clock 4.7 tHIGH High Period of the SCL clock 4 tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 ns tf Fall time of both SDA and SCL signals - 300 - 300 - 120 ns Data hold time 0 - 0 - 0 - s - 0.9(2) - 0.45(2) s tHD;DAT 0.6 tVD;DAT Data valid time - 3.45(2) tVD;ACK Data valid acknowledge time - 3.45(2) - 0.9(2) - 0.45(2) s tSU;DAT Data setup time 250 - 100 - 50 - ns tHD:STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - s tSU:STA Set-up time for a repeated START condition 4.7 - 0.6 - 0.26 tSU:STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - s Bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - s tBUF s Cb Capacitive load for each bus line - 400 - 400 - 550 pF tSP Pulse width of spikes that are suppressed by the analog filter for Standard and Fast mode 0 50(3) 0 50(3) - - ns DS9118 Rev 14 95/149 125 Electrical characteristics STM32F303xB STM32F303xC 1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when I2Cx_TIMING register is correctly programmed (Refer to the RM0316 reference manual). 2. The maximum tHD;DAT could be 3.45 s, 0.9 s and 0.45 s for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. 3. The minimum width of the spikes filtered by the analog filter is above tSP(max). Table 62. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit 50 260 ns Pulse width of spikes that are suppressed by the analog filter tAF 1. Guaranteed by design. Figure 25. I2C bus AC waveforms and measurement circuit VDD_I2C VDD_I2C Rp MCU Rp Rs SDA I2C bus Rs SCL tf SDA t SU;DAT tr 70% 30% 70% 30% tf t HD;DAT 70% 30% 70% 30% SCL t HD;STA S continued tr t VD;DAT t HIGH 70% 30% 70% 30% continued t LOW 1 / fSCL 9th clock t BUF 1st clock cycle SDA t SU;STA t HD;STA t SP t VD;ACK t SU;STO SCL Sr 9th clock P S MS19879V3 1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply. 96/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 63. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Master mode, SPI1 2.7<VDD<3.6 24 Slave mode, SPI1 2.7<VDD<3.6 24 Master mode, SPI1/2/3 2<VDD<3.6 - - Slave mode MHz 18 30 50 70 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 5.5 - - Slave mode 6.5 - - Master mode 5 - - Slave mode 5 - - tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time ta(SO) Data output access time Slave mode 0 - 4*Tpclk tdis(SO) Data output disable time Slave mode 0 - 24 Slave mode - 12 27 Slave mode, SPI1 2.7<VDD<3.6V - 12 18 Master mode - 1.5 3 Slave mode 11 - - Master mode 0 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time Unit 18 Slave mode, SPI1/2/3 2<VDD<3.6 DuCy(SCK) Duty cycle of SPI clock frequency Max % ns 1. Guaranteed by characterization results. DS9118 Rev 14 97/149 125 Electrical characteristics STM32F303xB STM32F303xC Figure 26. SPI timing diagram - slave mode and CPHA = 0 Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT BIT6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT th(NSS) tc(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 98/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Figure 28. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. DS9118 Rev 14 99/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 64. I2S characteristics(1) Symbol Parameter Conditions Min Max fCK 1/tc(CK) I2S clock frequency Master data: 16 bits, audio freq=48 kHz 1.496 1.503 Slave 0 12.288 - 8 2 tr(CK) tf(CK) I S clock rise and fall time Capacitive load CL = 30 pF tw(CKH) I2S clock high time 331 - tw(CKL) I2S clock low time Master fPCLK= 36 MHz, audio frequency = 48 kHz 332 - tv(WS) WS valid time Master mode 4 - th(WS) WS hold time Master mode 4 - tsu(WS) WS setup time Slave mode 4 - WS hold time Slave mode 0 - slave input clock duty cycle Slave mode 30 70 th(WS) Duty Cycle 2S I tsu(SD_MR) Data input setup time Master receiver 9 - tsu(SD_SR) Data input setup time Slave receiver 2 - Master receiver 0 - Slave receiver 0 - th(SD_MR) th(SD_SR) Data input hold time tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 29 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 12 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) - 3 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2 - 1. Guaranteed by characterization results. 100/149 DS9118 Rev 14 Unit MHz ns % ns STM32F303xB STM32F303xC Electrical characteristics Figure 29. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 30. I2S master timing diagram (Philips protocol)(1) 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS9118 Rev 14 101/149 125 Electrical characteristics STM32F303xB STM32F303xC USB characteristics Table 65. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 s 1. Guaranteed by design. Table 66. USB DC electrical characteristics Symbol Conditions Min.(1) Max.(1) Unit - 3.0(3) 3.6 V I(USB_DP, USB_DM) 0.2 - Parameter Input levels USB operating voltage(2) VDD VDI(4) Differential input sensitivity VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold - 1.3 2.0 V Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) - 0.3 VOH Static output level high RL of 15 k to VSS(5) 2.8 3.6 V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F303xB/STM32F303xC USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design. 5. RL is the load connected on the USB drivers. Figure 31. USB timings: definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b 102/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 67. USB: Full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF 4 - 20 ns CL = 50 pF 4 - 20 ns tr/tf 90 - 110 % - 1.3 - 2.0 V driving high and low 28 40 44 Driver characteristics tr tf trfm VCRS Rise time(2) Fall time (2) Rise/ fall time matching Output signal crossover voltage Output driver Z Impedance(3) DRV 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is already included in the embedded driver. CAN (controller area network) interface Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). DS9118 Rev 14 103/149 125 ADC characteristics Unless otherwise specified, the parameters given in Table 68 to Table 70 are guaranteed by design, with conditions summarized in Table 24. Table 68. ADC characteristics Symbol VDDA IDDA Parameter Analog supply voltage for ADC ADC current consumption on VDDA pin (see Figure 32) DS9118 Rev 14 Conditions Min Typ Max Unit - 2 - 3.6 V Single-ended mode, 5 MSPS - 907 1033.0 Single-ended mode, 1 MSPS - 194 285.5 Single-ended mode, 200 KSPS - 51.5 70 Differential mode, 5 MSPS - 887.5 1009 Differential mode, 1 MSPS - 212 285 Differential mode, 200 KSPS - 51 69.5 A Positive reference voltage - 2 - VDDA VREF- Negative reference voltage - - 0 - Single-ended mode, 5 MSPS - 104 139 Single-ended mode, 1 MSPS - 20.4 37 Single-ended mode, 200 KSPS - 3.3 11.3 Differential mode, 5 MSPS - 174 235 Differential mode, 1 MSPS - 34.6 52.6 Differential mode, 200 KSPS - 6 13.6 IREF V A STM32F303xB STM32F303xC VREF+ ADC current consumption on VREF+ pin (see Figure 33) Electrical characteristics 104/149 6.3.18 Symbol fADC fS(1) fTRIG(1) DS9118 Rev 14 VAIN Parameter ADC clock frequency Sampling rate External trigger frequency Conversion voltage range(2) Conditions Min Typ Max Unit - 0.14 - 72 MHz Resolution = 12 bits, Fast Channel 0.01 - 5.14 Resolution = 10 bits, Fast Channel 0.012 - 6 Resolution = 8 bits, Fast Channel 0.014 - 7.2 Resolution = 6 bits, Fast Channel 0.0175 - 9 fADC = 72 MHz Resolution = 12 bits - - 5.14 MHz Resolution = 12 bits - - 14 1/fADC - 0 - VREF+ V MSPS External input impedance - - - 100 k (1) Internal sample and hold capacitor - - 5 - pF tSTAB(1) Power-up time - 1 conversion cycle tCAL(1) Calibration time fADC = 72 MHz 1.56 s - 112 1/fADC tlatr(1) Trigger conversion latency Regular and injected channels without conversion abort RAIN CADC tlatrinj(1) Trigger conversion latency Injected channels aborting a regular conversion 105/149 CKMODE = 00 1.5 2 2.5 1/fADC CKMODE = 01 - - 2 1/fADC CKMODE = 10 - - 2.25 1/fADC CKMODE = 11 - - 2.125 1/fADC CKMODE = 00 2.5 3 3.5 1/fADC CKMODE = 01 - - 3 1/fADC CKMODE = 10 - - 3.25 1/fADC CKMODE = 11 - - 3.125 1/fADC Electrical characteristics (1) STM32F303xB STM32F303xC Table 68. ADC characteristics (continued) Symbol tS(1) TADCVREG_STUP(1) tCONV(1) CMIR(1) Parameter Sampling time ADC Voltage Regulator Start-up time Total conversion time (including sampling time) Common Mode Input signal Range Conditions Min Typ Max Unit fADC = 72 MHz 0.021 - 8.35 s - 1.5 - 601.5 1/fADC - - - 10 s fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 s Resolution = 12 bits ADC differential mode 14 to 614 (tS for sampling + 12.5 for successive approximation) (VSSA+VREF+)/2 -10% (VSSA+VREF+)/2 (VSSA+VREF+)/2 + 10% 1/fADC Electrical characteristics 106/149 Table 68. ADC characteristics (continued) V 1. Data guaranteed by design. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. DS9118 Rev 14 STM32F303xB STM32F303xC STM32F303xB STM32F303xC Electrical characteristics Figure 32. ADC typical current consumption on VDDA pin 1000 ADC current consumption (A) 900 800 700 Single-ended mode 600 Differential mode 500 400 300 200 100 0 5 1 0.2 Clock frequency (MSPS) MS36607V1 Figure 33. ADC typical current consumption on VREF+ pin 200 ADC current consumption (A) 180 Single-ended mode 160 Differential mode 140 120 100 80 60 40 20 0 5 1 0.2 Clock frequency (MSPS) MS36606V1 DS9118 Rev 14 107/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 69. Maximum ADC RAIN (1) Resolution 12 bits 10 bits 8 bits 6 bits RAIN max (k) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.018 NA NA 2.5 34.72 0.150 NA 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 1.5 20.83 0.082 NA NA 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 1.5 20.83 0.150 NA 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. Guaranteed by characterization results. 2. All fast channels, expect channels on PA2, PA6, PB1, PB12. 108/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics 3. Channels available on PA2, PA6, PB1, PB12. Table 70. ADC accuracy - limited test conditions, 100-pin packages (1)(2) Symbol Parameter ET Total unadjusted error Single ended Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error Integral linearity error Effective ENOB(4) number of bits Signal-tonoise and (4) SINAD distortion ratio Min Conditions ADC clock freq. 72 MHz Sampling freq. 5 Msps VDDA = VREF+ = 3.3 V 25C 100-pin package Single ended Differential Single ended Differential Single ended Differential Single ended Differential DS9118 Rev 14 (3) Typ Max (3) Unit 3.5 4.5 Fast channel 5.1 Ms - Slow channel 4.8 Ms - 4 4.5 Fast channel 5.1 Ms - 3 3 Slow channel 4.8 Ms - 3 3 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 2.5 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms - 3 4 Slow channel 4.8 Ms - 3.5 4 Fast channel 5.1 Ms - 1.5 2.5 Slow channel 4.8 Ms - 2 2.5 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 1.5 3 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms 10.7 10.8 - Slow channel 4.8 Ms 10.7 10.8 - Fast channel 5.1 Ms 11.2 11.3 - Slow channel 4.8 Ms 11.1 11.3 - Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - LSB bits dB 109/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 70. ADC accuracy - limited test conditions, 100-pin packages (1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. 72 MHz Sampling freq 5 Msps VDDA = VREF+ = 3.3 V 25C 100-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.1 Ms - -76 -76 Slow channel 4.8 Ms - -76 -76 Fast channel 5.1 Ms - -80 -80 Slow channel 4.8 Ms - -80 -80 (3) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Guaranteed by characterization results. 4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. 110/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 71. ADC accuracy, 100-pin packages(1)(2)(3) Symbol Parameter ET Single Ended Total unadjusted error Differential Single Ended EO Offset error Differential Single Ended EG ED EL ENOB (5) Gain error Differential linearity error Integral linearity error Effective number of bits Min (4) Max(4) Fast channel 5.1 Ms - 6.5 Slow channel 4.8 Ms - 6.5 Fast channel 5.1 Ms - 4 Slow channel 4.8 Ms - 4 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2 Fast channel 5.1 Ms - 6 Slow channel 4.8 Ms - 6 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2 Fast channel 5.1 Ms 10.4 - Slow channel 4.8 Ms 10.2 - Fast channel 5.1 Ms 10.8 - Slow channel 4.8 Ms 10.8 - Conditions ADC clock freq. 72 MHz, Sampling freq. 5 Msps 2 V VDDA , VREF+ 3.6 V 100-pin package Differential Single Ended Differential Single Ended Differential Single Ended Differential DS9118 Rev 14 Unit LSB bits 111/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 71. ADC accuracy, 100-pin packages(1)(2)(3) (continued) Symbol Parameter Single Ended Signal-toSINAD noise and (5) distortion ratio SNR(5) Signal-tonoise ratio Min (4) Max(4) Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -74 Slow channel 4.8 Ms - -74 Fast channel 5.1 Ms - -78 Slow channel 4.8 Ms - -76 Conditions Differential ADC clock freq. 72 MHz, Sampling freq. 5 Msps, 2 V VDDA, VREF+ 3.6 V 100-pin package Total THD(5) harmonic distortion Single Ended Differential Single Ended Differential Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Guaranteed by characterization results. 5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. 112/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 72. ADC accuracy - limited test conditions, 64-pin packages(1)(2) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (4) SINAD (4) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min Conditions ADC clock freq. 72 MHz Sampling freq. 5 Msps VDDA = 3.3 V 25C 64-pin package Single ended Differential Single ended Differential Single ended Differential Single ended Differential DS9118 Rev 14 Max (3) Typ Fast channel 5.1 Ms - 4 4.5 Slow channel 4.8 Ms - 5.5 6 Fast channel 5.1 Ms - 3.5 4 Slow channel 4.8 Ms - 3.5 4 Fast channel 5.1 Ms - 2 2 Slow channel 4.8 Ms - 1.5 2 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 1.5 2 Fast channel 5.1 Ms - 3 4 Slow channel 4.8 Ms - 5 5.5 Fast channel 5.1 Ms - 3 3 Slow channel 4.8 Ms - 3 3.5 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 2 3 Fast channel 5.1 Ms - 1.5 1.5 Slow channel 4.8 Ms - 1.5 (3) Unit LSB 2 Fast channel 5.1 Ms 10.8 10.8 - Slow channel 4.8 Ms 10.8 10.8 - Fast channel 5.1 Ms 11.2 11.3 - Slow channel 4.8 Ms 11.2 11.3 - Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - bit dB 113/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 72. ADC accuracy - limited test conditions, 64-pin packages(1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. 72 MHz Sampling freq 5 Msps VDDA = 3.3 V 25C 64-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.1 Ms - -80 -80 Slow channel 4.8 Ms - -78 -77 Fast channel 5.1 Ms - -83 -82 Slow channel 4.8 Ms - -81 -80 (3) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Guaranteed by characterization results. 4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. 114/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 73. ADC accuracy, 64-pin packages(1)(2)(3) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (5) SINAD (5) Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min(4) Max Fast channel 5.1 Ms - 6.5 Slow channel 4.8 Ms - 6.5 Fast channel 5.1 Ms - 4 Slow channel 4.8 Ms - 4.5 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2.5 Slow channel 4.8 Ms - 2.5 Fast channel 5.1 Ms - 6 Slow channel 4.8 Ms - 6 Fast channel 5.1 Ms - 3.5 Slow channel 4.8 Ms - 4 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3.5 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2.5 Fast channel 5.1 Ms 10.4 - Slow channel 4.8 Ms 10.4 - Fast channel 5.1 Ms 10.8 - Slow channel 4.8 Ms 10.8 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Conditions ADC clock freq. 72 MHz, Sampling freq. 5 Msps 2.0 V VDDA 3.6 V 64-pin package Single ended Differential Single ended Differential Single ended Differential Single ended Differential DS9118 Rev 14 (4) Unit LSB bits dB 115/149 125 Electrical characteristics STM32F303xB STM32F303xC Table 73. ADC accuracy, 64-pin packages(1)(2)(3) (continued) Symbol Parameter Single ended SNR(5) THD(5) Signal-tonoise ratio Total harmonic distortion Min(4) Max Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -75 Slow channel 4.8 Ms - -75 Fast channel 5.1 Ms - -79 Slow channel 4.8 Ms - -78 Conditions ADC clock freq. 72 MHz, Sampling freq 5 Msps, 2 V VDDA 3.6 V 64-pin package Differential Single ended Differential (4) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Guaranteed by characterization results. 5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. Table 74. ADC accuracy at 1MSPS(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(3) Fast channel 2.5 5 Slow channel 3.5 5 Fast channel 1 2.5 1.5 2.5 2 3 Test conditions Slow channel ADC Freq 72 MHz Fast channel Sampling Freq 1MSPS 2.4 V VDDA = VREF+ 3.6 V Slow channel Single-ended mode Fast channel 3 4 0.7 2 Slow channel 0.7 2 Fast channel 1 3 Slow channel 1.2 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC accuracy. 3. Guaranteed by characterization results. 116/149 DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Figure 34. ADC accuracy characteristics [1LSB IDEAL = VDDA VREF+ (or 4096 4096 depending on package) EG 4095 4094 (1) Example of an actu al transfe r curve (2) The ideal transfer cu rve (3) End point correlation line 4093 ET = Total unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the last actual one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end-point correlation line. (2) ET (3) 7 (1) 6 5 EO EL 4 3 ED 2 1 LSB IDEAL 1 0 VSSA 1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395e Figure 35. Typical connection diagram using the ADC VDD Sample and hold ADC converter VT 0.6 V RAIN (1) VAIN RADC AINx VT 0.6 V Cparasitic 12-bit converter IL 1 A CADC MS19881V3 1. Refer to Table 68 for the values of RAIN. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 11. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. DS9118 Rev 14 117/149 125 Electrical characteristics 6.3.19 STM32F303xB STM32F303xC DAC electrical specifications Table 75. DAC characteristics Symbol VDDA RLOAD(1) RO(1) CLOAD (1) VDAC_OUT (1) IDDA(3) Parameter Conditions Min Typ Max Unit - 2.4 - 3.6 V Resistive load DAC output Connected to VSSA buffer ON Connected to V DDA 5 - - 25 - - Output impedance DAC output buffer OFF - - 15 k Capacitive load DAC output buffer ON - - 50 pF 0.2 - VDDA - 0.2 V DAC output buffer OFF - 0.5 VDDA - 1LSB mV With no load, middle code (0x800) on the input. - - 380 A With no load, worst code (0xF1C) on the input. - - 480 A Given for a 10-bit input code - - 0.5 LSB Analog supply voltage Voltage on DAC_OUT output DAC DC current consumption in quiescent mode (Standby mode)(2) Corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC output buffer ON. k DNL(3) Differential non linearity Difference between two consecutive code-1LSB) Given for a 12-bit input code - - 2 LSB - - 1 LSB INL(3) Integral non linearity Given for a 10-bit input code (difference between measured value at Code i and the value at Code i on a Given for a 12-bit input code line drawn between Code 0 and last Code 4095) - - 4 LSB Offset error (difference Given for a 10-bit input code at between measured value at VDDA = 3.6 V Code (0x800) and the ideal value = VDDA/2) Given for a 12-bit input code at VDDA = 3.6 V - - 10 mV - - 3 LSB - - 12 LSB - - 0.5 % Settling time (full scale: for a 12-bit input code transition between the lowest and the CLOAD 50 pF, tSETTLING(3) highest input codes when RLOAD 5 k DAC_OUT reaches final value 1LSB - 3 4 s Max frequency for a correct CLOAD 50 pF, DAC_OUT change when small variation in the input RLOAD 5 k code (from code i to i+1LSB) - - 1 MS/s Offset(3) Gain error(3) Gain error Update rate(3) 118/149 Given for a 12-bit input code DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 75. DAC characteristics (continued) Symbol Parameter Conditions Wakeup time from off state tWAKEUP(3) (Setting the ENx bit in the DAC Control register) CLOAD 50 pF, RLOAD 5 k Power supply rejection ratio C LOAD = 50 pF, PSRR+ (1) (to VDDA) (static DC No RLOAD 5 k, measurement Min Typ Max Unit - 6.5 10 s - -67 -40 dB 1. Guaranteed by design. 2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved. 3. Guaranteed by characterization results. Figure 36. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DS9118 Rev 14 119/149 125 Electrical characteristics 6.3.20 STM32F303xB STM32F303xC Comparator characteristics Table 76. Comparator characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 2 - 3.6 VIN Comparator input voltage range - 0 - VDDA VBG Scaler input voltage - - 1.2 - VSC Scaler offset voltage - - 5 10 mV tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - 1(2) s Next activations - - 0.2 ms Startup time to reach propagation delay specification - - 60 s Ultra-low-power mode - 2 4.5 - 0.7 1.5 - 0.3 0.6 - 50 100 - 100 240 Ultra-low-power mode - 2 7 Low-power mode - 0.7 2.1 Medium power mode - 0.3 1.2 - 90 180 - 110 300 VDDA tSTART Parameter Comparator startup time Low-power mode Propagation delay for 200 mV step with 100 mV Medium power mode overdrive VDDA 2.7 V High speed mode tD Propagation delay for full range step with 100 mV overdrive VDDA < 2.7 V VDDA 2.7 V High speed mode VDDA < 2.7 V Unit V s ns s ns Voffset Comparator offset error - - 4 10 mV dVoffset/dT Offset error temperature coefficient - - 18 - V/ C Ultra-low-power mode - 1.2 1.5 Low-power mode - 3 5 Medium power mode - 10 15 High speed mode - 75 100 IDD(COMP) 120/149 COMP current consumption DS9118 Rev 14 A STM32F303xB STM32F303xC Electrical characteristics Table 76. Comparator characteristics(1) (continued) Symbol Parameter Conditions No hysteresis (COMPxHYST[1:0]=00) Vhys Comparator hysteresis - Min Typ Max - 0 - High speed mode Low hysteresis (COMPxHYST[1:0]=01) All other power modes 3 High speed mode Medium hysteresis (COMPxHYST[1:0]=10) All other power modes 7 High speed mode High hysteresis (COMPxHYST[1:0]=11) All other power modes 18 5 9 19 Unit 13 8 10 26 15 mV 19 49 31 40 1. Data guaranteed by design. 2. For more details and conditions, see Figure 37 Maximum VREFINT scaler startup time from power down. Figure 37. Maximum VREFINT scaler startup time from power down MS36682V1 DS9118 Rev 14 121/149 125 Electrical characteristics 6.3.21 STM32F303xB STM32F303xC Operational amplifier characteristics Table 77. Operational amplifier characteristics(1) Symbol Parameter Condition Min Typ Max Unit VDDA Analog supply voltage - 2.4 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25C, No Load on output. - - 4 All voltage/Temp. - - 6 25C, No Load on output. - - 1.6 All voltage/Temp. - - 3 Maximum calibration range VIOFFSET Input offset voltage After offset calibration VIOFFSET mV Input offset voltage drift - - 5 - V/C ILOAD Drive current - - - 500 A IDDOPAMP Consumption No load, quiescent mode - 690 1450 A ADC sampling time when reading the OPAMP output. - 400 - - ns CMRR Common mode rejection ratio - - 90 - dB PSRR Power supply rejection ratio 73 117 - dB GBW Bandwidth - - 8.2 - MHz SR Slew rate - - 4.7 - V/s RLOAD Resistive load - 4 - - k CLOAD Capacitive load - - - 50 pF Rload = min, Input at VDDA. VDDA -100 - - Rload = 20K, Input at VDDA. VDDA -20 - - TS_OPAMP_VOUT VOHSAT VOLSAT m tOFFTRIM tWAKEUP 122/149 High saturation voltage(2) High saturation voltage(2) DC mV Rload = min, input at 0V - - 100 Rload = 20K, input at 0V. - - 20 Phase margin - - 62 - Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - - - 2 ms - 2.8 5 s Wake up time from OFF state. CLOAD 50 pf, RLOAD 4 k, Follower configuration DS9118 Rev 14 STM32F303xB STM32F303xC Electrical characteristics Table 77. Operational amplifier characteristics(1) (continued) Symbol PGA gain Rnetwork Parameter Condition Min Typ Max Unit - 2 - - - 4 - - - 8 - - - 16 - - Gain=2 - 5.4/5.4 - R2/R1 internal resistance values in Gain=4 PGA mode (3) Gain=8 - 16.2/5.4 - - 37.8/5.4 - - 40.5/2.7 - Non inverting gain value - Gain=16 PGA gain error Ibias PGA BW en PGA gain error - -1% - 1% OPAMP input bias current - - - 0.2(4) PGA Gain = 2, Cload = 50pF, Rload = 4 K - 4 - PGA Gain = 4, Cload = 50pF, Rload = 4 K - 2 - PGA Gain = 8, Cload = 50pF, Rload = 4 K - 1 - PGA Gain = 16, Cload = 50pF, Rload = 4 K - 0.5 - @ 1KHz, Output loaded with 4 K - 109 - PGA bandwidth for different non inverting gain Voltage noise density @ 10KHz, Output loaded with 4 K k A MHz - 43 - nV ----------Hz 1. Guaranteed by design. 2. The saturation voltage can be also limited by the Iload (drive current). 3. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between OPAMP inverting input and ground. The PGA gain =1+R2/R1 4. Mostly TTa I/O leakage, when used in analog mode. DS9118 Rev 14 123/149 125 Electrical characteristics STM32F303xB STM32F303xC Figure 38. OPAMP voltage noise versus frequency 6.3.22 Temperature sensor characteristics Table 78. TS characteristics Symbol TL(1) Avg_Slope(1) V25 tSTART(1) TS_temp(1)(2) Parameter Min Typ Max Unit - 1 2 C Average slope 4.0 4.3 4.6 mV/C Voltage at 25 C 1.34 1.43 1.52 V 4 - 10 s 2.2 - - s VSENSE linearity with temperature Startup time ADC sampling time when reading the temperature 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. Table 79. Temperature sensor calibration values Calibration value name 124/149 Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at temperature of 110 C VDDA= 3.3 V 0x1FFF F7C2 - 0x1FFF F7C3 DS9118 Rev 14 STM32F303xB STM32F303xC 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 80. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit K R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1mV accuracy 2.2 - - s Er(1) TS_vbat(1)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. DS9118 Rev 14 125/149 125 Package information 7 STM32F303xB STM32F303xC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 LQFP100 - 14 x 14 mm, low-profile quad flat package information Figure 39. LQFP100 - 14 x 14 mm, low-profile quad flat package outline 0.25 mm c A1 A A2 SEATING PLANE C GAUGE PLANE D L D1 A1 K ccc C L1 D3 51 75 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 76 25 e 1L_ME_V5 1. Drawing is not to scale. Table 81. LQPF100 - 14 x 14 mm, low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.063 A1 0.05 - 0.15 0.002 - 0.0059 126/149 DS9118 Rev 14 STM32F303xB STM32F303xC Package information Table 81. LQPF100 - 14 x 14 mm, low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.2 0.0035 - 0.0079 D 15.80 16.00 16.2 0.622 0.6299 0.6378 D1 13.80 14.00 14.2 0.5433 0.5512 0.5591 D3 - 12.00 - - 0.4724 - E 15.80 16.00 16.2 0.622 0.6299 0.6378 E1 13.80 14.00 14.2 0.5433 0.5512 0.5591 E3 - 12.00 - - 0.4724 - e - 0.50 - - 0.0197 - L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - K 0 3.5 7 0 3.5 7 ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 40. LQFP100 - 14 x 14 mm, low-profile quad flat package recommended footprint 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are in millimeters. DS9118 Rev 14 127/149 142 Package information STM32F303xB STM32F303xC LQFP100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 41. LQFP100 - 14 x 14 mm, low-profile quad flat package top view example Product identification(1) STM32F303 VCT6 R Revision code Date code Y WW Pin 1 indentifier MSv36501V2 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 128/149 DS9118 Rev 14 STM32F303xB STM32F303xC LQFP64 - 10 x 10 mm, low-profile quad flat package information Figure 42. LQFP64 - 10 x 10 mm, low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A SEATING PLANE C A2 A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 b E3 7.2 Package information 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 82. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1 0.05 - 0.15 0.0020 - 0.0059 A2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 D - 12.00 - - 0.4724 - D1 - 10.00 - - 0.3937 - D3 - 7.50 - - 0.2953 - E - 12.00 - - 0.4724 - DS9118 Rev 14 0.0079 129/149 142 Package information STM32F303xB STM32F303xC Table 82. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 - 10.00 - - 0.3937 - E3 - 7.50 - - 0.2953 - e - 0.50 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 43. LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are in millimeters. 130/149 DS9118 Rev 14 STM32F303xB STM32F303xC Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 44. LQFP64 - 10 x 10 mm, low-profile quad flat package top view example Revision code Product identification(1) R STM32F303 RCT6 Date code Y WW Pin 1 indentifier MSv36502V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS9118 Rev 14 131/149 142 Package information 7.3 STM32F303xB STM32F303xC LQFP48 - 7 x 7 mm, low-profile quad flat package information Figure 45. LQFP48 - 7 x 7 mm, low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 E E1 E3 b 13 PIN 1 IDENTIFICATION 1 12 e 5B_ME_V2 1. Drawing is not to scale. Table 83. LQFP48 - 7 x 7 mm, low-profile quad flat package mechanical data Symbol 132/149 inches(1) millimeters Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1 0.05 - 0.15 0.0020 - 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 - 0.0079 D 8.80 9.00 9.20 0.3465 0.3543 0.3622 D1 6.80 7.00 7.20 0.2677 0.2756 0.2835 D3 - 5.50 - - 0.2165 - E 8.80 9.00 9.20 0.3465 0.3543 0.3622 DS9118 Rev 14 STM32F303xB STM32F303xC Package information Table 83. LQFP48 - 7 x 7 mm, low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max E1 6.80 7.00 7.20 0.2677 0.2756 0.2835 E3 - 5.50 - - 0.2165 - e - 0.50 - - 0.0197 - L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - K 0 3.5 7 0 3.5 7 ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint 0.50 1.20 9.70 0.30 25 36 37 24 0.20 7.30 5.80 7.30 48 13 12 1 1.20 5.80 9.70 ai14911d 1. Dimensions are in millimeters. DS9118 Rev 14 133/149 142 Package information STM32F303xB STM32F303xC LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example Product identification (1) STM32F303 CCT6 Date code Y WW Pin 1 identification Revision code R MS36605V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 134/149 DS9118 Rev 14 STM32F303xB STM32F303xC 7.4 Package information WLCSP100 - 0.4 mm pitch wafer level chip scale package information Figure 48. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package outline A1 BALL LOCATION A DETAIL A K BOTTOM VIEW SIDE VIEW FRONT VIEW DETAIL A ROTATED 90 A1 ORIENTATION REFERENCE aaa (4X) TOP VIEW WAFER BACK SIDE WLCSP100L_A01Q_ME_V1 1. Drawing is not to scale. DS9118 Rev 14 135/149 142 Package information STM32F303xB STM32F303xC Table 84. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Typ Min Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.17 - - 0.0067 - A2 - 0.38 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Ob 0.22 0.25 0.28 - 0.0098 0.0110 D 4.166 4.201 4.236 - 0.1654 0.1668 E 4.628 4.663 4.698 - 0.1836 0.1850 e - 0.4 - - 0.0157 - e1 - 3.6 - - 0.1417 - e2 - 3.6 - - 0.1417 - F - 0.3005 - - 0.0118 - G - 0.5315 - - 0.0209 - N - 100 - - 3.9370 - aaa - 0.1 - - 0.0039 - bbb - 0.1 - - 0.0039 - ccc - 0.1 - - 0.0039 - ddd - 0.05 - - 0.0020 - eee - 0.05 - - 0.0020 - A3 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 136/149 DS9118 Rev 14 STM32F303xB STM32F303xC Package information Figure 49. WLCSP100 - 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint Dpad Dsm WLCSP100L_A01Q_FP_V1 Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.1 mm DS9118 Rev 14 137/149 142 Package information STM32F303xB STM32F303xC WLCSP100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package top view example Ball A1 identifier Product identification(1) 32F303VC6 Revision code Y WW R MSv40444V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 138/149 DS9118 Rev 14 STM32F303xB STM32F303xC 7.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions on page 60. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 86. Package thermal characteristics Symbol JA 7.5.1 Parameter Value Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm 55 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 41 Thermal resistance junction-ambient WLCSP100 - 0.4 mm pitch 40 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org DS9118 Rev 14 139/149 142 Package information 7.5.2 STM32F303xB STM32F303xC Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F303xB/STM32F303xC at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 3 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 2 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 3 x 8 mA x 0.4 V + 2 x 20 mA x 1.3 V = 61.6 mW This gives: PINTmax = 175 mW and PIOmax = 61.6 mW: PDmax = 175 + 61.6 = 236.6 mW Thus: PDmax = 236.6 mW Using the values obtained in Table 86 TJmax is calculated as follows: - For LQFP64, 45C/W TJmax = 82 C + (45C/W x 236.6 mW) = 82 C + 10.65 C = 92.65 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Ordering information). 140/149 DS9118 Rev 14 STM32F303xB STM32F303xC Package information Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 9 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 9 x 8 mA x 0.4 V = 28.8 mW This gives: PINTmax = 70 mW and PIOmax = 28.8 mW: PDmax = 70 + 28.8 = 98.8 mW Thus: PDmax = 98.8 mW Using the values obtained in Table 86 TJmax is calculated as follows: - For LQFP100, 41C/W TJmax = 115 C + (41C/W x 98.8 mW) = 115 C + 4.05 C = 119.05 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information). DS9118 Rev 14 141/149 142 Ordering information 8 STM32F303xB STM32F303xC Ordering information Table 87. Ordering information scheme Example: STM32 F 303 R B T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 303 = STM32F303xx Pin count C = 48 pins R = 64 pins V = 100 pins Flash memory size B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package T = LQFP Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C 7 = Industrial temperature range, -40 to 105 C Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 142/149 DS9118 Rev 14 STM32F303xB STM32F303xC 9 Revision history Revision history Table 88. Document revision history Date Revision Changes 22-Jun-2012 1 Initial release 07-Sep-2012 2 Modified Features on cover page. Modified Table 2: STM32F301xx family device features and peripheral counts Added clock tree to Section 3.9: Clocks and startup Added Table 10: STM32F302xB/STM32F302xC I2C implementation Added Table 11: USART features Added Table 12: STM32F302xB/STM32F302xC SPI/I2S implementation Modified Table 13: Capacitive sensing GPIOs available on STM32F302xB/STM32F302xC devices Modified Figure 7, Figure 8 and Figure 9: STM32F302xB/STM32F302xC LQFP100 pinout Modified Table 16: STM32F302xB/STM32F302xC pin definitions Modified Figure 11: Power supply scheme Modified Table 21: Voltage characteristics Modified Table 22: Current characteristics Modified Table 25: Operating conditions at power-up / power-down Added footnote to Table 31: Typical and maximum current consumption from the VDDA supply Added footnote to Table 35 and Table 36: Typical current consumption in Sleep mode, code running from Flash or RAM Removed table "Switching output I/O current consumption" and table "Peripheral current consumption" Added note under Figure 17: Typical application with a 32.768 kHz crystal Updated Table 44: HSI oscillator characteristics Updated Wakeup time from low-power mode and Table 39: Low-power mode wakeup timings Updated Table 47: Flash memory characteristics Updated Table 52: Electrical sensitivities Updated Table 53: I/O current injection susceptibility Updated Table 54: I/O static characteristics Updated Table 55: Output voltage characteristics Updated Table 57: NRST pin characteristics Updated Table 63: SPI characteristics Updated Table 64: I2S characteristics Corrected LQFP100 in Section 7.2.3: Selecting the product temperature range 21-Sep-2012 3 Updated Table 63: SPI characteristics DS9118 Rev 14 143/149 148 Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 05-Dec-2012 144/149 Revision Changes 4 Updated first page Removed references to VDDSDx and VSSSD Added reference to PM0214 in Section 1 Moved Temp. sensor calibartion values toTable 79 and VREF calibration values to Table 29 Updated Table 3: STM32F303xx family device features and peripheral counts UpdatedSection 3.4: Embedded SRAM Updated Section 3.2: Memory protection unit (MPU) Updated Section 3.24: Universal serial bus (USB) Modified Section 3.26: Touch sensing controller (TSC) Updated heading of Table 11: USART features Updated Table 16: STM32F302xB/STM32F302xC pin definitions Added notes to PC13, PC14 and PC15 in Table 16: STM32F302xB/STM32F302xC pin definitions Updated Figure 11: Power supply scheme Modified Table 21: Voltage characteristics Modified Table 22: Current characteristics Modified Table 24: General operating conditions Modified Figure 13: Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = '00') Updated Section 6.3.14: I/O port characteristics Updated Table 30: Typical and maximum current consumption from VDD supply at VDD = 3.6V and Table 31: Typical and maximum current consumption from the VDDA supply Updated Table 32: Typical and maximum VDD consumption in Stop and Standby modes and Table 33: Typical and maximum VDDA consumption in Stop and Standby modes Updated Table 34: Typical and maximum current consumption from VBAT supply Added Figure 13: Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = '00') Updated Table 35: Typical current consumption in Run mode, code with data processing running from Flash and Table 36: Typical current consumption in Sleep mode, code running from Flash or RAM Added Table 38: Peripheral current consumption Added Table 37: Switching output I/O current consumption Updated Section 6.3.6: Wakeup time from low-power mode Modified ESD absolute maximum ratings Modified Table 55: Output voltage characteristics Updated EMI characteristics Updated Table 56: I/O AC characteristics Updated Table 53: I/O current injection susceptibility Updated Table 58: TIMx characteristics Updated Section 7.4: WLCSP100 - 0.4 mm pitch wafer level chip scale package information Added Table 69: Maximum ADC RAIN Added Table 70: ADC accuracy - limited test conditions, 100-pin packages Updated Table 64: ADC accuracy - limited test conditions 2) Updated Table 75: DAC characteristics Updated Table 77: Operational amplifier characteristics Updated figures and tables in Section 7: Package information DS9118 Rev 14 STM32F303xB STM32F303xC Revision history Table 88. Document revision history (continued) Date 08-Jan-2013 24-Jun-2013 13-Nov-2013 Revision Changes 5 Updated Vhys and Ilkg in Table 54: I/O static characteristics. Updated VIL(NRST), VIH(NRST), and VNF(NRST) in Table 57: NRST pin characteristics. Updated Table 70: ADC accuracy - limited test conditions, 100-pin packages and Table 64: ADC accuracy - limited test conditions 2). 6 Replaced Cortex-M4F with Cortex M4 with FPU Updated Core, Memories and SPI bullet points in Features Removed 8KB CCM SRAM from STM32F302xx devices, updated Figure 2: STM32F303xB/STM32F303xC block diagram and Table 3: STM32F303xx family device features and peripheral counts Updated Section 3.4: Embedded SRAM Added VREF+ in Section 3.14: Digital-to-analog converter (DAC) Removed DMA support for UART5 in Table 11: USART features Added `reference clock detection' bullet in Section 3.18: Real-time clock (RTC) and backup registers Added paragraph `The touch sensing controller is fully...' in Section 3.26: Touch sensing controller (TSC) Updated Comparison of I2C analog and digital filters Updated Section 3.10: General-purpose input/outputs (GPIOs) Added `EVENTOUT' in Table 16: STM32F302xB/STM32F302xC pin definitions and added note to `VREF+' pin Updated IVDD in Table 22: Current characteristics and Output driving current Updated Table 61: I2C timings specification (see I2C specification, rev.03, June 2007) and Figure 25: I2C bus AC waveforms and measurement circuit Added VREF+ row to Table 68: ADC characteristics, replaced VDDA with VREF+, updated tconv and added note to `conversion voltage range Added VREF+ row to Table 75: DAC characteristics and replaced VDDA with VREF+ Added `PGA BW' and `en' in Table 77: Operational amplifier characteristics 7 Removed STM32F302xB/STM32F302xC products (now in a separate datasheet). Added I2S feature for SPI2 and SPI3 Added tSP to Table 61: I2C timings specification (see I2C specification, rev.03, June 2007). Renamed tSP to tAN inTable 62: I2C analog filter characteristics. Added tSTAB in Table 68: ADC characteristics Renamed VOPAMPx to VREFOPAMPx Updated Table 71: ADC accuracy, 100-pin packages. Updated ADC channel names in Section 3.13.1, Section 3.13.2 and Section 3.13.3. DS9118 Rev 14 145/149 148 Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 18-Apr-2014 09-Dec-2014 29-Jan-2015 146/149 Revision Changes 8 Updated Table 50: EMI characteristics conditions :3.3v replaced by 3.6V. 2 Updated Section 6.3.17: Communications interfaces I C interface. Updated Table 77: Operational amplifier characteristics adding TS_OPAMP_VOUT row. Updated Section 3.13: Fast analog-to-digital converter (ADC). updated Arm and Cortex trademark. Updated Table 32: Typical and maximum VDD consumption in Stop and Standby modes with Max value at 85C and 105C. Updated Table 70: ADC accuracy - limited test conditions, 100-pin packages and Table 71: ADC accuracy, 100-pin packages for 100-pin package. Added Table 72: ADC accuracy - limited test conditions, 64-pin packages and Table 73: ADC accuracy, 64-pin packagesfor 64-pin package. Added Table 74: ADC accuracy at 1MSPS for 1MSPS sampling frequency. Updated Table 63: SPI characteristics. Updated Table 75: DAC characteristics. 9 Updated core description in cover page. Updated HSI characteristics Table 44: HSI oscillator characteristics and Figure 18: HSI oscillator accuracy characterization results for soldered parts. Updated Table 58: TIMx characteristics. Updated Table 16: STM32F302xB/STM32F302xC pin definitions adding note for I/Os featuring an analog output function (DAC_OUT,OPAMP_OUT). Updated Table 68: ADC characteristics adding IDDA & IREF consumptions. Added Figure 32: ADC typical current consumption on VDDA pin and Figure 33: ADC typical current consumption on VREF+ pin. Added Section 3.8: Interconnect matrix. Updated Figure 5: Clock tree. Added note after Table 32: Typical and maximum VDD consumption in Stop and Standby modes. Updated Section : In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. with new LQFP100, LQFP64, LQFP48 package marking. Updated Table 16: STM32F302xB/STM32F302xC pin definitions and alternate functions tables replacing usart_rts by usart_rts_de. 10 Updated Section 6.3.20: Comparator characteristics modifying ts_sc characteristics in Table 76 and adding Figure 37: Maximum VREFINT scaler startup time from power down. Updated IDD data in Table 42: HSE oscillator characteristics. DS9118 Rev 14 STM32F303xB STM32F303xC Revision history Table 88. Document revision history (continued) Date 17-Apr-2015 11-Dec-2015 Revision Changes 11 Updated Section 7: Package information: with new package information structure adding 1 sub paragraph for each package. Updated Figure 41: LQFP100 - 14 x 14 mm, low-profile quad flat package top view example removing gate mark. Added note for all packages about the device marking orientation: "the following figure gives an example of topside marking orientation versus pin 1 identifier location". Updated Table 82: LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data. 12 Added WLCSP100: - Updated cover page. - Updated Table 2: STM32F303xB/STM32F303xC family device features and peripheral counts. - Added Figure 7: STM32F303xB/STM32F303xC WLCSP100 pinout. - Updated Table 13: STM32F303xB/STM32F303xC pin definitions. - Updated Table 24: General operating conditions. - Added Section 7.4: WLCSP100 - 0.4 mm pitch wafer level chip scale package information. - Updated Table 86: Package thermal characteristics. - Updated Table 87: Ordering information scheme. Updated Figure 4, Figure 5, Figure 6, Table 13 and Table 22 removing all VDD and VSS indexes. Updated all the notes removing `not tested in production'. Updated Table 68: ADC characteristics adding VREF- negative voltage reference. Update Table 21: Voltage characteristics adding table note 4. DS9118 Rev 14 147/149 148 Revision history STM32F303xB STM32F303xC Table 88. Document revision history (continued) Date 06-May-2016 30-Oct-2018 148/149 Revision Changes 13 Updated Table 43: LSE oscillator characteristics (fLSE = 32.768 kHz) LSEDRV[1:0] bits. Updated Table 28: Embedded internal reference voltage VREFINT internal reference voltage (min and typ values). Updated Figure 5: STM32F303xB/STM32F303xC LQFP64 pinout replacing VSS by PF4. Updated Table 51: ESD absolute maximum ratings ESD CDM at class 3 and 4 including WLCSP100 package information. Updated Table 13: STM32F303xB/STM32F303xC pin definitions: - Adding `digital power supply' in the Pin function column at the line corresponding to K8/28/19 pins. - Adding VSS digital ground line with WLCSP100 K9 and K10 pins connected. - Replacing in VDD line for WLCSP100: `A10, B10' by `A9, A10, B10, B8'. Updated Figure 21: Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. Updated Table 77: Operational amplifier characteristics high saturation and low saturation voltages. Updated Table 13: STM32F303xB/STM32F303xC pin definitions adding note `Fast ADC channel' for ADCx_IN1..5. Updated Table 75: DAC characteristics resistive load. Updated Table 68: ADC characteristics adding CMIR parameter and modifying tSTAB parameter characteristics. 14 Updated Table 51: ESD absolute maximum ratings ESD class. Updated cover on 2 pages. Updated Section 1: Introduction with Arm logo. Updated Section 7: Package information adding information: - Other optional marking or inset/upset marks. - The printed markings may differ depending on the supply chain. - Updated note 1 below all the package device marking figures. DS9118 Rev 14 STM32F303xB STM32F303xC IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS9118 Rev 14 149/149 149