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ADS7843-Q1

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TOUCH SCREEN CONTROLLER

Check for Samples: ADS7843-Q1

1FEATURES DESCRIPTION

• Qualified for Automotive Applications The ADS7843-Q1 is a 12-bit sampling Analog-to-

• Ratiometric Conversion Digital Converter (ADC) with a synchronous serial

• Single Supply: 2.7V to 5V interface and low on-resistance switches for driving

touch screens. Typical power dissipation is 750µW at

• Up to 125kHz Conversion Rate a 125kHz throughput rate and a +2.7V supply. The

• Serial Interface reference voltage (VREF) can be varied between 1V

• Programmable 8- or 12-Bit Resolution and +VCC, providing a corresponding input voltage

range of 0V to VREF. The device includes a shutdown

• 2 Auxiliary Analog Inputs mode which reduces typical power dissipation to

• Full Power-Down Control under 0.5µW. The ADS7843-Q1 is specified down to

2.7V operation.

APPLICATIONS Low power, high speed, and onboard switches make

• Personal Digital Assistants the ADS7843-Q1 ideal for battery-operated systems

• Portable Instruments such as personal digital assistants with resistive

touch screens and other portable equipment. The

• Point-of-Sales Terminals ADS7843-Q1 is available in an SSOP-16 package

• Pagers and is specified over the –40°C to +85°C temperature

• Touch Screen Monitors range.

ORDERING INFORMATION(1)

TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°C to 85°C SSOP-16 – DBQ Tape and reel ADS7843IDBQRQ1 S7843Q

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PIN DESCRIPTIONS (continued)

SSOP PACKAGE DESCRIPTION

(TOP VIEW) NO. NAME

5 Y– Y– Position Input

6 GND Ground

7 IN3 Auxiliary Input 1. ADC input Channel 3.

8 IN4 Auxiliary Input 2. ADC input Channel 4.

9 VREF Voltage Reference Input

10 +VCC Power Supply, 2.7V to 5V.

PENIR Pen Interrupt. Open anode output (requires

11 Q 10kΩto 100kΩpull-up resistor externally).

1Serial Data Output. Data is shifted on the

12 DOUT falling edge of DCLK. This output is high

impedance when CS is HIGH.

PIN DESCRIPTIONS Busy Output. This output is high impedance

13 BUSY when CS is HIGH.

PIN DESCRIPTION Serial Data Input. If CS is LOW, data is latched

NO. NAME 14 DIN on rising edge of DCLK.

1 +VCC Power Supply, 2.7V to 5V. Chip Select Input. Controls conversion timing

15 CS

2 X+ X+ Position Input. ADC input Channel 1. and enables the serial input/output register.

3 Y+ Y+ Position Input. ADC input Channel 2. External Clock Input. This clock runs the SAR

4 X– X– Position Input 16 DCLK conversion process and synchronizes serial

data I/O.

ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range (unless otherwise noted)

PARAMETER VALUE UNIT

+VCC to GND –0.3 V to 6.5 V

+VCC to GND –0.3 to +6 V

Analog inputs to GND –0.3 to +VCC + 0.3 V

Digital inputs to GND –0.3 to +VCC + 0.3 V

Power dissipation 250 mW

Maximum junction temperature +150 °C

Operating temperature range –40°C to +85 °C

Storage temperature range –65°C to +150 °C

Lead temperature (soldering, 10s) +300 °C

Human-Body Model (HBM) 400 V

Electrostatic discharge Machine Model (MM) 100 V

(ESD) Charged-Device Model (CDM) 750 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

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ELECTRICAL CHARACTERISTICS

at TA= –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital

inputs = GND or +VCC, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Analog Input

Full-Scale Input Span Positive Input – Negative Input 0 VREF V

Absolute Input Range Positive Input +VCC

–0.2 V

+0.2

Negative Input –0.2 +0.2 V

Capacitance 25 pF

Leakage Current 0.1 μA

System Performance

Resolution 12 Bits

No Missing Codes 11 Bits

Integral Linearity Error ±2 LSB(1)

Offset Error ±6 LSB

Offset Error Match 0.1 1 LSB

Gain Error ±4 LSB

Gain Error Match 0.1 1 LSB

Noise 30 μVrms

Power-Supply Rejection 70 dB

Sampling Dynamics

Conversion Time 12 Clk

Cycles

Acquisition Time 3 Clk

Cycles

Throughput Rate 125 kHz

Multiplexer Settling Time 500 ns

Aperture Delay 30 ns

Aperture Jitter 100 ps

Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 dB

Switch Drivers

On-Resistance Y+, X+ 5 Ω

Y–, X– 6 Ω

Reference Input

Range 1 +VCC V

Resistance CS = GND or +VCC 5 GΩ

Input Current 13 40 μA

fSAMPLE = 12.5kHz 2.5 μA

CS = +VCC 0.001 3 μA

Digital Input/Output

Logic Family CMOS

Logic Levels, Except PENIRQ VIH | IIH |≤+5μA +VCC

+VCC • 0.7 +0.3

VIL | IIL |≤+5μA –0.3 +0.8 V

VOH IOH = –250μA +VCC • 0.8 V

VOL IOL = 250μA 0.4 V

PENIRQ VOL TA= 0°C to +85°C, 100kΩPull-Up 0.8 V

Data Format Straight

Binary

(1) LSB means Least Significant Bit. With VREF equal to +2.5V, 1LSB is 610μV.

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ELECTRICAL CHARACTERISTICS (continued)

at TA= –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital

inputs = GND or +VCC, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Power-Supply Requirements

+VCC Specified Performance 2.7 3.6 V

Quiescent Current 280 650 μA

fSAMPLE = 12.5kHz 220 μA

Shutdown Mode with DCLK = DIN = +VCC 3 μA

Power Dissipation +VCC = +2.7V 1.8 mW

Temperature Range

Specified Performance –40 +85 °C

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Delta from +25°C (LSB)

Supply Current ( A)m

Sample Rate (Hz)

Supply Current ( A)m

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TYPICAL CHARACTERISTICS

TA= 25°C, VDD = 5 V (unless otherwise noted)

SUPPLY CURRENT vs TEMPERATURE POWER-DOWN SUPPLY CURRENT vs TEMPERATURE

Figure 1. Figure 2.

SUPPLY CURRENT vs +VCC MAXIMUM SAMPLE RATE vs +VCC

Figure 3. Figure 4.

CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE

Figure 5. Figure 6.

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LSB Error

R ( )

ON W

R ( )

ON W

Reference Current ( A)m

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TYPICAL CHARACTERISTICS (continued)

TA= 25°C, VDD = 5 V (unless otherwise noted)

REFERENCE CURRENT vs SAMPLE RATE REFERENCE CURRENT vs TEMPERATURE

Figure 7. Figure 8.

SWITCH-ON RESISTANCE vs +VCC SWITCH-ON RESISTANCE vs TEMPERATURE

(X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND)

Figure 9. Figure 10.

MAXIMUM SAMPLING RATE vs RIN

Figure 11.

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1 F

10 Fm

1 Fm

100 k (optional)W

ADS7843-Q1

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THEORY OF OPERATION

The ADS7843-Q1 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on

capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a

0.6μm CMOS process.

The basic operation of the ADS7843-Q1 is shown in Figure 12. The device requires an external reference and an

external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage

between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The

average reference input current depends on the conversion rate of the ADS7843-Q1.

The analog input to the converter is provided via a four-channel multiplexer. A unique configuration of low on-

resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to

provide ground for an external device. By maintaining a differential input to the converter and a differential

reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error

for the particular measurement).

ANALOG INPUT

See Figure 13 for a block diagram of the input multiplexer on the ADS7843-Q1, the differential input of the ADC,

and the converter’s differential reference. Table 1 and Table 2 show the relationship between the A2, A1, A0,

and SER/DFR control bits and the configuration of the ADS7843-Q1. The control bits are provided serially via the

DIN pin—see the Digital Interface section of this data sheet for more details.

When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 13)

is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion

rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically

25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer

from the analog source to the converter is a function of conversion rate.

Figure 12. Basic Operation of the ADS7843-Q1

Table 1. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH)

X Y

A2 A1 A0 X+ Y+ IN3 IN4 –IN(1) SWITCH SWITCH +REF(1) –REF(1)

ES ES

0 0 1 +IN GND OFF ON +VREF GND

1 0 1 +IN GND ON OFF +VREF GND

0 1 0 +IN GND OFF OFF +VREF GND

1 1 0 +IN GND OFF OFF +VREF GND

(1) Internal node, for clarification only—not directly accessible by the user.

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Table 2. Input Configuration, Differential Reference Mode (SER/DFR LOW).

X Y

A2 A1 A0 X+ Y+ IN3 IN4 –IN(1) SWITCH SWITCH +REF(1) –REF(1)

ES ES

0 0 1 +IN –Y OFF ON +Y –Y

1 0 1 +IN –X ON OFF +X –X

0 1 0 +IN GND OFF OFF +VREF GND

1 1 0 +IN GND OFF OFF +VREF GND

(1) Internal node, for clarification only—not directly accessible by the user.

Figure 13. Simplified Diagram of Analog Input

REFERENCE INPUT

The voltage difference between +REF and –REF (shown in Figure 13) sets the analog input range. The

ADS7843-Q1 will operate with a reference in the range of 1V to +VCC. There are several critical items

concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog

voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant

bit) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will

appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a

given converter is 2LSBs with a 2.5V reference, it will typically be 5LSBs with a 1V reference. In each case, the

actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to

provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise

reference, and a low-noise input signal.

The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter

(CDAC) portion of the ADS7843-Q1. Typically, the input current is 13μA with VREF = 2.7V and fSAMPLE =

125kHz. This value will vary by a few microamps depending on the result of the conversion. The reference

current diminishes directly with both conversion rate and reference voltage. As the current from the reference is

drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce

overall current drain from the reference.

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There is also a critical item regarding the reference when making measurements where the switch drivers are on.

For this discussion, it’s useful to consider the basic operation of the ADS7843-Q1 as shown in Figure 12. This

particular application shows the device being used to digitize a resistive touch screen. A measurement of the

current Y position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and

Y– drivers, and digitizing the voltage on X+ (shown in Figure 14). For this measurement, the resistance in the X+

lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough

that this is not a concern).

Figure 14. Simplified Diagram of Single-Ended Reference (SER/DFR HIGH, Y Switches Enabled, X+ is

Analog Input)

However, since the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a

small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale

input regardless of where the pointing device is on the touch screen because some voltage is lost across the

internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen,

providing an additional source of error. This situation can be remedied as shown in Figure 15. By setting the

SER/DFR bit LOW, the +REF and –REF inputs are connected directly to Y+ and Y–. This makes the A/D

conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless

of how it changes in relation to the on-resistance of the internal switches. Note that there is an important

consideration regarding power dissipation when using the ratiometric mode of operation, see the Power

Dissipation section for more details. As a final note about the differential reference mode, it must be used with

+VCC as the source of the +REF voltage and cannot be used with VREF. It is possible to use a high precision

reference on VREF and single-ended reference mode for measurements which do not need to be ratiometric. Or,

in some cases, it could be possible to power the converter directly from a precision reference. Most references

can provide enough power for the ADS7843-Q1, but they might not be able to supply enough current for the

external load (such as a resistive touch screen).

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Figure 15. Simplified Diagram of Differential Reference (SER/DFR LOW, Y Switches Enabled, X+ is

Analog Input).

DIGITAL INTERFACE

Figure 16 shows the typical operation of the

ADS7843-Q1’s digital interface. This diagram

assumes that the source of the digital signals is a

microcontroller or digital signal processor with a basic

serial interface. Each communication between the

processor and the converter consists of eight clock

cycles. One complete conversion can be

accomplished with three serial communications, for a

total of 24 clock cycles on the DCLK input.

The first eight clock cycles are used to provide the

control byte via the DIN pin. When the converter has Figure 16. Conversion Timing, 24 Clocks per

enough information about the following conversion to Conversion, 8-bit Bus Interface. No DCLK Delay

set the input multiplexer, switches, and reference Required with Dedicated Serial Port.

inputs appropriately, the converter enters the

acquisition (sample) mode and, if needed, the internal Control Byte

switches are turned on. After three more clock cycles,

the control byte is complete and the converter enters See Figure 16 for the placement and order of the

the conversion mode. At this point, the input sample- control bits within the control byte. Table 3 and

and-hold goes into the hold mode and the internal Table 4 give detailed information about these bits.

switches may turn off. The next 12th clock cycles The first bit, the ‘S’ bit, must always be HIGH and

accomplish the actual A/D conversion. If the indicates the start of the control byte. The ADS7843-

conversion is ratiometric (SER/DFR LOW), the Q1 will ignore inputs on the DIN pin until the start bit

internal switches are on during the conversion. A 13th is detected. The next three bits (A2-A0) select the

clock cycle is needed for the last bit of the conversion active input channel or channels of the input

result. Three more clock cycles are needed to multiplexer (see Table 1 and Table 2 and Figure 13).

complete the last byte (DOUT will be LOW). These The MODE bit determines the number of bits for each

will be ignored by the converter. conversion, either 12 bits (LOW) or 8 bits (HIGH).

The SER/DFR bit controls the reference mode: either

single-ended (HIGH) or differential (LOW). (The

differential mode is also referred to as the ratiometric

conversion mode.) In single-ended mode, the

converter’s reference voltage is always the difference

between the VREF and GND pins. In differential

mode, the reference voltage is the difference between

the currently enabled switches. See Table 1 and

Table 2 and Figure 13 through Figure 15 for more

information. The last two bits (PD1-PD0) select the

power-down mode as shown in Table 5. If both inputs

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are HIGH, the device is always powered up. If both is initiated, the device will resume normal operation

inputs are LOW, the device enters a power-down instantly—no delay is needed to allow the device to

mode between conversions. When a new conversion power up and the very first conversion will be valid.

There are two power-down modes: one where

PENIRQ is disabled and one where it is enabled.

Table 3. Order of the Control Bits in the Control Byte

Bit 7 Bit 0

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(MSB) (LSB)

SER/D

S A2 A1 A0 MODE PD1 PD0

16-Clocks per Conversion

The control bits for conversion n + 1 can be overlapped with conversion ‘n’ to allow for a conversion every 16

clock cycles, as shown in Figure 17. This figure also shows possible serial communication occurring with other

serial peripherals between each byte transfer between the processor and the converter.

Table 4. Descriptions of the Control Bits within the Control Byte

BIT NAME DESCRIPTION

Start Bit. Control byte starts with first HIGH bit on DIN. A new control

7 S byte can start every 16th clock cycle in 12-bit conversion mode or

every 12th clock cycle in 8-bit conversion mode.

Channel Select Bits. Along with the SER/DFR bit, these bits control

6-4 A2-A0 the setting of the multiplexer input, switches, and reference inputs,

see Tables I and II.

12-Bit/8-Bit Conversion Select Bit. This bit controls the number of

3 MODE bits for the following conversion: 12 bits (LOW) or 8 bits (HIGH).

Single-Ended/Differential Reference Select Bit. Along with bits A2-

2 SER/DFR A0, this bit controls the setting of the multiplexer input, switches, and

reference inputs, see Tables I and II.

1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for details.

Table 5. Power-Down Selection

PD1 PD0 PENIRQ DESCRIPTION

Power-down between conversions. When each conversion is

finished, the converter enters a low power mode. At the start

of the next conversion, the device instantly powers up to full

0 0 Enabled power. There is no need for additional delays to assure full

operation and the very first conversion is valid. The Y– switch

is on while in power-down.

Same as mode 00, except PENIRQ is disabled. The Y–

0 1 Disabled switch is off while in power-down mode.

1 0 Disabled Reserved for future use.

No power-down between conversions, device is always

1 1 Disabled powered.

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Figure 17. Conversion Timing, 16 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required

with Dedicated Serial Port.

This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has

been captured on the input sample-and-hold may droop enough to affect the conversion result. Note that the

ADS7843-Q1 is fully powered while other serial communications are taking place during a conversion.

Digital Timing

Figure 19 and Table 6 provide detailed timing for the digital interface of the ADS7843-Q1.

Table 6. Timing Specifications

(+VCC = +2.7V and Above, TA= –40°C to +85°C, CLOAD = 50pF).

SYMBOL DESCRIPTION MIN MAX UNITS

tACQ Acquisition Time 1.5 μs

tDS DIN Valid Prior to DCLK Rising 100 ns

tDH DIN Hold After DCLK HIGH 10 ns

tDO DCLK Falling to DOUT Valid 200 ns

tDV CS Falling to DOUT Enabled 200 ns

tTR CS Rising to DOUT Disabled 200 ns

tCSS CS Falling to First DCLK Rising 100 ns

tCSH CS Rising to DCLK Ignored 0 ns

tCH DCLK HIGH 200 ns

tCL DCLK LOW 200 ns

tBD DCLK Falling to BUSY Rising 200 ns

tBDV CS Falling to BUSY Enabled 200 ns

CS Rising to BUSY Disabled 200 200 200 ns ns

tBTR 200 ns

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Data Format

The ADS7843-Q1 output data is in Straight Binary format, as shown in Figure 18. This figure shows the ideal

output code for the given input voltage and does not include the effects of offset, gain, or noise.

Figure 18. Ideal Input Voltages and Output Codes

8-Bit Conversion

The ADS7843-Q1 provides an 8-bit conversion mode that can be used when faster throughput is needed and the

digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier.

This could be used in conjunction with serial interfaces that provide 12-bit transfers or two conversions could be

accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster

throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling

time of the ADS7843-Q1 is not as critical—settling to better than 8 bits is all that is needed. The clock rate can

be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in

conversion rate.

Figure 19. Detailed Timing Diagram

down is negligible. If the conversion rate is decreased

POWER DISSIPATION by simply slowing the frequency of the DCLK input,

the two modes remain approximately equal. However,

There are two major power modes for the ADS7843- if the DCLK frequency is kept at the maximum rate

Q1: full power (PD1-PD0 = 11B) and auto power- during a conversion but conversions are simply done

down (PD1-PD0 = 00B). When operating at full speed less often, the difference between the two modes is

and 16 clocks per conversion ( see Figure 17), the dramatic.

ADS7843-Q1 spends most of its time acquiring or

converting. There is little time for auto power-down,

assuming that this mode is active. Therefore, the

difference between full power mode and auto power-

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Figure 20 shows the difference between reducing the prior to latching the output of the analog comparator.

DCLK frequency (“scaling” DCLK to match the Thus, during any single conversion for an ‘n-bit’ SAR

conversion rate) or maintaining DCLK at the highest converter, there are n ‘windows’ in which large

frequency and reducing the number of conversions external transient voltages can easily affect the

per second. In the later case, the converter spends conversion result. Such glitches might originate from

an increasing percentage of its time in power-down switching power supplies, nearby digital logic, and

mode (assuming the auto power-down mode is high-power devices. The degree of error in the digital

active). output depends on the reference voltage, layout, and

the exact timing of the external event. The error can

Another important consideration for power dissipation change if the external event changes in time with

is the reference mode of the converter. In the single- respect to the DCLK input.

ended reference mode, the converter’s internal

switches are on only when the analog input voltage is With this in mind, power to the ADS7843-Q1 should

being acquired (see Figure 16). Thus, the external be clean and well bypassed. A 0.1μF ceramic bypass

device, such as a resistive touch screen, is only capacitor should be placed as close to the device as

powered during the acquisition period. In the possible. A 1μF to 10μF capacitor may also be

differential reference mode, the external device must needed if the impedance of the connection between

be powered throughout the acquisition and +VCC and the power supply is high. The reference

conversion periods (see Figure 16). If the conversion should be similarly bypassed with a 0.1μF capacitor.

rate is high, this could substantially increase power If the reference voltage originates from an op amp,

dissipation. make sure that it can drive the bypass capacitor

without oscillation. The ADS7843-Q1 draws very little

current from the reference on average, but it does

place larger demands on the reference circuitry over

short periods of time (on each rising edge of DCLK

during a conversion).

The ADS7843-Q1 architecture offers no inherent

rejection of noise or voltage variation in regards to the

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise

and ripple from the supply will appear directly in the

digital results. While high frequency noise can be

filtered out, voltage variation due to line frequency

(50Hz or 60Hz) can be difficult to remove.

Figure 20. Supply Current versus Directly Scaling

the Frequency of DCLK with Sample Rate or The GND pin should be connected to a clean ground

Keeping DCLK at the Maximum Possible point. In many cases, this will be the “analog” ground.

Frequency Avoid connections which are too near the grounding

point of a microcontroller or digital signal processor. If

needed, run a ground trace directly from the

LAYOUT converter to the power-supply entry or battery

connection point. The ideal layout will include an

The following layout suggestions should provide the analog ground plane dedicated to the converter and

most optimum performance from the ADS7843-Q1. associated analog circuitry.

However, many portable applications have conflicting

requirements concerning power, cost, size, and In the specific case of use with a resistive touch

weight. In general, most portable devices have fairly screen, care should be taken with the connection

“clean” power and grounds because most of the between the converter and the touch screen. Since

internal components are very low power. This resistive touch screens have fairly low resistance, the

situation would mean less bypassing for the interconnection should be as short and robust as

converter’s power and less concern regarding possible. Longer connections will be a source of

grounding. Still, each situation is unique and the error, much like the on-resistance of the internal

following suggestions should be reviewed carefully. switches. Likewise, loose connections can be a

source of error when the contact resistance changes

For optimum performance, care should be taken with with flexing or vibrations.

the physical layout of the ADS7843-Q1 circuitry. The

basic SAR architecture is sensitive to glitches or

sudden changes on the power supply, reference,

ground connections, and digital inputs that occur just

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REVISION HISTORY

Changes from Original (March, 2011) to Revision A Page

• Changed top-side marking from ADS7843Q to S7843Q. ..................................................................................................... 1

Product Folder Link(s): ADS7843-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS7843IDBQRQ1 ACTIVE SSOP DBQ 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS7843-Q1 :

•Catalog: ADS7843

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS7843IDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS7843IDBQRQ1 SSOP DBQ 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

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