PRELIMINARY
8-Mbit (1M x 8) St atic RAM
CY7C1059DV33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-00061 Rev. *B Revised July 21, 2006
Features
•High speed
—t
AA = 10 ns
• Low active power
—I
CC = 110 mA
• Low CMOS standby power
—I
SB2 = 20 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• A vailable in lead-free 36-ball FBGA and 44-pin TSOP II
ZS44 packages
Functional Description[1]
The CY7C1059DV33 is a high-performance CMOS Static
RAM organized as 1M words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW . Data on the eight I/O pins (I/O0
through I/O7) is then written into the l ocation specified o n the
address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1059DV33 is a vaila ble in 3 6-bal l FB GA and 44 -pin
TSOP II package with center power and ground (revolutionary)
pinout.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www .cypress.com.
14
15
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O 0
I/O 1
I/O 2
I/O 3
1M x 8
ARRAY
I/O 7
I/O 6
I/O 5
I/O 4
A0
A11
A13
A12
A
CE
A
A16
A17
A9
A18
A10
A19
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 2 of 9
Pin Configuration
A15
VCC
A13
A12
A5
NC
WE A7
I/O4
I/O5
A4
I/O6
I/O7
VSS
A11
A10
A1
VSS
I/O0
A2
A8
A6
A3
A0
VCC
I/O1
I/O2
I/O3
A17
A18
A16
CE
OE
A9A14
3
26
5
4
1
D
E
B
A
C
F
G
H
36-ball FBGA
A19
A6
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15 29
30
VCC
A7
A8
A9
NC
NC
NC
NC
A18
VSS
NC
A15
A0
I/O0
A4
CE
A17
A12
A1
18
17
20
19
I/O1
27
28
25
26
22
21 23
24 NC
VSS
WE
I/O2
I/O3
A5
NC
A16
VCC
OE
I/O7
I/O6
I/O5
I/O4
A14
A13
A11
A10
A19
NC
NC
A2
A3
(Top View)
Selection Guide
–10 Unit
Maximum Access T ime 10 ns
Maximum Operating Current 110 mA
Maximum CMOS Standby Current 20 mA
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............. ... ............................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] ....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z S tate[2] .......... ..........................–0.3V to VCC + 0.3V
DC Input Voltage[2] ................................ –0.3V to VCC + 0. 3V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40°C to +85°C3.3V ± 0.3V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions –10 UnitMin. Max.
VOH Output HIGH Voltage VCC = Min. , IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min. , IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage[2] –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 µA
IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA
ICC VCC Operating
Supply Current VCC = Max., f = f MAX = 1/tRC 100 MHz 110 mA
83 MHz 100
66 MHz 90
40 MHz 80
ISB1 Automatic CE Power-down
Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH
or VIN < VIL, f = fMAX 40 mA
ISB2 Automatic CE Power-down
Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 20 mA
Capacitance[3]
Parameter Description Test Con dition s Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 16 pF
COUT I/O Capa citance 16 pF
Thermal Resistance[3]
Parameter Description Test Conditions FBGA TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air , soldered on a 3 × 4.5 inch,
four-layer printed circuit board TBD TBD °C/W
ΘJC Thermal Resistance
(Junction to Case) TBD TBD °C/W
Notes:
2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2V for pulse durations of l ess than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 4 of 9
AC Test Loads and Waveforms[4]
AC Switching Characteristics[5] Over the Operating Range
Parameter Description
–10
UnitMin. Max.
Read Cycle
tpower[6] VCC(typical) to the first access 100 µs
tRC Read Cycle Time 10 ns
tAA Address to Data Valid 10 ns
tOHA Data Hold from Address Change 3 ns
tACE CE LOW to Data Valid 10 ns
tDOE OE LOW to Data Valid 5 ns
tLZOE OE LOW to Low-Z 0 ns
tHZOE OE HIGH to High-Z[7, 8] 5ns
tLZCE CE LOW to Low-Z[8] 3ns
tHZCE CE HIGH to High-Z[7, 8] 5ns
tPU CE LOW to Power-up 0 ns
tPD CE HIGH to Power-down 10 ns
Write Cycle[9, 10]
tWC Write Cycle Time 10 ns
tSCE CE LOW to Write End 7 ns
tAW Address Set-up to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-up to Write Start 0 ns
tPWE WE Pulse Width 7 ns
tSD Data Set-up to Write End 5 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low-Z[8] 3ns
tHZWE WE LOW to High-Z[7, 8] 5ns
Notes:
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics ar e tested for all speeds using the test load
shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the powe r supply should be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE ar e s peci fi ed wi th a l oad capacitan ce of 5 pF a s in pa rt (d ) of AC Test Load s. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Wr ite time of the memory is defined by the overlap of CE LOW, and WE LOW . CE and WE must be LOW to initiate a Write, and the transition of either of
these signal s can terminate th e Write. Th e input dat a set-up and hold t iming should be r eferenced to the leading edge of the signal th at termina tes the W rite.
10.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z characteristics:
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 5 of 9
Data Retention Characteristics Over the Operating Range
Data Retention Waveform
Parameter Description Conditions[11] Min. Max. Unit
VDR VCC for Dat a Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
20 mA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tR[12] Oper ation Recovery Time tRC ns
Switching Waveforms
Read Cycle No. 1[13, 14]
Read Cycle No. 2 (OE Controlled)[14, 15]
Notes:
11.No inputs may exce ed V CC + 0.3V
12.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for Read cycle.
15.Address valid prior to or coincident with CE transition LOW .
3.0V3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 6 of 9
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[16, 17]
Write Cycle No. 2 (WE Controlled, OE LOW)[17]
Notes:
16.Data I/O is high-impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 18
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 18
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 7 of 9
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High-Z Power-down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High-Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1059DV33-10BAXI 51-85105 36-ball FBGA (Pb-Free) Industrial
CY7C1059DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these p arts.
Package Diagrams
36-Ball FBGA (7.00 mm x 8.5 mm x 1.2 mm) (51-85105)
51-85105-*D
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 8 of 9
© Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch an ge wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursua nt to an express written agreement with Cypress. Furthermore, Cy press does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-pin TSOP II (51-85087)
51-85087-*A
PRELIMINARY CY7C1059DV33
Document #: 001-00061 Rev. *B Page 9 of 9
Document History Page
Document Title: CY7C1059DV33 8-Mbit (1M x 8) Stat ic RAM
Document Number: 001-00061
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 342195 See ECN PCI New Data Sheet
*A 380574 See ECN SYT Redefined ICC values for Com’l and Ind’l temperature ran ges
ICC (Com’l): Changed from 11 0, 90 and 80 mA to 110, 100 and 95 mA for 8,
10 and 12 ns speed bins respecti vely
ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8,
10 and 12 ns speed bins respecti vely
Changed the Capacitance values from 8 pF to 10 pF on Page # 3
*B 485796 Se e ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Stree t” to “198 Champion Court”
Removed -8 and -12 Speed bins from product offering,
Removed Commercial Operating Range option,
Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and
VCC + 0.5V to VCC + 0.3V
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Changed the Description of I IX from Input Load Current to
Input Leakage Current.
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.
