1
LT1711/LT1712
Single/Dual 4.5ns, 3V/5V/±5V,
Rail-to-Rail Comparators
The LT
®
1711/LT1712 are UltraFast
TM
4.5ns comparators
featuring rail-to-rail inputs, rail-to-rail complementary out-
puts and an output latch. Optimized for 3V and 5V power
supplies, they operate over a single supply voltage range
from 2.4V to 12V or from ±2.4V to ±6V dual supplies.
The LT1711/LT1712 are designed for ease of use in a
variety of systems. In addition to wide supply voltage
flexibility, rail-to-rail input common mode range extends
100mV beyond both supply rails, and the outputs are
protected against phase reversal for inputs extending
further beyond the rails. Also, the rail-to-rail inputs may be
taken to opposite rails with no significant increase in input
current. The rail-to-rail matched complementary outputs
interface directly to TTL or CMOS logic and can sink 10mA
to within 0.5V of GND or source 10mA to within 0.7V of V
+
.
The LT1711
/LT1712
have internal TTL/CMOS compatible
latches for retaining data at the outputs. Each latch holds
data as long as the latch pin is held high. Latch pin
hysteresis provides protection against slow moving or
noisy latch signals. The LT1711 is available in the 8-pin
MSOP package. The LT1712 is available in the 16-pin
narrow SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
High Speed Automatic Test Equipment
■
Current Sense for Switching Regulators
■
Crystal Oscillator Circuits
■
High Speed Sampling Circuits
■
High Speed A/D Converters
■
Pulse Width Modulators
■
Window Comparators
■
Extended Range V/F Converters
■
Fast Pulse Height/Width Discriminators
■
Line Receivers
■
High Speed Triggers
UltraFast is a trademark of Linear Technology Corporation.
LT1711/LT1712 Propagation Delay
vs Input Overdrive
■
Ultrafast: 4.5ns at 20mV Overdrive
5.5ns at 5mV Overdrive
■
Rail-to-Rail Inputs
■
Rail-to-Rail Complementary Outputs (TTL/CMOS
Compatible)
■
Specified at 2.7V, 5V and ±5V Supplies
■
Output Latch
■
Inputs Can Exceed Supplies Without Phase Reversal
■
LT1711: 8-Lead MSOP Package
■
LT1712: 16-Lead Narrow SSOP Package
171112 TA01
–
+
LT1711
5V
390Ω
200pF * 1% FILM RESISTOR
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
5V
FREQUENCY
OUTPUT
3.9k* V
IN
0V TO 5V
1M
MV-209
VARACTOR
DIODE
2k
2k
100pF
15pFY1** 100pF
0.047µF
C SELECT
(CHOOSE FOR CORRECT
PLL LOOP RESPONSE)
1M
1M 1M*
1N4148 LT1004-2.5
47k*
1k*
A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator
INPUT OVERDRIVE (mV)
0
PROPAGATION DELAY (ns)
3.5
4.0
4.5
t
PD+
t
PD–
30 50
171112 TA02
3.0 10 20 40
5.0
5.5
6.0
60
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
STEP
= 100mV
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LT1711/LT1712
Supply Voltage
V
+
to V
–
............................................................ 12.6V
V
+
to GND ........................................................ 12.6V
V
–
to GND .............................................–10V to 0.3V
Differential Input Voltage ................................... ±12.6V
Latch Pin Voltage...................................................... 7V
Input and Latch Current..................................... ±10mA
ABSOLUTE AXI U RATI GS
WWWU
ORDER PART
NUMBER
LT1711CMS8
LT1711IMS8
Consult factory for parts specified with wider operating temperature ranges.
T
JMAX
= 150°C, θ
JA
= 250°C/ W (NOTE 12)
PACKAGE/ORDER I FOR ATIO
UU
W
MS8 PART MARKING
LTTC
LTTD
1
2
3
4
V
+
+IN
–IN
V
–
8
7
6
5
Q
Q
GND
LATCH
ENABLE
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
(Note 1)
Output Current (Continuous) ..............................±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 2)... –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
–IN A
+IN A
V
–
V
+
V
+
V
–
+IN B
–IN B
GND
Q A
Q A
Q B
Q B
GND
LATCH
ENABLE A
LATCH
ENABLE B
T
JMAX
= 150°C, θ
JA
= 120°C/ W (NOTE 12)
ORDER PART
NUMBER
LT1712CGN
LT1712IGN
GN PART MARKING
1712
1712I
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Positive Supply Voltage Range ●2.4 7 V
V
OS
Input Offset Voltage (Note 4) R
S
= 50Ω, V
CM
= V
+
/2 0.5 5.0 mV
R
S
= 50Ω, V
CM
= V
+
/2 ●6.0 mV
R
S
= 50Ω, V
CM
= 0V 0.7 mV
R
S
= 50Ω, V
CM
= V
+
1mV
∆V
OS
/∆T Input Offset Voltage Drift ●10 µV/°C
I
OS
Input Offset Current 0.2 3 µA
●6µA
I
B
Input Bias Current (Note 5) –18 –5 5 µA
●–35 10 µA
V
CM
Input Voltage Range (Note 9) ●–0.1 V
+
+ 0.1 V
CMRR Common Mode Rejection Ratio V
+
= 5V, 0V ≤ V
CM
≤ 5V 56 65 dB
V
+
= 5V, 0V ≤ V
CM
≤ 5V ●53 dB
V
+
= 2.7V, 0V ≤ V
CM
≤ 2.7V 54 65 dB
V
+
= 2.7V, 0V ≤ V
CM
≤ 2.7V ●50 dB
PSRR
+
Positive Power Supply Rejection Ratio 2.4V ≤ V
+
≤ 7V, V
CM
= 0V 58 75 dB
●56 dB
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
3
LT1711/LT1712
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR
–
Negative Power Supply Rejection Ratio –7V ≤ V
–
≤ 0V, V
+
= 5V, V
CM
= 5V 60 80 dB
●58 dB
A
V
Small-Signal Voltage Gain (Note 10) 1 15 V/mV
V
OH
Output Voltage Swing HIGH I
OUT
= 1mA, V
OVERDRIVE
= 50mV ●V
+
– 0.5 V
+
– 0.2 V
I
OUT
= 10mA, V
OVERDRIVE
= 50mV ●V
+
– 0.7 V
+
– 0.4 V
V
OL
Output Voltage Swing LOW I
OUT
= –1mA, V
OVERDRIVE
= 50mV ●0.20 0.4 V
I
OUT
= –10mA, V
OVERDRIVE
= 50mV ●0.35 0.5 V
I
+
Positive Supply Current (Per Comparator) V
+
= 5V, V
OVERDRIVE
= 1V 15 19 mA
●26 mA
I
–
Negative Supply Current (Per Comparator) V
+
= 5V, V
OVERDRIVE
= 1V 8 10 mA
●13 mA
V
IH
Latch Pin High Input Voltage ●2.4 V
V
IL
Latch Pin Low Input Voltage ●0.8 V
I
IL
Latch Pin Current V
LATCH
= V
+
●15 µA
t
PD
Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 4.5 6.0 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 20mV ●8.5 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 5mV 5.5 ns
∆t
PD
Differential Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 0.5 1.5 ns
t
r
Output Rise Time 10% to 90% 2 ns
t
f
Output Fall Time 90% to 10% 2 ns
t
LPD
Latch Propagation Delay (Note 7) 5ns
t
SU
Latch Setup Time (Note 7) 1ns
t
H
Latch Hold Time (Note 7) 0ns
t
DPW
Minimum Latch Disable Pulse Width (Note 7) 5 ns
f
MAX
Maximum Toggle Frequency V
IN
= 100mV
P-P
Sine Wave 100 MHz
t
JITTER
Output Timing Jitter V
IN
= 630mV
P-P
(0dBm) Sine Wave, f = 30MHz 11 ps
RMS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Positive Supply Voltage Range ●2.4 7 V
V
–
Negative Supply Voltage Range (Note 3) ●–7 0 V
V
OS
Input Offset Voltage (Note 4) R
S
= 50Ω, V
CM
= 0V 0.5 5.0 mV
R
S
= 50Ω, V
CM
= 0V ●6.0 mV
R
S
= 50Ω, V
CM
= 5V 0.7 mV
R
S
= 50Ω, V
CM
= –5V 1 mV
∆V
OS
/∆T Input Offset Voltage Drift 10 µV/°C
I
OS
Input Offset Current 0.2 3 µA
●6µA
I
B
Input Bias Current (Note 5) –18 –5 5 µA
●–35 10 µA
V
CM
Input Voltage Range ●–5.1 5.1 V
CMRR Common Mode Rejection Ratio –5V ≤ V
CM
≤ 5V 61 75 dB
●58 dB
PSRR
+
Positive Power Supply Rejection Ratio 2.4V ≤ V
+
≤ 7V, V
CM
= –5V 58 85 dB
●56 dB
PSRR
–
Negative Power Supply Rejection Ratio –7V ≤ V
–
≤ 0V, V
CM
= 5V 60 80 dB
●58 dB
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
4
LT1711/LT1712
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1711C/LT1712C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1711I/LT1712I are
guaranteed to meet specified performance from –40°C to 85°C.
Note 3: The negative supply should not be greater than the ground pin
voltage and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
Note 4: Input offset voltage (V
OS
) is measured with the LT1711/LT1712 in
a configuration that adds external hysteresis. It is defined as the average of
the two hysteresis trip points.
Note 5: Input bias current (I
B
) is defined as the average of the two input
currents.
Note 6: Propagation delay (t
PD
) is measured with the overdrive added to
the actual V
OS
. Differential propagation delay is defined as:
∆t
PD
= t
PD+
– t
PD–
. Load capacitance is 10pF. Due to test system
requirements, the LT1711/LT1712 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (t
LPD
) is the delay time for the output to
respond when the latch pin is deasserted. Latch setup time (t
SU
) is the
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
A
V
Small-Signal Voltage Gain 1 15 V/mV
V
OH
Output Voltage Swing HIGH (Note 8) I
OUT
= 1mA, V
OVERDRIVE
= 50mV ●4.5 4.8 V
I
OUT
= 10mA, V
OVERDRIVE
= 50mV ●4.3 4.6 V
V
OL
Output Voltage Swing LOW (Note 8) I
OUT
= –1mA, V
OVERDRIVE
= 50mV ●0.20 0.4 V
I
OUT
= –10mA, V
OVERDRIVE
= 50mV ●0.30 0.5 V
I
+
Positive Supply Current (Per Comparator) V
OVERDRIVE
= 1V 17 22 mA
●30 mA
I
–
Negative Supply Current (Per Comparator) V
OVERDRIVE
= 1V 9 12 mA
●15 mA
V
IH
Latch Pin High Input Voltage ●2.4 V
V
IL
Latch Pin Low Input Voltage ●0.8 V
I
IL
Latch Pin Current V
LATCH
= V
+
●15 µA
t
PD
Propagation Delay (Notes 6, 11) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 4.5 6.0 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 20mV ●8.5 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 5mV 5.5 ns
∆t
PD
Differential Propagation Delay (Notes 6, 11) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 0.5 1.5 ns
t
r
Output Rise Time 10% to 90% 2 ns
t
f
Output Fall Time 90% to 10% 2 ns
t
LPD
Latch Propagation Delay (Note 7) 5ns
t
SU
Latch Setup Time (Note 7) 1ns
t
H
Latch Hold Time (Note 7) 0ns
t
DPW
Minimum Latch Disable Pulse Width (Note 7) 5 ns
f
MAX
Maximum Toggle Frequency V
IN
= 100mV
P-P
Sine Wave 100 MHz
t
JITTER
Output Timing Jitter V
IN
= 630mV
P-P
(0dBm) Sine Wave, f = 30MHz 11 ps
RMS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t
H
) is the interval after the latch is asserted in
which the input signal must remain stable. Latch disable pulse width
(t
DPW
) is the width of the negative pulse on the latch enable pin that
latches in new data on the data inputs.
Note 8: Output voltage swings are characterized and tested at V
+
= 5V and
V
–
= 0V. They are guaranteed by design and correlation to meet these
specifications at V
–
= –5V.
Note 9: The input voltage range is tested under the more demanding
conditions of V
+
= 5V and V
–
= –5V. The LT1711/LT1712 are guaranteed
by design and correlation to meet these specifications at V
–
= 0V.
Note 10: The LT1711/LT1712 voltage gain is tested at V
+
= 5V and
V
–
= –5V only. Voltage gain at single supply V
+
= 5V and V
+
= 2.7V is
guaranteed by design and correlation.
Note 11: The LT1711/LT1712 t
PD
is tested at V
+
= 5V and 2.7V with
V
–
= 0V. Propagation delay at V
+
= 5V, V
–
= –5V is guaranteed by design
and correlation.
Note 12: Care must be taken to make sure that the LT1711/LT1712 do not
exceed T
JMAX
when operating with ±5V supplies over the industrial
temperature range. T
JMAX
is not exceeded for DC inputs, but supply
current increases with switching frequency (see Typical Performance
Characteristics).
5
LT1711/LT1712
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Propagation Delay
vs Load Capacitance
Propagation Delay
vs Input Common Mode Voltage Propagation Delay
vs Positive Supply Voltage Positive Supply Current
vs Positive Supply Voltage
Negative Supply Current
vs Negative Supply Voltage
Positive Supply Current
vs Switching Frequency Input Bias Current
vs Input Common Mode Voltage
Input Offset Voltage vs
Temperature Propagation Delay vs
Temperature
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE (mV)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5 050 75
171112 G01
–25 25 100 125
V
CM
= 2.5V
V
CM
= 5V
V
CM
= 0V
V
+
= 5V
V
–
= 0V
LOAD CAPACITANCE (pF)
0 60 100
171112 G02
20
10
9
8
7
t
PD+
6
5
4
340 80 120
PROPAGATION DELAY (ns)
t
PD–
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
TEMPERATURE (°C)
–50
PROPAGATION DELAY (ns)
100
171112 G03
050
8
7
6
5
4
3
2
1
0–25 25 75 125
t
PD+
t
PD
–
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF
INPUT COMMON MODE (V)
–1
PROPAGATION DELAY (ns)
5.5
2
171112 G04
4.5
01 3
3.5
3.0
6.0
5.0
4.0
456
t
PD–
t
PD+
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF
246810
POSITIVE SUPPLY VOLTAGE (V)
0
PROPAGATION DELAY (ns)
5.5
171112 G05
4.0
3.0
6.0
5.0
4.5
3.5
t
PD–
t
PD+
T
A
= 25°C
V
–
= 0V
V
CM
= 2.5V
V
OD
= 20mV
V
STEP
= 100mV
C
LOAD
= 10pF
POSITIVE SUPPLY VOLTAGE (V)
0
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
25
20
15
10
5
02468
171112 G06
10 12
V
–
= –5V
∆V
IN
= 100mV
I
OUT
= 0mA
I
+
AT –55°C
I
+
AT 25°C
I
+
AT 85°C
V
–
= 0V
SWITCHING FREQUENCY (MHz)
0
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
40
30
20
10
010 20 30 40
171112 G07
50 60
T
A
= 25°C
V
+
= 5V
V
–
= 0V
C
LOAD
= 10pF
NEGATIVE SUPPLY VOLTAGE (V)
0
14
12
10
8
6
4
2
0–3 –5
171112 G08
–1 –2 –4 –6 –7
NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
I
–
AT –55°C
I
–
AT 25°C
I
–
AT 85°C
V
+
= 5V
∆V
IN
= 100mV
I
OUT
= 0mA
INPUT COMMON MODE VOLTAGE (V)
–1
INPUT BIAS CURRENT (µA)
–2
4
10
246
171112 G09
–8
–14
–20 01 35
V
+
= 5V
V
–
= 0V
∆V
IN
= 0mV
I
B
AT –55°C
I
B
AT 25°C
I
B
AT 125°C
6
LT1711/LT1712
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Output High Voltage
vs Source Current
Output Timing Jitter
vs Switching Frequency Output Rising Edge, 5V Supply Output Falling Edge, 5V Supply
V
IN
Q
V
IN
Q
Output Low Voltage
vs Sink Current
Input Bias Current vs
Temperature
UU
U
PI FU CTIO S
V
+
(Pins 1): Positive Supply Voltage, Usually 5V.
+IN (Pin 2): Noninverting Input.
–IN (Pin 3): Inverting Input.
V
–
(Pins 4): Negative Supply Voltage, Usually 0V or –5V.
LATCH ENABLE (Pin 5):
Latch Enable Input. With a logic
high, the output is latched.
TEMPERATURE (°C)
–50
INPUT BIAS CURRENT (µA)
100
171112 G10
050
0
–1
–2
–3
–4
–5
–6
–7
–8 –25 25 75 125
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
SOURCE CURRENT (mA)
0.1
OUTPUT VOLTAGE (V)
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0 1.0 10 100
171112 G11
V+ = 5V
V– = 0V
∆VIN = 100mV
VOH AT –55°C
VOH AT 25°C
VOH AT 125°C
SINK CURRENT (mA)
0.1
OUTPUT VOLTAGE (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
01.0 10 100
171112 G12
V
OL
AT –55°C
V
OL
AT 25°C
V
OL
AT 125°C
V
+
= 5V
V
–
= 0V
∆V
IN
= 100mV
FREQUENCY (MHz)
0
OUTPUT TIMING JITTER (ps
RMS
)
100
90
80
70
60
50
40
30
30
10
080
171112 G13
20 40 60 100
T
A
= 25°C
V
+
= 5V
V
–
= 0V
V
CM
= 2.5V
V
IN
= 630mV
P-P
(0dBm) SINE WAVE
GND (Pin 6): Ground Supply Voltage, Usually 0V.
Q (Pin 7): Noninverting Output.
Q (Pin 8): Inverting Output.
LT1711
171112 G14 171112 G15
7
LT1711/LT1712
UU
U
PI FU CTIO S
LT1712
–IN A (Pin 1): Inverting Input of A Channel Comparator.
+IN A (Pin 2): Noninverting Input of A Channel
Comparator.
V
–
(Pins 3, 6): Negative Supply Voltage, Usually – 5V. Pins
3 and 6 should be connected together externally.
V
+
(Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins
4 and 5 should be connected together externally.
+IN B (Pin 7): Noninverting Input of B Channel
Comparator.
–IN B (Pin 8): Inverting Input of B Channel Comparator.
LATCH ENABLE B (Pin 9):
Latch Enable Input of B Channel
Comparator. With a logic high, the B output is latched.
GND (Pin 10): Ground Supply Voltage of B Channel
Comparator, Usually 0V.
Q B (Pin 11): Noninverting Output of B Channel
Comparator.
Q B (Pin 12): Inverting Output of B Channel
Comparator.
Q A (Pin 13): Inverting Output of A Channel
Comparator.
Q A (Pin 14): Noninverting Output of A Channel
Comparator.
GND (Pin 15): Ground Supply Voltage of A Channel
Comparator, Usually 0V
LATCH ENABLE A (Pin 16): Latch Enable Input of A
Channel Comparator.
With a logic high, the A output is
latched.
APPLICATIO S I FOR ATIO
WUUU
Common Mode Considerations
The LT1711/LT1712 are specified for a common mode
range of –5.1V to 5.1V on a ±5V supply, or a common
mode range of – 0.1V to 5.1V on a single 5V supply. A more
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply
voltage. The criteria for common mode limit is that the
output still responds correctly to a small differential input
signal.
When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.
Input Bias Current
Input bias current is measured with the outputs held at
2.5V with a 5V supply voltage. As with any rail-to-rail
differential input stage, the LT1711/LT1712 bias current
flows into or out of the device depending upon the com-
mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive, and these currents flow into the device. For inputs
far enough away from the supply rails, the input bias
current will be some combination of the NPN and PNP bias
currents. As the differential input voltage increases, the
input current of each pair will increase for one of the inputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.
Latch Pin Dynamics
The internal latches of the LT1711/LT1712 comparators
retain the input data (output latched) when their respec-
tive latch pin goes high. The latch pin will float to a low
state when disconnected, but it is better to ground the
8
LT1711/LT1712
latch when a flow-through condition is desired. The latch
pin is designed to be driven with either a TTL or CMOS
output. It has built-in hysteresis of approximately 100mV,
so that slow moving or noisy input signals do not impact
latch performance.
For the LT1712, if only one of the comparators is being
used at a given time, it is best to latch the second compara-
tor to avoid any possibility of interactions between the two
comparators in the same package.
High Speed Design Techniques
The extremely fast speed of the LT1711/LT1712 necessi-
tates careful attention to proper PC board layout and
circuit design in order to prevent oscillations, as with
most high speed comparators. The most common prob-
lem involves power supply bypassing which is necessary
to maintain low supply impedance. Resistance and induc-
tance in supply wires and PC traces can quickly build up
to unacceptable levels, thereby allowing the supply volt-
ages to move as the supply current changes. This move-
ment of the supply voltages will often result in improper
operation. In addition, adjacent devices connected through
an unbypassed supply can interact with each other through
the finite supply impedances.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1711/LT1712
supply pins. A good high frequency capacitor, such as a
1000pF ceramic, is recommended in parallel with larger
capacitors, such as a 0.1µF ceramic and a 4.7µF tantalum
in parallel. These bypass capacitors should be soldered to
the output ground plane such that the return currents do
not pass through the ground plane under the input cir-
cuitry. The common tie point for these two ground planes
should be at the board ground connection. Such star-
grounding and ground plane separation is extremely im-
portant for the proper operation of ultra high speed circuits.
Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as short
as possible and avoid running any output trace adjacent
to an input trace to prevent unnecessary coupling. If
output traces are longer than a few inches, provide proper
termination impedances (typically 100Ω to 400Ω) to
eliminate any reflections that may occur. Also keep source
impedances as low as possible, preferably much less than
1kΩ.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
this isolation as shown in Figure 1, a typical topside layout
of the LT1712 on a multilayer PC board. Shown is the
topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1712 and its adjacent X7R
0805 bypass capacitors. The V
+
, V
–
and GND traces all
shield the inputs from the outputs. Although the two V
–
pins are connected internally, they should be shorted
together externally as well in order for both to function as
shields. The same is true for the two V
+
pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
APPLICATIO S I FOR ATIO
WUUU
171112 F01
Figure 1. Typical LT1712 Topside Metal
for Multilayer PCB Layout
Hysteresis
Another important technique to avoid oscillations is to
provide positive feedback, also known as hysteresis,
from the output to the input. Increased levels of hyster-
esis, however, reduce the sensitivity of the device to input
voltage levels, so the amount of positive feedback should
be tailored to particular system requirements. The
LT1711/LT1712 are completely flexible regarding the
application of hysteresis, due to rail-to-rail inputs and the
complementary outputs. Specifically, feedback resistors
can be connected from one of the outputs to its corre-
sponding input without regard to common mode consid-
erations. Figure 2 shows several configurations.
9
LT1711/LT1712
APPLICATIO S I FOR ATIO
WUUU
–
+
50k
VIN
50Ω
Q
Q
V+ = 5V
V– = –5V
VHYST = 5mV
(ALL 3 CASES)
Q
Q
–
+
50k
VIN
VREF
50Ω
Q
Q
–
+
100k
100k
VIN+
VIN–
50Ω
50Ω
171112 F02
LT1711
LT1711 LT1711
Figure 2. Various Configurations for Introducing Hysteresis
TYPICAL APPLICATIO S
U
–
+
1/2
LT1712
TxD
RxD
7
8
9
LE 6
5
49.9Ω
750k
750k
100k
100k
49.9Ω
2
1
15
3
16
13
14
3V
3V
4
11
12
R2A
2.55k
R3A
124ΩR
OA
140ΩR
OB
140Ω
R1B
499Ω
6-FEET
TWISTED PAIR
Z
O
≈ 120ΩR1D
499Ω
R1C
499Ω
R3B
124Ω
R2C
2.55k 3V
100k
5
11
2
1
12 610
9
8
7
171112 F03
14
315 16 13
4
TxD
RxD
3V
R3C
124Ω
R3D
124Ω
R2D
2.55k
R2B
2.55k
R1A
499Ω
10
–
+
1/2
LT1712
LE
–
+
750k
750k
49.9Ω
49.9Ω
100k
–
+
LE
1/2
LT1712
LE
1/2
LT1712
3V 3V
DIODES: BAV99
×4
Figure 3. 75Mbaud Full Duplex Interface on Two Wires
Simultaneous Full Duplex 75Mbaud Interface
with Only Two Wires
The circuit of Figure 3 shows a simple, fully bidirectional,
differential 2-wire interface that gives good results to
75Mbaud, using the LT1712. Eye diagrams under condi-
tions of unidirectional and bidirectional communication
are shown in Figures 4 and 5. Although not as pristine as
the unidirectional performance of Figure␣ 4, the perfor-
mance under simultaneous bidirectional operation is still
excellent. Because the LT1712 input voltage range ex-
tends 100mV beyond both supply rails, the circuit works
with a full ±3V (one whole V
S
up or down) of ground
potential difference.
The circuit works well with the resistor values shown, but
other sets of values can be used. The starting point is the
characteristic impedance, Z
O
, of the twisted-pair cable.
The input impedance of the resistive network should
match the characteristic impedance and is given by:
RR RRR
RRRR
IN O O
=+
++
[]
2123
2123
•• ||( )
•||( )
10
LT1711/LT1712
Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open
171112 F04
TYPICAL APPLICATIO S
U
Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent
171112 F05
This comes out to 120Ω for the values shown. The
Thevenin equivalent source voltage is given by:
VV
RRR
RRR
R
RRRR
TH S
O
O
=+
++
++
[]
•(–)
()
••||( )
231
231
2123
This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω Z
O
.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:
R3/R2 = 1/2 • 0.0976
1
.
Having already designed R2 + R3 to be 2.653k (by allocat-
ing input impedance across R
O
, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and
123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.
Voltage-Tunable Crystal Oscillator
The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre-
quency. Such voltage-controlled crystal oscillators (VCXO)
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.
The LT1711 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuning bandwidth. It should be picked to complement loop
response in phase locking applications. Figure 6 is a plot
of tuning input voltage versus frequency deviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre-
quency exceeds ±240ppm for a 0V to 5V input.
INPUT VOLTAGE (V)
0
FREQUENCY DEVIATION (kHz)
245
9
8
7
6
5
4
3
2
1
0
171112 F06
13
14.3140MHz
14.31818MHz
14.3217MHz
Figure 6. Control Voltage vs Output Frequency for the
Front Page Application Circuit. Tuning Deviation from
Center Frequency Exceeds ±240ppm
1
Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +
124Ω = 2.674k.
11
LT1711/LT1712
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
345678
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10 9
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021 ± 0.006
(0.53 ± 0.015)
0° – 6° TYP
SEATING
PLANE
0.007
(0.18)
0.043
(1.10)
MAX
0.009 – 0.015
(0.22 – 0.38) 0.005 ± 0.002
(0.13 ± 0.05)
0.034
(0.86)
REF
0.0256
(0.65)
BSC
12
34
0.193 ± 0.006
(4.90 ± 0.15)
8765
0.118 ± 0.004*
(3.00 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
12
LT1711/LT1712
PART NUMBER DESCRIPTION COMMENTS
LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator
LT1116 12ns Single Supply Ground Sensing Comparator Single Supply Version of the LT1016
LT1394 7ns, UltraFast Single Supply Comparator 6mA Single Supply Comparator
LT1671 60ns, Low Power, Single Supply Comparator 450µA Single Supply Comparator
LT1713/LT1714 Single/Dual 7ns, Low Power, 3V/5V/±5V, R-R Comparator 7ns/5mA versions of the LT1711/LT1712
LT1719 4.5ns, Single Supply 3V/5V/±5V Comparator 4mA Comparator with Rail-to-Rail Outputs and Level Shifting
LT1720/LT1721 Dual/Quad, 4.5ns, Single Supply Comparator Dual/Quad Version of the LT1719
LINEAR TECHNOLOGY CORPO RATION 2001
171112f LT/TP 0401 4K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
RELATED PARTS
Figure 7. LT1711 Comparator is Configured as a Series
Resonant Xtal Oscillator. LT1806 Op Amp is Configured
in a Q = 5 Bandpass with fC = 1MHz
3V/DIV
1V/DIV
1V/DIV
200ns/DIV 171112 F08
Figure 8. Oscillator Waveforms with VS = 3V. Top is
Comparator Output. Middle is Xtal Feedback to Pin 2 at
LT1711 (Note the Glitches). Bottom is Buffered, Inverted
and Bandpass Filtered with a Q = 5 by LT1806
1MHz Series Resonant Crystal Oscillator
with Square and Sinusoid Outputs
Figure 7 shows a classic 1MHz series resonant crystal
oscillator. At series resonance, the crystal is a low imped-
ance and the positive feedback connection is what brings
about oscillation at the series resonant frequency. The RC
feedback around the other path ensures that the circuit
does not find a stable DC operating point and refuse to
oscillate. The comparator output is a 1MHz square wave
(top trace of Figure 8) with jitter measured at better than
28ps
RMS
on a 5V supply and 40ps
RMS
on a 3V supply. At
Pin 2 of the comparator, on the other side of the crystal, is
a clean sine wave except for the presence of the small high
U
TYPICAL APPLICATIO
frequency glitch (middle trace of Figure 8). This glitch is
caused by the fast edge of the comparator output feeding
back through crystal capacitance. Amplitude stability of
the sine wave is maintained by the fact that the sine wave
is basically a filtered version of the square wave. Hence,
the usual amplitude control loops associated with sinusoi-
dal oscillators are not necessary.
2
The sine wave is filtered
and buffered by the fast, low noise LT1806 op amp. To
remove the glitch, the LT1806 is configured as a bandpass
filter with a Q of 5 and unity-gain center frequency of
1MHz, with its output shown as the bottom trace of
Figure␣ 8. Distortion was measured at – 70dBc and –60dBc
on the second and third harmonics, respectively.
2
Amplitude will be a linear function of comparator output swing, which is supply dependent
and therefore adjustable. The important difference here is that any added amplitude
stabilization or control loop will not be faced with the classical task of avoiding regions of
nonoscillation versus clipping.
–
+
LT1711
2
3
6
LE
5
1
R1
1k V
S
V
S
V
S
7
8
SQUARE
171112 F07
SINE
R3
1k
C1
0.1µF
4
R2
1k
R4
210Ω
1
6
2
3
4
7
R8
2k
V
S
1MHz
AT-CUT
R9
2k
R7
15.8k
R10
1k
R6
162Ω
C2
0.1µF
C3
100pF
C4
100pF
C5
100pF
–
+
LT1806S8
R5
6.49k
