ISL97642 (R) Data Sheet June 18, 2007 TFT-LCD DC/DC with Integrated Amplifiers FN6436.0 Features The ISL97642 integrates a high performance boost regulator with 2 LDO controllers for VON and VOFF, a VON-slice circuit with adjustable delay and three amplifiers for VCOM and VGAMMA applications. The boost converter in the ISL97642 is a current mode PWM type integrating an 18V N-Channel MOSFET. Using external low-cost transistors, the LDO controllers provide tight regulation for VON, VOFF, as well as providing start-up sequence control and fault protection. The amplifiers are ideal for VCOM and VGAMMA applications, with 150mA peak output current drive, 12MHz bandwidth, and 12V/s slew rate. All inputs and outputs are rail-to-rail. Available in the 32 Ld thin QFN (5mmx5mm) Pb-free package, the ISL97642 is specified for operation over the -40C to +85C temperature range. * Current mode boost regulator - Fast transient response - 1% accurate output voltage - 18V/2.4A integrated FET - >90% efficiency * 2.6V to 5.5V VIN supply * 2 LDO controllers for VON and VOFF - 2% output regulation - VON-slice circuit * High speed amplifiers - 150mA short-circuit output current - 12V/s slew rate - 12MHz -3dB bandwidth - Rail-to-rail inputs and outputs * Built-in power sequencing * Internal soft-start * Multiple overload protection * Thermal shutdown * 32 Ld 5x5 thin QFN package * Pb-free plus anneal available (RoHS compliant) Applications * TFT-LCD panels * LCD monitors * Notebooks * LCD-TVs Ordering Information PART NUMBER (Note) ISL97642IRTZ* PART MARKING 97642 IRTZ PACKAGE (Pb-free) PKG. DWG. # 32 Ld 5x5x0.75 TQFN L32.5x5A *Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97642 Pinouts 25 FBP 26 DRVP 27 FBN 28 DRVN 29 DEL 30 CTL 31 DRN 32 COM ISL97642 (32 LD TQFN) TOP VIEW SRC 1 24 COMP REF 2 23 FB AGND 3 22 IN PGND 4 21 LX THERMAL PAD OUT1 5 20 NC NEG3 16 POS3 15 SUP 14 17 OUT3 NC 13 OUT2 8 NC 12 18 NC BGND 11 POS1 7 POS2 10 19 NC NEG2 9 NEG1 6 NC = NOT INTERNALLY CONNECTED 2 FN6436.0 June 18, 2007 ISL97642 Absolute Maximum Ratings (TA = +25C) Thermal Information IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V COMP, FB, FBP, FBN, DEL, REF to AGND. . . . . -0.3V to VIN+0.3V PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3, DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . . VIN -20V to VIN +0.3V COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to VSRC +0.3V LX Maximum Continuous RMS Output Current . . . . . . . . . . . . . 1.6A OUT1, OUT2, OUT3, OUT4, OUT5 Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . 75mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Continuous Junction Temperature . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over-temperature from -40C to +85C. Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT 5.5 V SUPPLY VIN Input Supply Range VLOR Undervoltage Lockout Threshold VIN rising 2.4 2.5 2.6 V VLOF Undervoltage Lockout Threshold VIN falling 2.2 2.3 2.4 V IS Quiescent Current LX not switching 2.5 mA ISS Quiescent Current - Switching LX switching 5 10 mA TFD Fault Delay Time CDEL = 100nF 23 VREF Reference Voltage TA = +25C SHUTDN 2.6 ms 1.19 1.215 1.235 V 1.187 1.215 1.238 V Thermal Shutdown Temperature 140 C MAIN BOOST REGULATOR VBOOST Output Voltage Range fOSC Oscillator Frequency 1050 1200 DCM Maximum Duty Cycle 82 85 VFBB Boost Feedback Voltage 1.192 1.205 1.218 V 1.188 1.205 1.222 V 0.85 0.925 1.020 V (Note 1) TA = +25C VIN+15% 18 V 1350 kHz % VFTB FB Fault Trip Level Falling edge VBOOST/IBOOST Load Regulation 50mA < ILOAD < 250mA 0.1 % VBOOST/VIN Line Regulation VIN = 2.6V to 5.5V 0.08 %/V IFB Input Bias Current VFB = 1.35V gmV FB Transconductance dI = 2.5A at COMP, FB = COMP rONLX LX ON-resistance ILEAKLX LX Leakage Current VFB = 1.35V, VLX = 13V ILIMLX LX Current Limit Duty cycle = 65% (Note 1) tSSB Soft-Start Period CDEL = 100nF 3 500 160 150 2.4 nA A/V 200 250 m 0.02 40 A 2.8 3.3 A 7 ms FN6436.0 June 18, 2007 ISL97642 Electrical Specifications VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over-temperature from -40C to +85C. Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT 18 V 600 800 A 3 12 mV -50 +50 nA VSUP V OPERATIONAL AMPLIFIERS VSUP Supply Operating Range ISUP Supply Current per Amplifier VOS Offset Voltage IB Input Bias Current CMIR Common Mode Input Range 0 CMRR Common Mode Rejection Ratio 60 AOL Open Loop Gain VOH Output Voltage High VOL Output Voltage Low 4.5 90 dB 110 dB IOUT = 100A VSUP-15 VSUP-2 mV IOUT = 5mA VSUP-250 VSUP-150 mV IOUT = -100A IOUT = -5mA ISC Short-Circuit Current 100 ICONT Continuous Output Current 50 PSRR Power Supply Rejection Ratio 60 BW-3dB 2 30 mV 100 150 mV 150 mA mA 100 dB -3dB Bandwidth 12 MHz GBWP Gain Bandwidth Product 8 MHz SR Slew Rate 12 V/s POSITIVE LDO VFBP Positive Feedback Voltage IDRVP = 100A, TA = +25C 1.176 1.2 1.224 V IDRVP = 100A 1.176 1.2 1.229 V 0.9 0.98 V 50 nA VFTP VFBP Fault Trip Level VFBP falling 0.82 IBP Positive LDO Input Bias Current VFBP = 1.4V -50 VPOS/IPOS FBP Load Regulation VDRVP = 25V, IDRVP = 0A to 20A IDRVP Sink Current VFBP = 1.1V, VDRVP = 10V ILEAKP DRVP Off Leakage Current VFBP = 1.4V, VDRVP = 30V tSSP Soft-Start Period CDEL = 100nF FBN Regulation Voltage IDRVN = 0.2mA, TA = +25C 0.173 0.203 0.233 V IDRVN = 0.2mA 0.171 0.203 0.235 V 430 480 mV 50 nA 2 0.5 % 4 mA 0.1 10 A 7 ms NEGATIVE LDO VFBN VFTN VFBN Fault Trip Level VFBN rising 380 IBN Negative LDO Input Bias Current VFBN = 250mV -50 FBN Load Regulation VDRVN = -6V, IDRVN = 2A to 20A IDRVN Source Current VFBN = 500mV, VDRVN = -6V ILEAKN DRVN Off Leakage Current VFBP = 1.35V, VDRVP = 30V tSSN Soft-start Period CDEL = 100nF VLO CTL Input Low Voltage VIN = 2.6V to 5.5V VHI CTL Input High Voltage VIN = 2.6V to 5.5V 2 0.5 % 4 mA 0.1 10 A 7 ms VON -SLICE CIRCUIT 4 0.4VIN 0.6VIN V V FN6436.0 June 18, 2007 ISL97642 Electrical Specifications VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, Over-temperature from -40C to +85C. Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP -1 MAX UNIT 1 A ILEAKCTL CTL Input Leakage Current CTL = AGND or IN tDrise CTL to OUT Rising Prop Delay 1k from DRN to 8V, VCTL = 0V to 3V step, no load on OUT, measured from VCTL = 1.5V to OUT = 20% 100 ns tDfall CTL to OUT Falling Prop Delay 1k from DRN to 8V, VCTL = 3V to 0V step, no load on OUT, measured from VCTL = 1.5V to OUT = 80% 100 ns VSRC SRC Input Voltage Range ISRC SRC Input Current 30 V Start-up sequence not completed 150 250 A Start-up sequence completed 150 250 A rONSRC SRC ON-resistance Start-up sequence completed 5 10 rONDRN DRN ON-resistance Start-up sequence completed 30 60 tON Turn On Delay CDEL = 100nF (See Figure 22) 10 ms tDEL1 Delay Between VBOOST and VOFF CDEL = 100nF (See Figure 22) 10 ms tDEL2 Delay Between VON and VOFF CDEL = 100nF (See Figure 22) 10 ms tDEL3 Delay From VON to VON-slice Enabled CDEL = 100nF (See Figure 22) 10 ms CDEL Delay Capacitor 100 nF SEQUENCING 22 NOTE: 1. Limits should be considered typical and are not production tested. 5 FN6436.0 June 18, 2007 ISL97642 Pin Descriptions PIN NAME ISL97642 SRC 1 Upper reference voltage for switch output REF 2 Internal reference bypass terminal AGND 3 Analog ground for boost converter and control circuitry PGND 4 Power ground for boost switch OUT1 5 Operational amplifier 1 output NEG1 6 Operational amplifier 1 inverting input POS1 7 Operational amplifier 1 non-inverting input OUT2 8 Operational amplifier 2 output NEG2 9 Operational amplifier 2 inverting input POS2 10 Operational amplifier 2 non-inverting input BGND 11 Operational amplifier ground POS3 15 Operational amplifier 3 non-inverting input NEG3 16 Operational amplifier 3 inverting input OUT3 17 Operational amplifier 3 output SUP 14 Amplifier positive supply rail. Bypass to BGND with 0.1F capacitor POS3 15 Operational amplifier 3 non-inverting input NEG3 16 Operational amplifier 3 inverting input OUT3 17 Operational amplifier 3 output NC 18 NC 19 NC 20 LX 21 Main boost regulator switch connection IN 22 Main supply input; bypass to AGND with 1F capacitor FB 23 Main boost feedback voltage connection COMP 24 Error amplifier compensation pin FBP 25 Positive LDO feedback connection DRVP 26 Positive LDO transistor drive FBN 27 Negative LDO feedback connection DRVN 28 Negative LDO transistor driver DEL 29 Connection for switch delay timing capacitor CTL 30 Input control for switch output DRN 31 Lower reference voltage for switch output COM 32 Switch output; when CTL = 1, COM is connected to SRC through a 15 resistor; when CTL = 0, COM is connected to DRN through a 30 resistor 6 PIN FUNCTION FN6436.0 June 18, 2007 ISL97642 Typical Performance Curves 100 94 90 92 70 60 EFFICIENCY (%) EFFICIENCY (%) 80 VIN = 5V VIN = 3V 50 40 30 20 88 86 82 200 400 600 800 1000 78 1200 0 200 LOAD CURRENT (mA) 600 800 1000 1200 FIGURE 2. BOOST EFFICIENCY AT VOUT = 12V (P MODE) 0 0.12 VIN = 3V -0.1 LINE REGULATION (%) LOAD REGULATION (%) 400 LOAD CURRENT (mA) FIGURE 1. BOOST EFFICIENCY AT VOUT = 12V (PI MODE) -0.2 -0.3 -0.4 VIN = 5V -0.5 -0.6 VIN = 5V VIN = 3V 84 80 10 0 0 90 0 200 400 600 800 1000 1200 0.10 0.08 0.06 0.04 0.02 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) LOAD CURRENT (mA) FIGURE 3. BOOST LOAD REGULATION vs LOAD CURRENT (PI MODE) FIGURE 4. BOOST LINE REGULATION vs INPUT VOLTAGE (PI MODE) LINE REGULATION (%) 3.5 BOOST OUTPUT VOLTAGE (AC COUPLING) 3.0 2.5 2.0 BOOST OUTPUT CURRENT 1.5 1.0 VBOOST = 12V COUT = 30F 0.5 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) FIGURE 5. BOOST LINE REGULATION vs INPUT VOLTAGE (P MODE) 7 FIGURE 6. BOOST PULSE LOAD TRANSIENT RESPONSE FN6436.0 June 18, 2007 ISL97642 Typical Performance Curves 0 VON = 20V LINE REGULATION (%) LOAD REGULATION (%) 0 (Continued) -0.05 -0.10 -0.15 -0.20 -0.25 5 10 15 20 25 -0.02 -0.04 -0.06 -0.08 -0.12 20 30 VON = 20V ILOAD = 20mA -0.10 21 VON LOAD CURRENT (mA) FIGURE 7. VON LOAD REGULATION -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 10 15 20 24 25 30 26 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -15 VOFF = -8V ILOAD = 50mA -14 -13 -12 -11 -10 INPUT VOLTAGE (V) LOAD CURRENT (mA) FIGURE 9. VOFF LOAD REGULATION FIGURE 10. VOFF LINE REGULATION VCDEL INPUT VOLTAGE VBOOST VBOOST VOFF VOFF VON TIME (20ms/DIV) FIGURE 11. START-UP SEQUENCE 8 25 0 VOFF = -8V 5 23 FIGURE 8. VON LINE REGULATION LINE REGULATION (%) LOAD REGULATION (%) 0 -0.1 22 INPUT VOLTAGE (V) VON TIME (20ms/DIV) FIGURE 12. START-UP SEQUENCE FN6436.0 June 18, 2007 ISL97642 Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 0.8 POWER DISSIPATION (W) POWER DISSIPATION (W) 3.0 (Continued) 2.5 2.857W QFN32 2.0 JA = 35C/W 1.5 1.0 0.5 JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.7 758mW QFN32 0.6 JA = 125C/W 0.5 0.4 0.3 0.2 0.1 0 0 0 25 75 85 100 50 125 150 0 AMBIENT TEMPERATURE (C) 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (C) FIGURE 13. OP AMP RAIL-TO-RAIL INPUT/OUTPUT FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE INPUT OUTPUT TIME (50s/DIV) FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE TABLE 1. RECOMMENDED COMPONENTS Applications Information The ISL97642 provides a highly integrated multiple output power solution for TFT-LCD applications. The system consists of one high efficiency boost converter and two low cost linear-regulator controllers (VON and VOFF) with multiple protection functions. The block diagram of the whole part is shown in Figure 16. Table 1 lists the recommended components. The ISL97642 integrates an N-Channel MOSFET in boost converter to minimize the external component counts and cost. The VON, VOFF linear-regulators are independently regulated by using external resistors. To achieve higher voltage than VBOOST, one or multiple stage charge pumps may be used. 9 DESIGNATION C1, C2, C3 D1 DESCRIPTION 10F, 16V X5R ceramic capacitor (1210) TDK C3216X5R0J106K 1A 20V low leakage Schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3 D11, D12, D21 200mA, 30V Schottky barrier diode (SOT-23) Fairchild BAT54S L1 6.8H, 1.3A Inductor TDK SLF6025T-6R8M1R3-PF Q11 200mA, 40V PNP amplifier (SOT-23) Fairchild MMBT3906 Q21 200mA, 40V NPN amplifier (SOT-23) Fairchild MMBT3904 FN6436.0 June 18, 2007 ISL97642 VREF REFERENCE GENERATOR OSCILLATOR COMP SLOPE COMPENSATION OSC LX PWM LOGIC CONTROLLER BUFFER FBB GM AMPLIFIER CINT CURRENT AMPLIFIER PGND UVLO COMPARATOR CURRENT REF CURRENT LIMIT COMPARATOR SHUTDOWN AND START-UP CONTROL VREF SS + DRVP BUFFER THERMAL SHUTDOWN FBP UVLO COMPARATOR SS + DRVN 0.2V BUFFER FBN 0.4V UVLO COMPARATOR FIGURE 16. BLOCK DIAGRAM Boost Converter The main boost converter is a current mode PWM converter operating at a fixed frequency. The 1.2MHz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low cost power system for LCD panel design. The boost converter can operate in continuous or discontinuous inductor current mode. The ISL97642 is designed for continuous current mode, but it can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1: V BOOST 1 ------------------------ = ------------1-D V IN (EQ. 1) Figure 17 shows the block diagram of the boost controller. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined using Equation 2: R1 + R2 V BOOST = --------------------- x V REF R1 (EQ. 2) Where D is the duty cycle of switching MOSFET. 10 FN6436.0 June 18, 2007 ISL97642 The current through MOSFET is limited to 2.8A (typ) peak. This restricts the maximum output current based on Equation 3: I L V IN I OMAX = I LMT - -------- x -------- 2 VO Where IL is peak to peak inductor ripple current, and is set by Equation 4: V IN D I L = --------- x ----L fS (EQ. 4) (EQ. 3) where fS is the switching frequency. SHUTDOWN AND START-UP CONTROL CLOCK SLOPE COMPENSATION IFB CURRENT AMPLIFIER PWM IREF LX LOGIC BUFFER IFB FBB GM AMPLIFIER IREF REFERENCE GENERATOR COMP PGND FIGURE 17. THE BLOCK DIAGRAM OF THE BOOST CONTROLLER 11 FN6436.0 June 18, 2007 ISL97642 Table 2 gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and ILMT: TABLE 2. VIN (V) VO (V) L (H) fS (MHz) IOMAX (mA) 3.3 9 6.8 1.2 890 3.3 12 6.8 1.2 666 3.3 15 6.8 1.2 530 5 9 6.8 1.2 1350 5 12 6.8 1.2 1000 5 15 6.8 1.2 795 Input Capacitor The input capacitor is used to supply the current to the converter. It is recommended that CIN be larger than 10F. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than the maximum input voltage. Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Value of 3.3H to 10H inductor is recommended in applications to fit the internal slope compensation. The inductor must be able to handle the following average and peak current: I L I LPK = I LAVG + -------2 IO I LAVG = ------------1-D (EQ. 5) Rectifier Diode A high-speed diode is desired due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements. Output Capacitor The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor. IO V O - V IN 1 V RIPPLE = I LPK x ESR + ------------------------ x ---------------- x ----C OUT f S VO NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in the Equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. Compensation The ISL97642 incorporates a transconductance amplifier in its feedback path to allow the user some adjustment on the transient response and better regulation. The ISL97642 uses current mode control architecture, which has a fast current sense loop and a slow voltage feedback loop. The fast current feedback loop does not require any compensation. The slow voltage loop must be compensated for stable operation. The compensation network is a series RC network from COMP pin to ground. The resistor sets the high frequency integrator gain for fast transient response and the capacitor sets the integrator zero to ensure loop stability. For most applications, a 2.2nF capacitor and a 180 resistor are inserted in series between COMP pin and ground. To improve the transient response, either the resistor value can be increased or the capacitor value can be reduced, but too high resistor value or too low capacitor value will reduce loop stability. Boost Feedback Resistors As the boost output voltage, VBOOST, is reduced below 12V, the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally (as VBOOST is reduced) by means of a series resistor-capacitor network (R7 and C7) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz for C2 (effective) = 10F and 4kHz for C2 (effective) = 30F. R 7 = 1 0.1 x R 2 - ( 1 R 1 )^-1 (EQ. 7) C 7 = 1 2 x 3.142 x fp x R 7 (EQ. 8) Linear-Regulator Controllers (VON and VOFF) The ISL97642 includes 2 independent linear-regulator controllers, in which there is one positive output voltage (VON) and one negative voltage (VOFF). The VON and VOFF linear-regulator controller function diagram, application circuit and waveforms are shown in Figures 18 and 19 respectively. (EQ. 6) For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. 12 FN6436.0 June 18, 2007 ISL97642 VBOOST LX 0.1F LDO_ON 0.9V PG_LDOP + - CP (TO 36V) 36V ESD CLAMP RBP 700 0.1F VON (TO 35V) DRVP FBP RP1 CON RP2 20k + GMP 1: Np The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by ISL97642 ranges from -5V to -25V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level. Set-up Output Voltage FIGURE 18. VON FUNCTIONAL BLOCK DIAGRAM Refer to the "Typical Application Circuit" on page 18. The output voltages of VON, VOFF and VLOGIC are determined by Equations 9 and 10: R 12 V ON = V REF x 1 + ---------- R 11 LX (EQ. 9) R 22 V OFF = V REFN + ---------- x ( V REFN - V REF ) R (EQ. 10) 21 0.1F Where VREF = 1.2V, VREFN = 0.2V. CP (TO -26V) LDO_OFF PG_LDON VREF + 0.1F RN2 20k 0.4V FBN 1: Nn RN1 VOFF (TO -20V) + GMN DRVN 36V ESD CLAMP RBN 700 High Charge Pump Output Voltage (>36V) Applications In the applications where the charge pump output voltage is over 36V, an external NPN transistor needs to be inserted in between the DRVP pin and the base of pass transistor Q3, as shown in Figure 20, or the linear regulator can control only one stage charge pump and regulate the final charge pump output, as shown in Figure 21. COFF VIN CHARGE PUMP OR VBOOST OUTPUT 700 DRVP FIGURE 19. VOFF FUNCTIONAL BLOCK DIAGRAM The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by ISL97642 ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference. 13 Q11 NPN CASCODE TRANSISTOR VON ISL97642 FBP FIGURE 20. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V) FN6436.0 June 18, 2007 ISL97642 LX 0.1F VBOOST 0.1F 700 DRVP Q11 0.1F 0.1F VON 0.47F 0.1F (>36V) ISL97642 0.22F FBP FIGURE 21. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP Calculation of the Linear Regulator Base-emitter Resistors (RBP and RBN) For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain frequency (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency, low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagram), which increases the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. So choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VON linear regulator. If a Fairchild MMBT3906 PNP transistor is used as the external pass transistor (Q11 in the application diagram), then for a maximum VON operating requirement of 50mA, the data sheet indicates Hfe_min = 60. The base-emitter saturation voltage is: Vbe_max = 0.7V. For the ISL97642, the minimum drive current is: I_DRVP_min = 2mA The minimum base-emitter resistor, RBP, can now be calculated as: RBP_min = VBE_max (I_DRVP_min - Ic/Hfe_min = ( ( 0.7V ) ( 2mA - ( 50mA ) 60 ) ) = 600 (EQ. 11) This is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; for example, 700. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected by supply noise if RBP is made too high in value. 14 Charge Pump To generate an output voltage higher than VBOOST, single or multiple stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages: V OUT + V CE - V INPUT N POSITIVE -------------------------------------------------------------V INPUT - 2 x V F (EQ. 12) where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on the transistor selected. VF is the forward-voltage of the charge-pump rectifier diode. The number of negative charge-pump stages is given by: V OUTPUT + V CE N NEGATIVE ------------------------------------------------V INPUT - 2 x V F (EQ. 13) To achieve high efficiency and low material cost, the lowest number of charge-pump stages, which can meet the above requirements, is always preferred. Charge Pump Output Capacitors Ceramic capacitor with low ESR is recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by Equation 14: I OUT C OUT -----------------------------------------------------2 x V RIPPLE x f OSC (EQ. 14) where fOSC is the switching frequency. Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps The ISL97642 VON and VOFF architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the VON and VOFF supplies. It can be appreciated that should a regular supply of LX switching FN6436.0 June 18, 2007 ISL97642 edges be interrupted (for example during discontinuous operation at light boost load currents), then this may affect the performance of VON and VOFF regulation - depending on their exact loading conditions at the time. To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted by suitable choice of inductor given VIN, VOUT, switching frequency and the VBOOST current loading, to be in continuous operation. Equation 15 gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that: I ( v BOOST_load > D * 1 - D * V IN 2 * L * f OSC ) (EQ. 15) where the duty cycle, D = (VBOOST - VIN)/VBOOST For example, with VIN = 5V, fOSC = 1.2MHz and VBOOST = 12V, we find continuous operation of the boost converter can be guaranteed for: L = 10H and I(VBOOST) > 51mA L = 6.8H and I(VBOOST) > 74mA L = 3.3H and I(VBOOST) > 153mA 15 Start-up Sequence Figure 22 shows a detailed start-up sequence waveform. For a successful power-up, there should be 6 peaks at VCDEL. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage is higher than 2.4V, an internal current source starts to charge CCDEL. During the initial slow ramp, the device checks whether there is a fault condition. If no fault is found during the initial ramp, CCDEL is discharged after the first peak. VREF turns on at the peak of the first ramp. Initially, the boost is not enabled so VBOOST rises to VINVDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. VBOOST soft-starts at the beginning of the third ramp, and is checked at the end of this ramp. The soft-start ramp depends on the value of the CDEL capacitor. For CDEL of 100nF, the soft-start time is ~7ms. VOFF turns on at the start of the fourth peak. VON is enabled at the beginning of the sixth ramp. VOFF and VON are checked at end of this ramp. FN6436.0 June 18, 2007 CHIP DISABLED FAULT DETECTED VON SOFT-START VOFF ON VBOOST SOFT-START VREF ON ISL97642 VCDEL IN VREF VBOOST tON tDEL1 VOFF tDEL2 VON VON SLICE CIRCUIT tDEL3 START-UP SEQUENCE TIMED BY CDEL NOTE: Not to scale NORMAL OPERATION FAULT PRESENT FIGURE 22. START-UP SEQUENCE Component Selection for Start-up Sequencing and Fault Protection The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 100nF and has a usable range from 22nF minimum to several microfarads - only limited by the leakage in the capacitor reaching A levels. CDEL should be at least 1/5 of the value of CREF (see Figure 22). Note that 16 with 100nF on CDEL, the fault time-out will be typically 23ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1F will give a fault time-out period of typically 230ms). Fault Sequencing The ISL97642 has an advanced fault detection system, which protects the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high quality layout/design of the PCB (in respect of grounding quality and decoupling) is necessary to avoid falsely triggering the fault FN6436.0 June 18, 2007 ISL97642 detection scheme - especially during start-up. The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation. VON -Slice Circuit series with the output. However, this will obviously reduce the gain. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current and reduce the gain. The VON-slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin. Over-Temperature Protection Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 5 internal MOSFET, and if CTL is high, COM connects to SRC via a 30 MOSFET. An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point, the device will be latched off until either the input supply voltage or enable is cycled. The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin, as in Equation 16: Layout Recommendation Vg V -------- = ----------------------------------( R i || R L ) * C L t (EQ. 16) Where Vg is the supply voltage applied to the switch control circuit, Ri is the resistance between COM and DRN or SRC including the internal MOSFET rDS(ON), the trace resistance and the resistor inserted; RL is the load resistance of the switch control circuit, and CL is the load capacitance of the switch control circuit. In the "Typical Application Circuit" on page 18, R8, R9 and C8 give the bias to DRN based on Equation 17: V ON * R 9 + A VDD * R 8 V DRN = ------------------------------------------------------------R8 + R9 (EQ. 17) and R10 can be adjusted to adjust the slew rate. Op Amps The ISL97642 has 3 amplifiers respectively. The op amps are typically used to drive the TFT-LCD backplane (VCOM) or the gamma-correction divider string. They feature rail-torail input and output capability. They are unity gain stable, and have low power consumption (typical 600A per amplifier). The ISL97642 has a -3dB bandwidth of 12MHz while maintaining a 10V/s slew rate. Short Circuit Current Limit The ISL97642 will limit the short circuit current to 180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted for a long time, the junction temperature will trigger the Over-Temperature Protection limit and, hence, the part will shut down. Driving Capacitive Loads ISL97642 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in 17 The devices performance (including efficiency, output noise, transient response and control loop stability) is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDD bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers (if available) to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C22, the CDELAY capacitor C7 and the integrator capacitor C23. 9. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation. FN6436.0 June 18, 2007 ISL97642 Typical Application Circuit D11 0.1F VCP D21 VCN D12 0.1F 0.1F 0.1F VIN (2.6V TO 5.5V) AVDD (9V) D1 L1 6.8H 10 10F C1 10Fx2 LX C2 IN FB 470nF R2 64.9k R1 10.2k PGND BOOST R7 OPEN C7 OPEN 180 COMP 2.2nF 700 GND VCN 0.1F VNEG (-8V) DRVN Q21 R22 82k NEG REG DRVP POS REG FBN FBP 10k 470nF R21 VCP 700 Q11 R12 182k R11 9.76k 0.1F VON (24.5V) 470nF REF REF 0.1F CONTROL INPUT SRC CTL COM SW CTL DEL 100nF TO GATE DRIVER IC R8 68k R9 1k DRN AVDD C8 0.1F VMAIN AVDD NEG3 VCOM FB3 OUT3 VCOM3 POS3 OP3 + VCOM SET3 NEG2 NEG1 VCOM FB1 VCOM FB2 OUT2 VCOM2 POS2 OP2 + + VCOM SET2 OUT1 OP1 VCOM1 POS1 VCOM SET1 AGND 18 FN6436.0 June 18, 2007 ISL97642 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) L32.5x5A 2X 0.15 C A D A 32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) D/2 MILLIMETERS 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.30 5, 8 3.55 7, 8 A3 E/2 b E D D2 B TOP VIEW 0.20 REF 0.18 5.00 BSC 3.30 C 0.08 C SEATING PLANE A3 SIDE VIEW A1 3.45 - E 5.00 BSC - 5.75 BSC 9 3.30 e / / 0.10 C - E1 E2 A 0.25 3.45 3.55 0.50 BSC 7, 8 - k 0.20 - - - L 0.30 0.40 0.50 8 N 32 2 Nd 8 3 Ne 8 3 Rev. 2 05/06 NX b 5 0.10 M C A B D2 NX k D2 2 (DATUM B) 8 7 N (DATUM A) 6 INDEX AREA E2 E2/2 3 2 1 NX L N 7 (Ne-1)Xe REF. 8 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN6436.0 June 18, 2007