© Semiconductor Components Industries, LLC, 2015
October, 2017 − Rev. 1
1Publication Order Number:
ESD7331/D
ESD7331
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESD7331 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, the
part is well suited for use in high frequency designs such as USB 2.0
high speed applications.
Features
•Low Capacitance 0.4 pF (Typ)
•Low Clamping Voltage
•Small Body Outline Dimensions: 0.60 mm x 0.30 mm
•Low Body Height: 0.3 mm
•Stand−off Voltage: 3.3 V
•IEC61000−4−2 Level 4 ESD Protection
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•USB 2.0/3.0
•MHL 2.0
•eSATA
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 61000−4−2 (ESD) Contact
Air
±15
±15
kV
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
°PD°
RqJA
250
400
mW
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
Lead Solder Temperature − Maximum
(10 Second Duration)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
Device Package Shipping†
ORDERING INFORMATION
www.onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
ESD7331MUT5G X3DFN2
(Pb−Free)
15000 / Tape &
Reel
X3DFN2
CASE 152AF
MARKING
DIAGRAM
PIN 1
6 = Specific Device Code
(Rotated 180°)
M = Date Code
1
Cathode
2
Anode
6
M
Bi−Directional
IPP
IPP
V
I
IR
IT
IT
IR
VRWM
VCVBR
VRWM VC
VBR
ESD7331
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2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM 3.3 V
Breakdown Voltage (Note 2) VBR IT = 1 mA 4.0 V
Reverse Leakage Current IRVRWM = 3.3 V 1.0 mA
Clamping Voltage (Note 3) VCIPP = 1 A 7.5 V
ESD Clamping Voltage VCPer IEC61000−4−2See Figures 1 and 2
Junction Capacitance CJVR = 0 V, f = 1 MHz 0.4 0.75 pF
Dynamic Resistance RDYN TLP Pulse 0.26 W
Insertion Loss f = 100 MHz
f = 8.5 GHz
0.003
1.79
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.
Figure 1. ESD Clamping Voltage Positive 8 kV
Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Negative 8 kV
Contact per IEC61000−4−2
VOLTAGE (V)
TIME (ns)
−20
0
20
40
60
80
100
120
140
160
−20 0 20 40 60 80 100 120 140
VOLTAGE (V)
TIME (ns)
−70
−60
−50
−40
−30
−20
−10
0
10
−20 0 20 40 60 80 100 120 140
ESD7331
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3
Figure 3. Reverse Leakage Current Figure 4. Line Capacitance, f = 1 MHz
IR (A)
VR (V)
C (pF)
VBias (V)
1.E−11
1.E−10
1.E−09
1.E−08
1.E−07
1.E−06
1.E−05
1.E−04
1.E−03
1.E−12
−10 −6−4−20 2 4 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
−2.5 −2−1.5 −1−0.5 0 0.5 1 1.5
Figure 5. RF Insertion Loss Figure 6. Capacitance over Frequency
CAPACITANCE (pF)
FREQUENCY (Hz)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.E+00 2.E+09 4.E+09 6.E+09 8.E+09 1.E+10
6 10 2 2.5
S21 (dB)
FREQUENCY (Hz)
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
1.E+07 1.E+08 1.E+09 1.E+10
0
1
Figure 7. Positive TLP I−V Curve
ITLP (A)
VCTLP (V)
0
2
4
6
8
10
12
14
16
18
22
048121620
Figure 8. Negative TLP I−V Curve
−88
0.7
0.8
0.9
1.0
2 6 10 14 18
20
ITLP (A)
VCTLP (V)
0
−2
−4
−6
−8
−10
−12
−14
−16
−18
−22
0−4−8−12 −16 −20−2−6−10 −14 −18
−20
ESD7331
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4
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 9. IEC61000−4−2 Spec
Figure 10. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 11. 8 X 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
ESD7331
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5
PACKAGE DIMENSIONS
X3DFN2, 0.62 x 0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
E
D
BOTTOM VIEW
b
e
2X
L22X
TOP VIEW
2X
A
A1
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A0.25 0.33
A1 −−− 0.05
b0.22 0.28
e0.355 BSC
L2 0.17 0.23
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.74
1
0.30
0.31
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2
1
See Application Note AND8398/D for more mounting details
A
M
0.05 BC
A
M
0.05 BC
2X
2X
RECOMMENDED
PIN 1
INDICATOR
(OPTIONAL)
D0.58 0.66
E0.28 0.36
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