MC145484MOTOROLA 1
Advance Information
The MC145484 is a general purpose per channel PCM Codec–Filter with pin
selectable Mu–Law or A–Law companding, and is offered in 20–pin SOG and
SSOP packages. This device performs the voice digitization and reconstruction
as well as the band limiting and smoothing required for PCM systems. This
device is designed to operate in both synchronous and asynchronous
applications and contains an on–chip precision reference voltage.
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter , the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band–
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter . The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
The MC145484 PCM Codec–Filter has a high impedance VAG reference pin
which allows for decoupling of the internal circuitry that generates the
mid–supply VAG reference voltage, to the VSS power supply ground. This
reduces clock noise on the analog circuitry when external analog signals are
referenced to the power supply ground. This device is optimal for electronic
SLIC interfaces.
The MC145484 PCM Codec–Filter accepts a variety of clock formats,
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 and MC145572
U–Interface Transceivers, MC145474/75 and MC145574 S/T–Interface Trans-
ceivers, MC145532 ADPCM Transcoder, MC145422/26 UDLT–1,
MC145421/25 UDLT–2, and MC3419/MC33120 SLICs.
The MC145484 PCM Codec–Filter utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
•Single 5 V Power Supply
•Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
•Fully–Differential Analog Circuit Design for Lowest Noise
•Transmit Band–Pass and Receive Low–Pass Filters On–Chip
•Active R–C Pre–Filtering and Post–Filtering
•Mu–Law and A–Law Companding by Pin Selection
•On–Chip Precision Reference V oltage of 1.575 V for a – 0 dBm TLP @ 600 Ω
•Push–Pull 300 Ω Power Drivers with External Gain Adjust
•MC14LC5480EVK is the Evaluation Kit for This Device
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MC145484/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
DW SUFFIX
SOG PACKAGE
CASE 751D
ORDERING INFORMATION
MC145484DW SOG Package
MC145484SD SSOP
20
1
VDD
PO–
PI
RO–
VAG Ref
PDI
BCLKR
DR
FSR
PO+ 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Mu/A
TG
TI–
TI+
VAG
MCLK
BCLKT
DT
FST
VSS
SD SUFFIX
SSOP
CASE 940C
20
1
Motorola, Inc. 1997
REV 0
2/97 TN97022700
MC145484 MOTOROLA
2
FREQ
FREQ
RO–
PI
PO–
PO+
VDD
VSS
VAG
TG
TI–
TI+
–
+
– 1
1
–
+
SHARED
DAC
DAC
1.575 V
REF
ADC
TRANSMIT
SHIFT
REGISTER
SEQUENCE
AND
CONTROL
DR
FSR
BCLKR
Mu/A
PDI
MCLK
BCLKT
FST
DT
RECEIVE
SHIFT
REGISTER
VAG Ref
VDD
VSS
R*
R*
Figure 1. MC145484 5 V PCM Codec–Filter Block Diagram
DEVICE DESCRIPTION
A PCM Codec–Filter is used for digitizing and reconstruct-
ing the human voice. These devices are used primarily for
the telephone network to facilitate voice switching and trans-
mission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from ‘‘COder’’ for the analog–to–digital
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for
the digital–to–analog converter (DAC) used for reconstruct-
ing voice. A codec is a single device that does both the ADC
and DAC conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This may be accomplished with a linear 13–bit ADC and
DAC, but will far exceed the required signal–to–distortion
ratio at larger amplitudes than 40 dB below the peak ampli-
tude. This excess performance is at the expense of data per
sample. Two methods of data reduction are implemented by
compressing the 13–bit linear scheme to companded
pseudo–logarithmic 8–bit schemes. The two companding
schemes are: Mu–255 Law, primarily in North America and
Japan; and A–Law, primarily used in Europe. These com-
panding schemes are accepted world wide. These compand-
ing schemes follow a segmented or ‘‘piecewise–linear’’ curve
formatted as sign bit, three chord bits, and four step bits. For
a given chord, all sixteen of the steps have the same voltage
weighting. As the voltage of the analog input increases, the
four step bits increment and carry to the three chord bits
which increment. When the chord bits increment, the step
bits double their voltage weighting. This results in an effec-
tive resolution of six bits (sign + chord + four step bits) across
a 42 dB dynamic range (seven chords above 0, by 6 dB per
chord).
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated
from the signal by a high–pass filter before the analog–to–
digital converter.
The digital–to–analog conversion process reconstructs a
staircase version of the desired in–band signal, which has
spectral images of the in–band signal modulated about the
sample frequency and its harmonics. These spectral images
are called aliasing components, which need to be attenuated
to obtain the desired signal. The low–pass filter used to at-
tenuate these aliasing components is typically called a re-
construction or smoothing filter.
The MC145484 PCM Codec–Filter has the codec, both
presampling and reconstruction filters, and a precision volt-
age reference on–chip.
MC145484MOTOROLA 3
PIN DESCRIPTIONS
POWER SUPPLY
VDD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 5 V. This pin should be decoupled to VSS with a
0.1 µF ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
This output pin provides a mid–supply analog ground. This
pin should be decoupled to VSS with a 0.01 µF ceramic ca-
pacitor. All analog signal processing within this device is ref-
erenced to this pin. If the audio signals to be processed are
referenced to VSS, then special precautions must be utilized
to avoid noise between VSS and the VAG pin. Refer to the ap-
plications information in this document for more information.
The VAG pin becomes high impedance when this device is in
the powered–down mode.
VAG Ref
Analog Ground Reference Bypass (Pin 1)
This pin is used to capacitively bypass the on–chip circuit-
ry that generates the mid–supply voltage for the VAG output
pin. This pin should be bypassed to VSS with a 0.1 µF ceram-
ic capacitor using short, low inductance traces. The VAG Ref
pin is only used for generating the reference voltage for the
VAG pin. Nothing is to be connected to this pin in addition to
the bypass capacitor . All analog signal processing within this
device is referenced to the VAG pin. If the audio signals to be
processed are referenced to VSS, then special precautions
must be utilized to avoid noise between VSS and the V AG pin.
Refer to the applications information in this document for
more information. When this device is in the powered–down
mode, the VAG Ref pin is pulled to the VDD power supply with
a non–linear, high–impedance circuit.
CONTROL
Mu/A
Mu/A Law Select (Pin 16)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu–Law companding is selected
when this pin is connected to VDD and A–Law companding is
selected when this pin is connected to VSS.
PDI
Power–Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO–, PO–, PO+, TG, VAG, and DT to be-
come high impedance and the VAG Ref pin is pulled to the
VDD power supply with a non–linear , high–impedance circuit.
The device will operate normally when a logic 1 is applied to
this pin. The device goes through a power–up sequence
when this pin is taken to a logic 1 state, which prevents the
DT PCM output from going low impedance for at least two
FST cycles. The V AG and V AG Ref circuits and the signal pro-
cessing filters must settle out before the DT PCM output or
the RO– receive analog output will represent a valid analog
signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
This is the non–inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the VSS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to VDD minus 1.2 V. This is an FET
gate input.
The TI+ pin also serves as a digital input control for the
transmit input multiplexer. Connecting the TI+ pin to VDD will
place this amplifier’s output (TG) into a high–impedance
state, and selects the TG pin to serve as a high–impedance
input to the transmit filter. Connecting the TI+ pin to VSS will
also place this amplifier’s output (TG) into a high–impedance
state, and selects the TI– pin to serve as a high–impedance
input to the transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting op-
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.
The TI– pin also serves as one of the transmit input multi-
plexer pins when the TI+ pin is connected to VSS. When TI+
is connected to VDD, this pin is ignored. See the pin descrip-
tions for the TI+ and the TG pins for more information.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to VDD will place the TG pin into a high–impedance state,
and selects the TG pin to serve as a high–impedance input to
the transmit filter. All signals at this pin are referenced to the
VAG pin. When TI+ is connected to VSS, this pin is ignored.
See the pin descriptions for the TI+ and TI– pins for more in-
formation. This pin is high impedance when the device is in
the powered–down mode.
MC145484 MOTOROLA
4
RO–
Receive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 1.575 V peak referenced to the VAG
pin. If the device is operated half–channel with the FST pin
clocking and FSR pin held low, the receive filter input will be
conencted to the VAG voltage. This minimizes transients at
the RO– pin when full–channel operation is resumed by
clocking the FSR pin. This pin is high impedance when the
device is in the powered–down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the
VAG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to VDD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
This is the inverting power amplifier output, which is used
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300 Ω load to PO+. The PO+ and PO– outputs are
differential (push–pull) and capable of driving a 300 Ω load to
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
and signal reference of this output is the VAG pin. The VAG
pin cannot source or sink as much current as this pin, and
therefore low impedance loads must be between PO+ and
PO–. The PO+ and PO– differential drivers are also capable
of driving a 100 Ω resistive load or a 100 nF Piezoelectric
transducer in series with a 20 Ω resister with a small increase
in distortion. These drivers may be used to drive resistive
loads of ≥ 32 Ω when the gain of PO– is set to 1/4 or less.
Connecting PI to VDD will power down the power driver am-
plifiers and the PO+ and PO– outputs will be high imped-
ance. This pin is also high impedance when the device is
powered down by the PDI pin.
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
This is the non–inverting power amplifier output, which is
an inverted version of the signal at PO–. This pin is capable
of driving a 300 Ω load to PO–. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high im-
pedance when the device is powered down by the PDI pin.
See PI and PO– for more information.
DIGITAL INTERFACE
MCLK
Master Clock (Pin 11)
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately ris-
ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the out-
put of the serial PCM data at the DT pin. This input is com-
patible with various standards including IDL, Long Frame
Sync, Short Frame Sync, and GCI formats. If both FST and
FSR are held low for several 8 kHz frames, the device will
power down.
BCLKT
Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data. In
the IDL and GCI modes it also controls the transfer rate of
the receive PCM data. This pin can accept any bit clock fre-
quency from 64 to 4096 kHz for Long Frame Sync and Short
Frame Sync timing. This pin can accept clock frequencies
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz
to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BCLKT and is high im-
pedance except when outputting PCM data. When operating
in the IDL or GCI mode, data is output in either the B1 or B2
channel as selected by FSR. This pin is high impedance
when the device is in the powered down mode.
FSR
Frame Sync, Receive (Pin 7)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes. When an ISDN mode (IDL or GCI) has
been selected with BCLKR, this pin selects either B1 (logic 0)
or B2 (logic 1) as the active data channel.
BCLKR
Bit Clock, Receive (Pin 9)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,
and DR become IDL Interface compatible. When this pin is
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-
face compatible.
DR
Data, Receive (Pin 8)
This pin is the PCM data input, and when in a Long Frame
Sync or Short Frame Sync mode is controlled by FSR and
BCLKR. When in the IDL or GCI mode, this data transfer is
controlled by FST and BCLKT. FSR and BCLKR select the
B channel and ISDN mode, respectively.
MC145484MOTOROLA 5
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of this device includes a low–noise,
three–terminal op amp capable of driving a 2 kΩ load. This
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be confi-
gured in an inverting gain circuit. The analog signal may be
applied directly to the TG pin if this transmit op amp is inde-
pendently powered down by connecting the TI+ input to the
VDD power supply. The TG pin becomes high impedance
when the transmit op amp is powered down. The TG pin is
internally connected to a 3–pole anti–aliasing pre–filter. This
pre–filter incorporates a 2–pole Butterworth active low–pass
filter, followed by a single passive pole. This pre–filter is fol-
lowed by a single–ended to differential converter that is
clocked at 512 kHz. All subsequent analog processing uti-
lizes fully–differential circuitry. The next section is a fully–dif-
ferential, 5–pole switched–capacitor low–pass filter with a
3.4 kHz frequency cutoff. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff fre-
quency of about 200 Hz. This high–pass stage has a trans-
mission zero at dc that eliminates any dc coming from the
analog input or from accumulated op amp offsets in the pre-
ceding filter stages. The last stage of the high–pass filter is
an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and re-
ceive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are virtually independent of tempera-
ture and power supply voltage. A binary–weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed
comparator to implement a successive–approximation con-
version algorithm. All of the analog circuitry involved in the
data conversion (the voltage reference, RDAC, CDAC, and
comparator) are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-
pacitor low–pass filter with sinX/X correction, and a 2–pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing fil-
ter is buffered by an amplifier, which is output at the RO– pin.
This output is capable of driving a 2 kΩ load to the VAG pin.
The MC145484 also has a pair of power amplifiers that are
connected in a push–pull configuration. The PI pin is the in-
verting input to the PO– power amplifier. The non–inverting
input is internally tied to the V AG pin. This allows this amplifier
to be used in an inverting gain circuit with two external resis-
tors. The PO+ a mplifier has a gain of minus one, and is in-
ternally connected to the PO– output. This complete power
amplifier circuit is a differential (push–pull) amplifier with ad-
justable gain that is capable of driving a 300 Ω load to
+ 12 dBm. The power amplifier may be powered down inde-
pendently of the rest of the chip by connecting the PI pin to
VDD.
POWER–DOWN
There are two methods of putting this device into a low
power consumption mode, which makes the device nonfunc-
tional and consumes virtually no power. PDI is the power–
down input pin which, when taken low, powers down the
device. Another way to power the device down is to hold both
the FST and FSR pins low while the BCLKT and MCLK pins
are clocked. When the chip is powered down, the VAG, TG,
RO–, PO+, PO–, and DT outputs are high impedance and
the V AG Ref pin is pulled to the VDD power supply with a non–
linear, high–impedance circuit. To return the chip to the pow-
er–up state, PDI must be high and the FST frame sync pulse
must be present while the BCLKT and MCLK pins are
clocked. The DT output will remain in a high–impedance
state for at least two 8 kHz FST pulses after power–up.
MASTER CLOCK
Since this codec–filter design has a single DAC architec-
ture, the MCLK pin is used as the master clock for all analog
signal processing including analog–to–digital conversion,
digital–to–analog conversion, and for transmit and receive fil-
tering functions of this device. The clock frequency applied to
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-
vice has a prescaler that automatically determines the proper
divide ratio to use for the MCLK input, which achieves the re-
quired 256 kHz internal sequencing clock. The clocking re-
quirements of the MCLK input are independent of the PCM
data transfer mode (i.e., Long Frame Sync, Short Frame
Sync, IDL mode, or GCI mode).
DIGITAL I/O
The MC145484 is pin selectable for Mu–Law or A–Law.
Table 1 shows the 8–bit data word format for positive and
negative zero and full scale for both companding schemes.
Table 2 shows the series of eight PCM words for both Mu–
Law and A–Law that correspond to a digital milliwatt. The
digital mW is the 1 kHz calibration signal reconstructed by
the DAC that defines the absolute gain or 0 dBm0 Transmis-
sion Level Point (TLP) of the DAC. The timing for the PCM
data transfer is independent of the companding scheme se-
lected. Refer to Figure 2 for a summary and comparison of
the four PCM data interface modes of this device.
MC145484 MOTOROLA
6
Table 1. PCM Codes for Zero and Full Scale
Ll
Mu–Law A–Law
Level Sign Bit Chord Bits Step Bits Sign Bit Chord Bits Step Bits
+ Full Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
+ Zero 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1
– Zero 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1
– Full Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
Table 2. PCM Codes for Digital mW
Ph
Mu–Law A–Law
Phase Sign Bit Chord Bits Step Bits Sign Bit Chord Bits Step Bits
π/8 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0
3π/8 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1
5π/8 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1
7π/8 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0
9π/8 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0
11π/8 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1
13π/8 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1
15π/8 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0
MC145484MOTOROLA 7
Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)
Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)
Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking)
Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking)
Din (DR)
IDL RX (DR) DON’T
CARE
DON’T CARE
8DR
87654321DR DON’T CAREDON’T CARE
87654321
87654321
B2–CHANNEL (FSR = 1)B1–CHANNEL (FSR = 0)
B2–CHANNEL (FSR = 1)B1–CHANNEL (FSR = 0)
Dout (DT)
DCL (BCLKT)
FSC (FST)
IDL TX (DT)
IDL CLOCK (BCLKT)
IDL SYNC (FST)
DT
BCLKT (BCLKR)
FST (FSR)
DT
BCLKT (BCLKR)
FST (FSR)
DON’T CAREDON’T CARE
DON’T
CARE
DON’T
CARE DON’T CARE
7654321
8
87654321
7654321 8
87654321
7654321
87654321 87654321
87654321 87654321
Figure 2. Digital Timing Modes for the PCM Data Interface
MC145484 MOTOROLA
8
Long Frame Sync
Long Frame Sync is the industry name for one type of
clocking format that controls the transfer of the PCM data
words. (Refer to Figure 2a.) The ‘‘Frame Sync’’ or ‘ ‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Long’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Long Frame Sync
timing occurs when the frame sync is used directly as the
PCM data output driver enable. This results in the PCM out-
put going low impedance with the rising edge of the transmit
frame sync, and remaining low impedance for the duration of
the transmit frame sync.
The implementation of Long Frame Sync has maintained
compatibility and been optimized for external clocking sim-
plicity. This optimization includes the PCM data output going
low impedance with the logical AND of the transmit frame
sync (FST) with the transmit data bit clock (BCLKT). The op-
timization also includes the PCM data output (DT) remaining
low impedance until the middle of the LSB (seven and a half
PCM data clock cycles) or until the FST pin is taken low,
whichever occurs last. This requires the frame sync to be
approximately rising edge aligned with the initiation of the
PCM data word transfer , but the frame sync does not have a
precise timing requirement for the end of the PCM data word
transfer. The device recognizes Long Frame Sync clocking
when the frame sync is held high for two consecutive falling
edges of the transmit data clock. The transmit logic decides
on each frame sync whether it should interpret the next
frame sync pulse as a Long or a Short Frame Sync. This de-
cision is used for receive circuitry also. The device is de-
signed to prevent PCM bus contention by not allowing the
PCM data output to go low impedance for at least two frame
sync cycles after power is applied or when coming out of the
powered down mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The logical AND of the receive frame sync with the receive
data clock tells the device to start latching the 8–bit serial
word into the receive data input on the falling edges of the
receive data clock. The internal receive logic counts the re-
ceive data clock cycles and transfers the PCM data word to
the digital–to–analog converter sequencer on the ninth data
clock rising edge.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 µs. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Short Frame Sync
Short Frame Sync is the industry name for the type of
clocking format that controls the transfer of the PCM data
words (refer to Figure 2b). The ‘‘Frame Sync’’ or ‘‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Short’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Short Frame Sync
timing occurs when the frame sync is used as a ‘‘pre–syn-
chronization’’ pulse that is used to tell the internal logic to
clock out the PCM data word under complete control of the
data clock. The Short Frame Sync is held high for one falling
data clock edge. The device outputs the PCM data word be-
ginning with the following rising edge of the data clock. This
results in the PCM output going low impedance with the ris-
ing edge of the transmit data clock, and remaining low im-
pedance until the middle of the LSB (seven and a half PCM
data clock cycles).
The device recognizes Short Frame Sync clocking when
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a Long or a Short Frame Sync. This decision is used
for receive circuitry also. The device is designed to prevent
PCM bus contention by not allowing the PCM data output to
go low impedance for at least two frame sync cycles after
power is applied or when coming out of the powered down
mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The falling edge of the receive data clock latching a high
logic level at the receive frame sync input tells the device to
start latching the 8–bit serial word into the receive data input
on the following eight falling edges of the receive data clock.
The internal receive logic counts the receive data clock
cycles and transfers the PCM data word to the digital–to–
analog converter sequencer on the rising data clock edge af-
ter the LSB has been latched into the device.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 µs. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Interchip Digital Link (IDL)
The Interchip Digital Link (IDL) Interface is one of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the IDL mode, the de-
vice can communicate in either of the two 64 kbps B chan-
nels (refer to Figure 2c for sample timing). The IDL mode is
selected when the BCLKR pin is held high for two or more
FST (IDL SYNC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of
four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),
and IDL RX (DR). The IDL interface mode provides access to
both the transmit and receive PCM data words with common
control clocks of IDL Sync and IDL Clock. In this mode, the
MC145484MOTOROLA 9
FSR pin controls whether the B1 channel or the B2 channel
is used for both transmit and receive PCM data word trans-
fers. When the FSR pin is low, the transmit and receive PCM
words are transferred in the B1 channel, and for FSR high
the B2 channel is selected. The start of the B2 channel is ten
IDL CLK cycles after the start of the B1 channel.
The IDL SYNC (FST, Pin 14) is the input for the IDL frame
synchronization signal. The signal at this pin is nominally
high for one cycle of the IDL Clock signal and is rising edge
aligned with the IDL Clock signal. (Refer to Figure 4 and the
IDL T iming specifications for more details.) This event identi-
fies the beginning of the IDL frame. The frequency of the IDL
Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST)
should be aligned approximately with the rising edge of
MCLK. MCLK must be one of the clock frequencies specified
in the Digital Switching Characteristics table, and is typically
tied to IDL CLK (BCLKT).
The IDL CLK (BCLKT, Pin 12) is the input for the PCM
data clock. All IDL PCM transfers and data control sequenc-
ing are controlled by this clock following the IDL SYNC. This
pin accepts an IDL data clock frequency of 256 kHz to 4.096
MHz.
The IDL TX (DT, Pin 13) is the output for the transmit PCM
data word. Data bits are output for the B1 channel on se-
quential rising edges of the IDL CLK signal beginning after
the IDL SYNC pulse. If the B2 channel is selected, then the
PCM word transfer starts on the eleventh IDL CLK rising
edge after the IDL SYNC pulse. The IDL TX pin will remain
low impedance for the duration of the PCM word until the
LSB after the falling edge of IDL CLK. The IDL TX pin will re-
main in a high impedance state when not outputting PCM
data or when a valid IDL Sync signal is missing.
The IDL RX (DR, Pin 8) is the input for the receive PCM
data word. Data bits are input for the B1 channel on sequen-
tial falling edges of the IDL CLK signal beginning after the
IDL SYNC pulse. If the B2 channel is selected, then the PCM
word is latched in starting on the eleventh IDL CLK falling
edge after the IDL SYNC pulse.
General Circuit Interface (GCI)
The General Circuit Interface (GCI) is the second of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the GCI mode, the
device can communicate in either of the two 64 kbps B–
channels. (Refer to Figure 2d for sample timing.) The GCI
mode is selected when the BCLKR pin is held low for two or
more FST (FSC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The GCI Interface consists
of four pins: FSC (FST), DCL (BCLKT), Dout (DT), and Din
(DR). The GCI interface mode provides access to both the
transmit and receive PCM data words with common control
clocks of FSC (frame synchronization clock) and DCL (data
clock). In this mode, the FSR pin controls whether the B1
channel or the B2 channel is used for both transmit and re-
ceive PCM data word transfers. When the FSR pin is low , the
transmit and receive PCM words are transferred in the B1
channel, and for FSR high the B2 channel is selected. The
start of the B2 channel is 16 DCL cycles after the start of the
B1 channel.
The FSC (FST, Pin 14) is the input for the GCI frame syn-
chronization signal. The signal at this pin is nominally rising
edge aligned with the DCL clock signal. (Refer to Figure 6
and the GCI Timing specifications for more details.) This
event identifies the beginning of the GCI frame. The frequen-
cy of the FSC synchronization signal is 8 kHz. The rising
edge of the FSC (FST) should be aligned approximately with
the rising edge of MCLK. MCLK must be one of the clock fre-
quencies specified in the Digital Switching Characteristics
table, and is typically tied to DCL (BCLKT).
The DCL (BCLKT, Pin 12) is the input for the clock that
controls the PCM data transfers. The clock applied at the
DCL input is twice the actual PCM data rate. The GCI frame
begins with the logical AND of the FSC with the DCL. This
event initiates the PCM data word transfers for both transmit
and receive. This pin accepts a GCI data clock frequency of
512 kHz to 6.176 MHz for PCM data rates of 256 kHz to
3.088 MHz.
The GCI Dout (DT, Pin 13) is the output for the transmit
PCM data word. Data bits are output for the B1 channel on
alternate rising edges of the DCL clock signal, beginning with
the FSC pulse. If the B2 channel is selected, then the PCM
word transfer starts on the seventeenth DCL rising edge after
the FSC rising edge. The Dout pin will remain low impedance
for 15–1/2 DCL clock cycles. The Dout pin becomes high
impedance after the second falling edge of the DCL clock
during the LSB of the PCM word. The Dout pin will remain in
a high–impedance state when not outputting PCM data or
when a valid FSC signal is missing.
The Din (DR, Pin 8) is the input for the receive PCM data
word. Data bits are latched in for the B1 channel on alternate
rising edges of the DCL clock signal, beginning with the se-
cond DCL clock after the rising edge of the FSC pulse. If the
B2 channel is selected then the PCM word is latched in start-
ing on the eighteenth DCL rising edge after the FSC rising
edge.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The MC145484 is manufactured using high–speed CMOS
VLSI technology to implement the complex analog signal
processing functions of a PCM Codec–Filter . The fully–dif fer-
ential analog circuit design techniques used for this device
result in superior performance for the switched capacitor fil-
ters, the analog–to–digital converter (ADC) and the digital–
to–analog converter (DAC). Special attention was given to
the design of this device to reduce the sensitivities of noise,
including power supply rejection and susceptibility to radio
frequency noise. This special attention to design includes a
fifth order low–pass filter, followed by a third order high–pass
filter whose output is converted to a digital signal with greater
than 75 dB of dynamic range, all operating on a single 5 V
power supply. This results in an LSB size for small audio sig-
nals of about 386 µV. The typical idle channel noise level of
this device is less than one LSB. In addition to the dynamic
range of the codec–filter function of this device, the input
gain–setting op amp has the capability of greater than 35 dB
of gain intended for an electret microphone interface.
This device was designed for ease of implementation, but
due to the large dynamic range and the noisy nature of the
environment for this device (digital switches, radio tele-
MC145484 MOTOROLA
10
phones, DSP front–end, etc.) special care must be taken to
assure optimum analog transmission performance.
PC BOARD MOUNTING
It is recommended that the device be soldered to the PC
board for optimum noise performance. If the device is to be
used in a socket, it should be placed in a low parasitic pin
inductance (generally, low–profile) socket.
POWER SUPPLY, GROUND, AND NOISE
CONSIDERATIONS
This device is intended to be used in switching applica-
tions which often require plugging the PC board into a rack
with power applied. This is known as ‘‘hot–rack insertion.’’ In
these applications care should be taken to limit the voltage
on any pin from going positive of the VDD pins, or negative of
the VSS pins. One method is to extend the ground and power
contacts of the PCB connector. The device has input protec-
tion on all pins and may source or sink a limited amount of
current without damage. Current limiting may be accom-
plished by series resistors between the signal pins and the
connector contacts.
The most important considerations for PCB layout deal
with noise. This includes noise on the power supply, noise
generated by the digital circuitry on the device, and cross
coupling digital or radio frequency signals into the audio sig-
nals of this device. The best way to prevent noise is to:
1. Keep digital signals as far away from audio signals as
possible.
2. Keep radio frequency signals as far away from the audio
signals as possible.
3. Use short, low inductance traces for the audio circuitry
to reduce inductive, capacitive, and radio frequency
noise sensitivities.
4. Use short, low inductance traces for digital and RF
circuitry to reduce inductive, capacitive, and radio
frequency radiated noise.
5. Bypass capacitors should be connected from the VDD,
VAG Ref, and V AG pins to VSS with minimal trace length.
Ceramic monolithic capacitors of about 0.1 µF are
acceptable for the VDD and V AG Ref pins to decouple the
device from its own noise. The VDD capacitor helps
supply the instantaneous currents of the digital circuitry
in addition to decoupling the noise which may be
generated by other sections of the device or other
circuitry on the power supply. The VAG Ref decoupling
capacitor is effecting a low–pass filter to isolate the
mid–supply voltage from the power supply noise gener-
ated on–chip as well as external to the device. The VAG
decoupling capacitor should be about 0.01 µF. This
helps to reduce the inpedance of the VAG pin to VSS at
frequencies above the bandwidth of the VAG generator,
which reduces the susceptibility to RF noise.
6. Use a short, wide, low inductance trace to connect the
VSS ground pin to the power supply ground. The VSS pin
is the digital ground and the most negative power supply
pin for the analog circuitry. All analog signal processing
is referenced to the V AG pin, but because digital and RF
circuitry will probably be powered by this same ground,
care must be taken to minimize high frequency noise in
the VSS trace. Depending on the application, a double–
sided PCB with a VSS ground plane connecting all of the
digital and analog VSS pins together would be a good
grounding method. A multilayer PC board with a ground
plane connecting all of the digital and analog VSS pins
together would be the optimal ground configuration.
These methods will result in the lowest resistance and
the lowest inductance in the ground circuit. This is
important to reduce voltage spikes in the ground circuit
resulting from the high speed digital current spikes. The
magnitude of digitally induced voltage spikes may be
hundreds of times larger than the analog signal the
device is required to digitize.
7. Use a short, wide, low inductance trace to connect the
VDD power supply pin to the 5 V power supply.
Depending on the application, a double–sided PCB with
VDD bypass capacitors to the VSS ground plane, as
described above, may complete the low impedance
coupling for the power supply . For a multilayer PC board
with a power plane, connecting all of the VDD pins to the
power plane would be the optimal power distribution
method. The integrated circuit layout and packaging
considerations for the 5 V VDD power circuit are
essentially the same as for the VSS ground circuit.
8. The VAG pin is the reference for all analog signal
processing. In some applications the audio signal to be
digitized may be referenced to the VSS ground. To
reduce the susceptibility to noise at the input of the ADC
section, the three–terminal op amp may be used in a
differential to single–ended circuit to provide level
conversion from the VSS ground to the VAG ground with
noise cancellation. The op amp may be used for more
than 35 dB of gain in microphone interface circuits, which
will require a compact layout with minimum trace lengths
as well as isolation from noise sources. It is recom-
mended that the layout be as symmetrical as possible to
avoid any imbalances which would reduce the noise
cancelling benefits of this differential op amp circuit.
Refer to the application schematics for examples of this
circuitry.
If possible, reference audio signals to the VAG pin
instead of to the VSS pin. Handset receivers and tele-
phone line interface circuits using transformers may be
audio signal referenced completely to the VAG pin. Re-
fer to the application schematics for examples of this
circuitry. The VAG pin cannot be used for ESD or line
protection.
MC145484MOTOROLA 11
MAXIMUM RATINGS (Voltages Referenced to VSS Pin)
Rating Symbol Value Unit
DC Supply Voltage VDD – 0.5 to 6 V
Voltage on Any Analog Input or Output Pin VSS – 0.3 to VDD + 0.3 V
Voltage on Any Digital Input or Output Pin VSS – 0.3 to VDD + 0.3 V
Operating Temperature Range TA– 40 to + 85 °C
Storage Temperature Range Tstg – 85 to +150 °C
POWER SUPPLY (TA = – 40 to + 85°C)
Characteristics Min Typ Max Unit
DC Supply Voltage 4.5 5.0 5.5 V
Active Power Dissipation (VDD = 5 V) (No Load, PI ≥ VDD – 0.5 V)
(No Load, PI ≤ VDD – 1.5 V) —
—3
34.8
5.0 mA
Power–Down Dissipation (VIH for Logic Levels Must be ≥ 3.0 V) PDI = VSS
FST and FSR = VSS, PDI = VDD —
—0.002
0.01 0.1
0.2 mA
DIGITAL LEVELS (VDD = + 5 V ± 10%, VSS = 0 V, TA = – 40 to + 85°C)
Characteristics Symbol Min Max Unit
Input Low Voltage VIL —0.6 V
Input High Voltage VIH 2.4 — V
Output Low Voltage (DT Pin, IOL= 2.5 mA) VOL —0.4 V
Output High Voltage (DT Pin, IOH = – 2.5 mA) VOH VDD – 0.5 — V
Input Low Current (VSS ≤ Vin ≤ VDD) IIL – 10 + 10 µA
Input High Current (VSS ≤ Vin ≤ VDD) IIH – 10 + 10 µA
Output Current in High Impedance State (VSS ≤ DT ≤ VDD) IOZ – 10 + 10 µA
Input Capacitance of Digital Pins (Except DT) Cin —10 pF
Input Capacitance of DT Pin when High–Z Cout —15 pF
MC145484 MOTOROLA
12
ANALOG ELECTRICAL CHARACTERISTICS (VDD = + 5 V ±10%, VSS = 0 V, TA = – 40 to + 85 °C)
Characteristics Min Typ Max Unit
Input Current TI+, TI– — ± 0.1 ± 1.0 µA
Input Resistance to VAG (VAG – 0.5 V ≤ Vin ≤ VAG + 0.5 V)
TI+, TI– 10
—
— MΩ
Input Capacitance TI+, TI– — — 10 pF
Input Offset Voltage of TG Op Amp TI+, TI– — — ± 5 mV
Input Common Mode Voltage Range TI+, TI– 1.2 VDD – 2.0 V
Input Common Mode Rejection Ratio TI+, TI– — 60 — dB
Gain Bandwidth Product (10 kHz) of TG Op Amp (RL ≥ 10 kΩ) — 3000 — kHz
DC Open Loop Gain of TG Op Amp (RL ≥ 10 kΩ) — 95 — dB
Equivalent Input Noise (C–Message) Between TI+ and TI– at TG — –30 — dBrnC
Output Load Capacitance for TG Op Amp 0 — 100 pF
Output Voltage Range for TG
(RL = 10 kΩ to VAG)
(RL = 2 kΩ to VAG)0.5
1.0 —
—VDD – 0.5
VDD – 1.0
V
Output Current (0.5 V ≤ Vout ≤ VDD – 0.5 V) TG, RO– ± 1.0 — — mA
Output Load Resistance to VAG TG, RO– 2 — — kΩ
Output Impedance (0 to 3.4 kHz) RO– — 1 — Ω
Output Load Capacitance RO– 0 — 500 pF
DC Output Offset Voltage of or RO– Referenced to VAG — — ± 25 mV
VAG Output Voltage Referenced to VSS (No Load) VDD/2 – 0.1 VDD/2 VDD/2 + 0.1 V
VAG Output Current with ± 25 mV Change in Output V oltage ± 2.0 ± 10 — mA
Power Supply Rejection Ratio T ransmit
(0 to 100 kHz @100 mV rms Applied to VDD, Receive
C–Message Weighting, All Analog Signals
Referenced to VAG Pin)
50
50 80
75 —
—dBC
Power Drivers PI, PO+, PO–
Input Current (VAG – 0.5 V ≤ PI ≤ VAG + 0.5 V) PI — ± 0.05 ± 1.0 µA
Input Resistance (VAG – 0.5 V ≤ PI ≤ VAG + 0.5 V) PI 10 — — MΩ
Input Offset Voltage PI — — ± 20 mV
Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–) — — ± 50 mV
Output Current (VSS + 0.7 V ≤ PO+ or PO– ≤ VDD – 0.7 V) ± 10 — — mA
PO+ or PO– Output Resistance (Inverted Unity Gain for PO–) — 1 — Ω
Gain Bandwidth Product (10 kHz, Open Loop for PO–) — 1000 — kHz
Load Capacitance (PO+ or PO– to VAG, or PO+ to PO–) 0 — 1000 pF
Gain of PO+ Relative to PO– (RL = 300 Ω, + 3 dBm0, 1 kHz) – 0.2 0 + 0.2 dB
Total Signal to Distortion at PO+ and PO– with a Differential Load of: 300 Ω
100 nF in series with ≥ 20 Ω
≥100 Ω
45
—
—
60
40
40
—
—
—
dBC
Power Supply Rejection Ratio 0 to 4 kHz
(0 to 25 kHz @ 100 mV rms Applied to VDD. 4 to 25 kHz
PO– Connected to PI. Differential or Measured
Referenced to VAG Pin.)
40
—55
40 —
—dB
MC145484MOTOROLA 13
ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V ± 10%, VSS = 0 V, All Analog Signals Referenced to VAG, 0 dBm0 = 0.775 Vrms = + 0 dBm @ 600 Ω, FST = FSR = 8 kHz,
BCLKT = MCLK = 2.048 MHz Synchronous Operation, TA = – 40 to + 85°C, Unless Otherwise Noted)
Ch i i
A/D D/A
Ui
Characteristics Min Typ Max Min Typ Max Units
Peak Single Frequency Tone Amplitude without Clipping T max —1.575 — — 1.575 — Vpk
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 5.0 V) – 0.25 — + 0.25 – 0.25 — + 0.25 dB
Absolute Gain Variation with Temperature 0 to + 70°C
(Referenced to 25°C) – 40 to + 85°C—
——
—± 0.03
± 0.05 —
——
—± 0.03
± 0.05 dB
Absolute Gain Variation with Power Supply (TA = 25°C) — — ± 0.03 — — ± 0.03 dB
Gain vs Level Tone (Mu–Law, Relative to – 10 dBm0, 1.02 kHz)
+ 3 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
–
0.30
– 0.8
–
1.2
—
—
—
+ 0.20
+ 0.40
+ 0.80
– 0.20
–
0.40
– 0.80
—
—
—
+ 0.20
+ 0.40
+ 0.80
dB
Gain vs Level Pseudo Noise, CCITT G.712 – 10 to – 40 dBm0
(A–Law, Relative to – 10 dBm0) – 40 to – 50 dBm0
– 50 to – 55 dBm0
– 0.25
– 0.60
– 1.00
—
—
—
+ 0.25
+ 0.30
+ 0.45
– 0.25
– 0.30
– 0.45
—
—
—
+ 0.25
+ 0.30
+ 0.45
dB
Total Distortion, 1.02 kHz Tone + 3 dBm0
(Mu–Law, C–Message Weighting) 0 to – 30 dBm0
– 40 dBm0
– 45 dBm0
34
36
30
25
—
—
—
—
—
—
—
—
34
36
30
25
—
—
—
—
—
—
—
—
dBC
Total Distortion, Pseudo Noise, CCITT G.714 (A–Law) – 3 dBm0
– 6 to – 27 dBm0
– 34 dBm0
– 40 dBm0
– 50 dBm0
– 55 dBm0
30
36
34
29
19
14
—
—
—
—
—
—
—
—
—
—
—
—
30
36
35
30
20
15
—
—
—
—
—
—
—
—
—
—
—
—
dB
Idle Channel Noise (For End–to–End and A/D, See Note 1)
(Mu–Law, C–Message Weighted)
(A–Law, Psophometric Weighted) —
——
—17
– 69 —
——
—11
– 79 dBrnc0
dBm0p
Frequency Response (Relative to 1.02 kHz @ 0 dBm0) 15 Hz
50 Hz
60 Hz
165 Hz
200 Hz
300 to 3000 Hz
3000 to 3200 Hz
3300 Hz
3400 Hz
3600 Hz
4000 Hz
4600 Hz to 100 kHz
—
—
—
—
– 1.0
– 0.20
– 0.20
– 0.35
– 0.8
—
—
—
—
—
—
– 3.0
—
—
—
—
—
– 3.0
—
—
– 40
– 30
– 26
—
– 0.4
+ 0.15
+ 0.20
+ 0.15
0
—
– 14
– 32
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.15
– 0.20
– 0.35
– 0.85
—
—
—
—
—
—
—
—
—
—
—
—
– 3.0
—
—
0
0
0
0
0
+ 0.15
+ 0.20
+ 0.15
0
—
– 14
30
dB
In–Band Spurious (1.02 kHz @ 0 dBm0, T ransmit and Receive)
300 to
3400 Hz — — – 48 — — – 48 dB
Out–of–Band Spurious at RO+ (300 to 3400 Hz @ 0 dBm0 in)
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
dB
Idle Channel Noise Selective (8 kHz, Input = VAG, 30 Hz Bandwidth) — — — — — – 70 dBm0
Absolute Delay (1600 Hz) — — 315 — — 205 µs
Group Delay Referenced to 1600 Hz 500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
210
130
70
35
70
95
145
– 40
– 40
– 40
– 30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
85
110
175
µs
Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2) — — –75 — — –75 dB
Intermodulation Distortion of Two Frequencies of Amplitudes
(– 4 to – 21 dBm0 from the Range 300 to 3400 Hz) — — – 41 — — – 41 dB
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.
MC145484 MOTOROLA
14
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = + 5 V ±10%, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted)
Ref.
No. Characteristics Min Typ Max Unit
1Master Clock Frequency for MCLK —
—
—
—
—
—
—
256
512
1536
1544
2048
2560
4096
—
—
—
—
—
—
—
kHz
1MCLK Duty Cycle for 256 kHz Operation 45 — 55 %
2Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns
3Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns
4Rise Time for All Digital Signals — — 50 ns
5 Fall T ime for All Digital Signals — — 50 ns
6Setup T ime from MCLK Low to FST High 50 — — ns
7 Setup T ime from FST High to MCLK Low 50 — — ns
8Bit Clock Data Rate for BCLKT or BCLKR 64 — 4096 kHz
9Minimum Pulse Width High for BCLKT or BCLKR 50 — — ns
10 Minimum Pulse Width Low for BCLKT or BCLKR 50 — — ns
11 Hold T ime from BCLKT (BCLKR) Low to FST (FSR) High 20 — — ns
12 Setup Time for FST (FSR) High to BCLKT (BCLKR) Low 80 — — ns
13 Setup Time from DR Valid to BCLKR Low 0 — — ns
14 Hold Time from BCLKR Low to DR Invalid 50 — — ns
LONG FRAME SPECIFIC TIMING
15 Hold T ime from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns
16 Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data — — 60 ns
17 Delay T ime from BCLKT High to DT for Valid Chord and Step Bit Data — — 60 ns
18 Delay T ime from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
of FST to DT Output High Impedance 10 — 60 ns
19 Minimum Pulse Width Low for FST or FSR 50 — — ns
SHORT FRAME SPECIFIC TIMING
20 Hold T ime from BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns
21 Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low 50 — — ns
22 Delay Time from BCLKT High to DT Data Valid 10 — 60 ns
23 Delay T ime from the 8th BCLKT Low to DT Output High Impedance 10 — 60 ns
MC145484MOTOROLA 15
MCLK
DT
FST
BCLKT
7
11 15
16
3
17
4
8
910
18 18
16
12
6 2
1
5
BCLKR
DR
FSR
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB
14
13
8
910
123456789
123456789
15
12
11
Figure 3. Long Frame Sync Timing
MC145484 MOTOROLA
16
MCLK
DT
FST
BCLKT
7
12
3
22
4
8
910
23
22
11
6 2
1
5
BCLKR
DR
FSR
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB
14
13
8
910
123456789
123456789
12
11
20 21
20 21
Figure 4. Short Frame Sync Timing
MC145484MOTOROLA 17
DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE
(VDD = 5.0 V ± 10%, TA = – 40 to + 85°C, CL = 150 pF, See Figure 5 and Note 1)
Ref.
No. Characteristics Min Max Unit
31 T ime Between Successive IDL Syncs Note 2
32 Hold T ime of IDL SYNC After Falling Edge of IDL CLK 20 — ns
33 Setup T ime of IDL SYNC Before Falling Edge IDL CLK 60 — ns
34 IDL Clock Frequency 256 4096 kHz
35 IDL Clock Pulse Width High 50 — ns
36 IDL Clock Pulse Width Low 50 — ns
37 Data Valid on IDL RX Before Falling Edge of IDL CLK 20 — ns
38 Data Valid on IDL RX After Falling Edge of IDL CLK 75 — ns
39 Falling Edge of IDL CLK to High–Z on IDL TX 10 50 ns
40 Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX 10 60 ns
41 Rising Edge of IDL CLK to Data Valid on IDL TX — 50 ns
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 µs interval).
CH1MSB
IDL TX
(DT)
LSBST3ST2ST1CH3CH2CH1MSB LSBST3ST2ST1CH3CH2CH1MSB
LSBST3ST2ST1CH3CH2CH1MSBLSBST3ST2ST1CH3
IDL RX
(DR)
IDL CLOCK
(BCLKT)
IDLE SYNC
(FST)
21
19181716151413121110987654321
31
32
33
32 34
35
40 41 36 39
40 41 39
37 37
38 38
CH2
Figure 5. IDL Interface Timing
MC145484 MOTOROLA
18
DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE
(VDD = 5.0 V ±10%, TA = – 40 to + 85°C, CL = 150 pF, See Figure 6 and Note 1)
Ref.
No. Characteristics Min Max Unit
42 Time Between Successive FSC Pulses Note 2
43 DCL Clock Frequency 512 6176 kHz
44 DCL Clock Pulse Width High 50 — ns
45 DCL Clock Pulse Width Low 50 — ns
46 Hold T ime of FSC After Falling Edge of DCL 20 — ns
47 Setup T ime of FSC to DCL Falling Edge 60 — ns
48 Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of Dout —60 ns
49 Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of Dout —60 ns
50 Rising Edge of DCL to Valid Data on Dout —60 ns
51 Second DCL Falling Edge During LSB to High Impedance of Dout 10 50 ns
52 Setup Time of Din Before Rising Edge of DCL 20 — ns
53 Hold Time of Din After DCL Rising Edge — 60 ns
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).
31
FSC
(FST)
1211109
Din (DR) CH1MSB
CH1MSB
Dout (DT)
DCL
(BCLKT) 5
4321
1 343332302928272625242322212019181715 1614138765432
LSBST3ST2ST1CH3CH2CH1MSB
LSBST3ST2ST1CH3CH2CH1MSB LSBST3ST2ST1CH3CH2CH1MSB
LSBST3ST2ST1CH3CH2CH1
Din (DR)
Dout (DT)
DCL
(BCLKT)
FSC
(FST)
46
46
47 44 43
45
49
48
52 53
52 53 52 53
MSB
49 50 51 48 50 51
42
Figure 6. GCI Interface Timing
MC145484MOTOROLA 19
PCM IN
2.048 MHz
PCM OUT
8 kHz
+ 5 V
1.0
µ
F
AUDIO OUT
+ 5 V
+
–
0.1
µ
F
0.01
µ
F
10 k
Ω
ANALOG IN
PDI
RO–
PI
PO–
PO+
BCLKR
DR
FSR
VDD
VAG Ref
Mu/A
MCLK
BCLKT
DT
FST
TG
TI–
TI+
VAG
VSS
20
19
18
17
16
15
14
13
12
11 10
8
7
6
5
4
3
2
1
9
10 k
Ω
10 k
Ω
10 k
Ω
1.0
µ
F
Y
0.1
µ
F20 k
20 k
Figure 7. MC145484 Test Circuit — Signals Referenced to VAG Pin
+
68
µ
F
PCM IN
2.048 MHz
PCM OUT
8 kHz
+ 5 V
1.0
µ
F
RL
≥
2 k
Ω
AUDIO OUT
+ 5 V
0.1
µ
F
0.01
µ
F
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
ANALOG IN
20
19
18
17
16
15
14
13
12
11 10
8
7
6
5
4
3
2
1
9
10 k
Ω
1.0
µ
F
Y
RL
≥
150
Ω
AUDIO OUT
PDI
RO–
PI
PO–
PO+
BCLKR
DR
FSR
VDD
VAG Ref
Mu/A
MCLK
BCLKT
DT
FST
TG
TI–
TI+
VAG
VSS
20 k
0.1
µ
F
20 k
Figure 8. MC145484 Test Circuit — Signals Referenced to VSS
MC145484 MOTOROLA
20
8 kHz
2.048 MHz 256 8 97654321
MC74HC4060
1/2 MC74HC73
1/2 MC74HC73
0.1
µ
F
10 M
Ω
18 pF18 pF
2.048 MHz
(FST, FSR)
(BCLKT, BCLKR, MCLK)
8 kHz
2.048 MHz
R OSC
OUT 2
OSC
OUT 1
OSC IN
GND
VCC
Q4Q8
+ 5 V
VCC
GND
+ 5 V
Q
K
J
RQ
Q
K
J
+ 5 V 300
Ω
Q
R
Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz
SIDETONE
420 pF
420 pF
REC
MIC
68
µ
F
+5 V
PCM IN
2.048 MHz
PCM OUT
8 kHz
+ 5 V
1.0
µ
F
+ 5 V
0.1
µ
F
0.01
µ
F
75 k
Ω
1 k
Ω
75 k
Ω
PDI
RO–
PI
PO–
PO+
BCLKR
DR
FSR
VDD
VAG Ref
Mu/A
MCLK
BCLKT
DT
FST
TG
TI–
TI+
VAG
VSS
20
19
18
17
16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
9
1.0
µ
F
1 k
Ω
1 k
Ω
1 k
Ω
0.1
µ
F
Figure 10. MC145484 Analog Interface to Handset
MC145484MOTOROLA 21
B1 – 0 V
B2 – + 5 V
R0 = 600
Ω
R0
N = 1N = 1
RING
TIP
Din
DCL – 4.096 MHz
Dout
FSC – 8 kHz
+ 5 V
1.0
µ
F
+ 5 V
0.1
µ
F
10 k
Ω
20
19
18
17
16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
9
0.1
µ
F
10 k
Ω
Mu/A
MCLK
BCLKT
DT
FST
TG
TI–
TI+
VAG
VSS
PDI
RO–
PI
PO–
PO+
BCLKR
DR
FSR
VDD
VAG Ref
10 k
Ω
10 k
Ω
0.1
µ
F
Figure 11. MC145484 Transformer Interface to 600 Ω Telephone Line with GCI Clocking
– 48 V
N = 0.5
R0 = 600
Ω
N = 0.5
RING
TIP
1/4 R0
PCM IN
2.048 MHz
PCM OUT
8 kHz
1.0
µ
F
+ 5 V
N = 0.5
10 k
Ω
PDI
RO–
PI
PO–
PO+
BCLKR
DR
FSR
VDD
VAG Ref
Mu/A
MCLK
BCLKT
DT
FST
TG
TI–
TI+
VAG
VSS
20
19
18
17
16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
9
10 k
Ω
0.1
µ
F
20 k
Ω
+ 5 V
0.1
µ
F
0.1
µ
F
10 k
Ω
Figure 12. MC145484 Step–Up Transformer Interface to 600 Ω Telephone Line
MC145484 MOTOROLA
22
MC33120/1 VDD
PDI
ST1
VDG
VAG
RFO
12
13
14
9
10
8
11
RxI
15
TxO
VCC
EP
RSI
BP
CN
VEE
NOTES:
1. Component values can be adjusted as needed for desired transmit and receive gain, terminating
impedance, and transhybrid loss.
2. + 5 V line should be clean and free of noise.
3. Keep digital signal lines away from analog signal lines to keep noise from coupling into the analog sections.
4. See data sheets for additional information.
CF 7
VQB 6
CP
TSI
BN
EN
20
19
18
17
16
5
4
3
2
1
MJD253
TIP
1k, 2%
9.1 k
9.1 k
1k, 2%
100
Ω
VEE
0.01
µ
F
RING
MJD243
100
Ω
VEE
0.01
µ
F
0.1
µ
F
BATTERY
VOLTAGE
(– 24 TO – 48 V)
MC145484
VAG
TI+
TI–
Mu/A
VSS
MCLK
19
18
17
16
14
15
11
FST
20
TG
VAG Ref
RO–
PO+
PI
FSR
BCLKR
DT 13
BCLKT 12
PO–
VDD
PDI
DR
1
2
3
4
5
6
7
10
8
9
+ 5 V
0.1
µ
F
4.7
µ
F
300
Ω
20
Ω
10
µ
F
1
µ
F
600
Ω
15.8 k
20.3 k
10 k
30.6 k
4.7 k
1
µ
F
0.005
µ
F
600
Ω
1
µ
F
ANALOG/
DIGITAL
GROUND
0.1
µ
F
10 k
10 k
4.7
µ
F
+ 5 V
0.1
µ
F
+ 5 V
PCM IN
8 kHz
PCM OUT
2.048 MHz
31.6 k
31.6 k
6.2 k
1
µ
F0.01
µ
F
MC145436ADW
D4
D8
DV
ATB
Xin
15
14
13
12
10
11
Xout
16
NC
D2
D1
NC
ENB
Xen
GND 9
VDD
GT
Ain
1
2
3
4
5
6
7
8
TO MCU
1 M
Ω
3.58 MHz
0.1
µ
F
NC
+ 5 V
0.1
µ
F
NC
NC
+
1
Figure 13. POTS Line Interface Circuit Using MC145484, MC33120/21, and MC145436A
MC145484MOTOROLA 23
Table 3. Mu–Law Encode–Decode Characteristics
Chord Number Step Decision Decode
Number of Steps Size Levels Sign Chord Chord Chord Step Step Step Step Levels
Normalized
Encode Normalized
12345678
Digital Code
8159 1 0 0 0 0 0 0 0 8031
7903
8 16 256
…
…
…
4319 1 0 0 0 1 1 1 1 4191
4063
…
…
…
7 16 128 2143 1 0 0 1 1 1 1 1 2079
2015
…
…
…
6 16 64 1055 1 0 1 0 1 1 1 1 1023
991
…
…
…
516325111 0 1 1 1 1 1 1 495
479
…
…
…
4 16 16 239 1 1 0 0 1 1 1 1 231
223
…
…
…
3 16 8 103 11011111 99
95
…
…
…
2164 35 11101111 33
31
…
…
…
1152 3 11111110 2
1
11 11111111 0
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
MC145484 MOTOROLA
24
Table 4. A–Law Encode–Decode Characteristics
Chord Number Step Decision Decode
Number of Steps Size Levels Sign Chord Chord Chord Step Step Step Step Levels
Normalized
Encode Normalized
12345678
Digital Code
4096 1 0 1 0 1 0 1 0 4032
3968
7 16 128
…
…
…
2176 1 0 1 0 0 1 0 1 2112
2048
…
…
…
6 16 64 1088 1 0 1 1 0 1 0 1 1056
1024
…
…
…
5 16 32 544 1 0 0 0 0 1 0 1 528
512
…
…
…
4 16 16 272 1 0 0 1 0 1 0 1 264
256
…
…
…
3 16 8 136 1 1 1 0 0 1 0 1 132
128
…
…
…
2164 68 11110101 66
64
…
…
…
1322 2 11010101 1
0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all even numbered bits.
MC145484MOTOROLA 25
PACKAGE DIMENSIONS
DW SUFFIX
SOG PACKAGE
CASE 751D–04
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X K
C
–T–
SEATING
PLANE
M
RX 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A12.65 12.95 0.499 0.510
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0 7 0 7
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
____
SD SUFFIX
SSOP
CASE 940C–02
20 11
101
H
A
B
–P–
–R–
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ANSI
Y14.5M, 1982.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.15MM PER SIDE.
4. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
5. TERMINAL POSITIONS ARE SHOWN FOR
REFERENCE ONLY.
6. THE LEAD WIDTH DIMENSION DOES NOT
INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL
BE 0.08MM TOTAL IN EXCESS OF THE LEAD
WIDTH DIMENSION.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A7.10 7.30 0.280 0.287
B5.20 5.38 0.205 0.212
C1.75 1.99 0.069 0.078
D0.25 0.38 0.010 0.015
F0.65 1.00 0.026 0.039
G0.65 BSC 0.026 BSC
H0.59 0.75 0.023 0.030
J0.10 0.20 0.004 0.008
L7.65 7.90 0.301 0.311
M0 8 0 8
N0.05 0.21 0.002 0.008
____
GD
S
P
M
0.120 (0.005) T
0.076 (0.003)
N
C
M
R
M
0.25 (0.010)
L
J
F
M
NOTE 4
MC145484 MOTOROLA
26
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer .
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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MC145484/D
◊
