MB90F553APMC - Fujitsu Limited - Datasheet.Directory

FUJITSU MICROELECTRONICS

DATA SHEET

2008.9

The information fo r microcontroller support s is shown in the following homepage.

Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page

"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in

system development. http://edevice.fujitsu.com/micom/en-support/

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90550A/550B Series

MB90552A/552B/553A/553B/T552A/T553A

MB90F553A/P553A/V550A

■DESCRIPTION

The MB90550A/550 B series is a line of general-purpose, high -perf ormance, 16-bit microcontrollers designed for

applications which require high-speed real-time processing, such as industrial machines, OA equipment, and

process control systems.

While inheriting the AT architecture of the F2MC*-8 family, the instruction set for the MB90550A/550B series

incorporates additional in structions f or high-le vel languages, supports e xtended addressing modes , and contains

enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulat ion

instructions. In addition, the MB90550A/550B has an on-chip 32-bit accumulator which enables processing of

long-word data.

MB90552B and MB9055 3B are radia tion noise decr eased type. T here ar e no change in the functi onal specifica-

tion.

*: F2MC is the abbreviation of FUJITSU MICROELECTRONICS Flexible Microcontroller.

■FEATURES

• Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, × four times the PLL clock)

• Maximum memory sp ace: 16 Mbytes (Continued)

DS07-13706-6E

MB90550A/550B Series

2DS07-13706-6E

(Continued)

• Instruction set optimized for controller applications

Supported data types: Bit, byte, word and long word

Typical addressin g mo d e: 23 typ es

Enhanced precision calculatio n realized by 32-bit accumulator

Enhanced signed multiplication/division instruction and RETI instruction function s

• Instruction set designed for high level language (C) and multi-task operat ions

Adoption of system stack pointer

Symmetrical instruction set and barrel shift instructions

• Integrated address match detection function (for two address pointers)

• Faster execution speed: 4-byte queue

• Powerful interrupt functions (Eight priority levels programmable)

External interrupt inputs: 8 channels

• Data transfer functions (In telligent I/O service): Up to 16 channels

DTP request inputs: 8 channels

• Embedded ROM size (EPROM, Flash: 128 Kbytes)

Mask ROM: 64 Kbytes/128 Kbytes

• Embedded RAM size (EPROM, Flash: 4 Kbytes)

Mask ROM: 2 Kbytes/4 Kbytes

• General-purpose ports: Up to 83 channels

(Input pull-up resistor settable for: 16 channels; Open drain settable for: 8 channels; I/O open drains: 6

channels)

• A/D converter (RC successive approximation type): 8 channels

(Resolution: 8 or 10 bits selectable; Conversion time of 26.3 µs minimum)

• UART: 1 channel

• Extended I/O serial interface: 2 channels

•I

2C interface: 2 channels

(Two channels , including one switchable between terminal input and output)

• 16-bit reload timer: 2 channels

• 8/16-bit PPG timer: 3 channels

(8 bits × 2 channels; 16 bits x 1 channel: Mode switching function provided)

• 16-bit I/O time r

(Input capture × 4 channels, output compare × 4 channels, free r un time r ×1 channel)

• Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28)

• Timebase timer/watchdog timer: 18 bits

• Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operatio n modes)

• Package: QFP-100, LQFP-100

•CMOS technology

MB90550A/550B Series

DS07-13706-6E 3

■PRODUCT LINEUP

(Continued)

Part number

Item

MB90552A

MB90552B MB90553A

MB90553B MB90F553A MB90P553A MB90T552A MB90T553A MB90V550A

Classification Mask ROM products Flash ROM

products OTP External ROM products Evaluation

product

Mass Product

ROM size 64 Kbytes 128 Kbytes None None

RAM size 2 Kbytes 4 Kbytes 2 Kbytes 4 Kbytes 6 Kbytes

CPU functions

The number of instructions: 340

Instruction bit length: 8 bits, 16 bit s

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 8 bits, 16 bits

Minimum execution time: 62.5 ns (at ma ch in e cloc k of 16 MHz)

Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)

Ports

General-purpose I/O ports (CMOS ou tput): 53

General-purpose I/O ports (with pull-up resistor): 16

General-purpose I/O ports (N-channel open-drain output): 6

General-purpose I/O ports (N-channel open-drain function selectable): 8

Total: 83

UART (SCI)

Clock synchronized transmission (62.5 Kbps to 2 Mbps)

Clock asynchronized transmission (625 00 bps to 9615 bps)

Transmission can be performed by bi-directional serial transmission or by

master/slave connection.

8/10-bit A/D

converter

Conversion precision: 8/10-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Scan conversion mode (converts t wo or more successive channels and can program up to

8 channels.)

Continuous conversion mod e (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/16-bit PPG timer

Number of channels: 3 (8-bit × 6 channels)

PPG operation of 8-bit or 16-bit

A pulse wave of given inter vals and given duty ratios can be output.

Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz)

16-bit

I/O

timer

16-bit

free run timer Number of channels: 1

Overflow interrupts

Output com-

pare (OCU) Number of channels: 4

Pin input factor: A match signal of compare register

Input capture

(ICU) Number of channels: 4

Rewriting a register value upon a pin input (rising, falling or both edges)

MB90550A/550B Series

4DS07-13706-6E

(Continued)

*:Varies with conditions such as the operating freque ncy. (See section “■ ELECTRICAL CHARACTERISTICS”)

Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an

operating temperature of 0°C to +25°C, and an operating frequency of 1 MHz to 16 MHz.

■PACKAGE AND CORRESPONDING PRODUCTS

: Available ×: Not available

Note:For more inf ormation about each package, see section “■ PACKAGE DIMENSIONS”

■DIFFERENCES AMONG PRODUCTS

Memory Size

In evaluation with an evaluation product, note the difference between the evaluation product and the product

actually used. The following items must be taken into consideration.

• The MB90V550A does not have an internal ROM. However, operations equivalent to those perfor med by a

chip with an internal ROM can be e valuated b y using a dedicated development tool, enab ling selection of ROM

size by setting the development tool.

• In the MB90V550A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH

are mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)

• In the MB90F553A/553A/553B/552A/552B, images from FF4000H to FFFFFFH are mapped to ban k 00, and

FF0000H to FF3FFFH to bank FF only.

Part number

Item

MB90552A

MB90552B MB90553A

MB90553B MB90F553A MB90P553A MB90T552A MB90T553A MB90V550A

DTP/external

interrupt circuit

Number of inputs: 8

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.

Extended I/O serial

interface Clock synchronized transmission (3125 bps to 1 Mbps)

LSB first/MSB first

I2C interface Serial I/O port for supporting Inter IC BUS

Timebase timer 18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

Watchdog timer Reset ge neration inter val: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Process CMOS

Power supply volt-

age for operation* 4.5 V to 5.5 V

Package MB90552A

MB90552B MB90553A

MB90553B MB90F553A MB90P553A

FPT-100P-M20 ×

FPT-100P-M06

MB90550A/550B Series

DS07-13706-6E 5

■PIN ASSIGNMENTS

(Continued)

(Top View)

(FPT-100P-M06)

100

P20/A16

P21/A17

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

P32/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SCK

P41/SOT

P42/SIN

P43/SCK1

P44/SOT1

P45/SIN1

P46/ADTG

P47/SCK0

P50/SDA0/SOT0

P51/SCL0/SIN0

P52/SDA1

PA4/CKOT

PA2

RST

PA1/OUT3

PA0/OUT2

P97/PPG5

P96/PPG4

P95/PPG3

P94/PPG2

P93/PPG1

P92/PPG0

P91/OUT1

P90/OUT0

P87/IN3

P86/IN2

P85/IN1

P84/IN0

P83/TOT1

P82/TOT0

P81/TIN1

P80/TIN0

P77/IRQ7

P76/IRQ6

P75/IRQ5

P74/IRQ4

P73/IRQ3

P72/IRQ2

HST

MD2

PA3

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

P00/AD00

P53/SCL1

P54/SDA2

P55/SCL2

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P70/IRQ0

P71/IRQ1

MD0

MD1

AVRH

AVRL

MB90550A/550B Series

6DS07-13706-6E

(Continued) (Top view)

(FPT-100P-M20)

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

VSS

P32/WRL

P34/HRQ

P33/WRH

P35/HAK

P36/RDY

P37/CLK

P40/SCK

P41/SOT

P42/SIN

P43/SCK1

P44/SOT1

VCC

P45/SIN1

P46/ADTG

P47/SCK0

RST

PA1/OUT3

PA0/OUT2

P97/PPG5

P96/PPG4

P95/PPG3

P94/PPG2

P93/PPG1

P92/PPG0

P91/OUT1

P90/OUT0

P87/IN3

P86/IN2

P85/IN1

P84/IN0

P83/TOT1

P82/TOT0

P81/TIN1

P80/TIN0

P77/IRQ7

P76/IRQ6

P75/IRQ5

P74/IRQ4

P73/IRQ3

P72/IRQ2

100

P21/A17

P20/A16

P17/AD15

P16/AD14

P15/AD13

P14/AD12

P13/AD11

P12/AD10

P11/AD09

P10/AD08

P07/AD07

P06/AD06

P05/AD05

P04/AD04

P03/AD03

P02/AD02

P01/AD01

P00/AD00

VCC

VSS

PA4/CKOT

PA3

PA2

P50/SDA0/SOT0

P51/SCL0/SIN0

P52/SDA1

P53/SCL1

P54/SDA2

P55/SCL2

AVCC

AVRH

AVRL

AVSS

P60/AN0

P61/AN1

P62/AN2

P63/AN3

VSS

P64/AN4

P65/AN5

P66/AN6

P67/AN7

P70/IRQ0

P71/IRQ1

MD0

MD1

MD2

HST

MB90550A/550B Series

DS07-13706-6E 7

■PIN DESCRIPTION

(Continued)

Pin no. Pin name Circuit type Function

QFP LQFP

82 80 X0 A Oscillation pin

83 81 X1 A Oscillation pin

77 75 RST B Reset input pin

52 50 HST C Hardware standby input pin

85 to 92 83 to 90 P00 to P07 D

(CMOS)

General-pur pose I/O ports.

A pull-up resistor can be added (RD07 to RD00 = 1) by using

the pull-up resistor setting register (RDR0).

D07 to D00 = 1: Disabled when the port is set for output.

AD00 to

AD07 Serve as lower data I/O/lower address output (AD00 to AD07)

pins in the external bus mode.

93 to

100 91 to 98 P10 to P17 D

(CMOS)

General-pur pose I/O ports.

A pull-up resistor can be added (RD17 to RD10 = 1) by using the

pull-up resistor setting register (RDR1).

D17 to D10 = 1: Disabled when the port is set for output.

AD08 to

AD15 Serve as upper dat a I/O/middle address output ( AD08 to AD15)

pins in the 16-bit bus-width, external bus mode.

1 to 8 99,100,

1 to 6

P20 to P27 E

(CMOS)

General-pur pose I/O ports.

This function is enabled either in single-chip mod e or with the

external address output control register set to “Port”.

A16 to A23 External address bus A16 to A23 output pins.

This function is enabled in an external-bus enabled mode with

the external address output register set to “Address”.

97 P30 E

(CMOS)

General-pur pose I/O port.

This function is enabled in single-chip mode.

ALE Address latch enable output pin.

This function is enabled in an external-bus enabled mode.

10 8 P31 E

(CMOS)

General-pur pose I/O port.

This function is enabled in single-chip mode.

RD Read strobe output pin for the data bus.

This function is enabled in an external-bus enabled mode.

12 10 P32 E

(CMOS)

General-pur pose I/O port.

This function is enabled in single-chip mode.

WRL Write strobe output pin for the lower eight bits of the data bus.

This function is enabled in an external-bus enabled mode.

13 11 P33 E

(CMOS)

General-pur pose I/O port.

This function is enabled in single-chip mode.

WRH Write strobe output pin for the upper ei ght bits of the data bus.

This function is enabled in an external-bus enabled mode.

MB90550A/550B Series

8DS07-13706-6E

(Continued)

Pin no. Pin name Circuit type Function

QFP LQFP

14 12 P34 E

(CMOS)

General-purpose I/O port.

This function is enabled in single-chip mode

HRQ Hold request input pin.

This function is enabled in an exter nal-bus enabled mode .

15 13 P35 E

(CMOS)

General-purpose I/O port.

This function is enabled in single-chip mode.

HAK Hold acknowledge output pin.

This function is enabled in an exter nal-bus enabled mode .

16 14 P36 E

(CMOS)

General-purpose I/O port.

This function is enabled in single-chip mode.

RDY Ready signal input pi n.

This function is enabled in an exter nal-bus enabled mode .

17 15 P37 E

(CMOS)

General-purpose I/O port.

This function is enabled in single-chip mode.

CLK CLK output pin.

This function is enabled in an exter nal-bus enabled mode .

18 16 P40 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD40 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D40 = 0: Disabled when the po rt is set for input.)

SCK UART serial clock I/O pin.

This function is enabled with the UART clock output enabled.

19 17 P41 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD41 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D41 = 0: Disabled when the po rt is set for input.)

SOT UART serial data output pin.

This function is enabled with the UART serial data output enabled.

20 18

P42 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD42 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D42 = 0: Disabled when the por t is set for input.)

SIN UART serial data input pin. Since this input is used as required while

the UART is operating for input, the output by any other function

must be off unless used intentionally.

21 19 P43 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD43 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D43 = 0: Disabled when the por t is set for input.)

SCK1 Extended I/O serial clock I/O pin. This function is enabled with the

extended I/O serial clock output enabled.

MB90550A/550B Series

DS07-13706-6E 9

(Continued)

Pin no. Pin name Circuit type Function

QFP LQFP

22 20

P44 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD44 = 1) depending on

the setting of the open-drain control settin g register (ODR4).

(D44 = 0: Disabled when the po rt is set for input.)

SOT1 Extended I/O serial data output pin.

This function is enabled wit h the extended I /O serial data output

enabled.

24 22

P45

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD45 = 1) depending on

the setting of the open-drain control settin g register (ODR4).

(D45 = 0: Disabled when the po rt is set for input.)

SIN1

Extended I/O serial data input pin.

Since this input is used as requi red while the extended I/O serial

interface is operating for input, the output by any oth er function

must be off unless used intentionally.

25 23

P46

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD46 = 1) depending on

the setting of the open-drain control settin g register (ODR4).

(D46 = 0: Disabled when the po rt is set for input.)

ADTG

A/D converter external trigger input pi n.

Since this input is used as required while the A/D converter is op-

erating for inp ut, the output by an y other functio n must be off un -

less used intentionally.

26 24 P47 F

(CMOS/H)

General-purpose I/O port.

Serves as an open-drain output port (OD47 = 1) depending on

the setting of the open-drain control settin g register (ODR4).

D47 = 0: Disabled when the port is set for input.

SCK0 Extended I/O serial clock I/O pin. This function is enabled with

the extended I/O serial clock output enabled.

27 25 C — Capacitance pin for regulati ng the power supply.

Connect an exte rnal ceramic capacitor o f about 0.1 µF.

28 26

P50

(NchOD/H)

N-channel open-drain I/O port.

SDA0

I2C interface data I/O pin.

This function is enabled with the I2C interface enab le d for

operation.

While the I2C interface is operating, place the port output in the

Hi-Z state (PDR = 1).

SOT0 Extended I/O serial data output pin.

This function is enabled wit h the extended I /O serial data output

enabled.

MB90550A/550B Series

10 DS07-13706-6E

(Continued)

Pin no. Pin name Circuit type Function

QFP LQFP

29 27

P51

(NchOD/H)

N-channel open-drain I/O port.

SCL0

I2C interface clock I/O pin. This functi on is enabled with the

I2C interface enabled f or operation.

While the I2C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

SIN0

Extended I/O serial data input pin.

Since this input is used as required while the extended I/O

serial interface is operating for input, the output by any other

function must be off unless used intentionally.

30,32 28,30

P52,P54

(NchOD/H)

N-channel open-drain I/O ports.

SDA1,SDA2 I2C interface data I/O pins. This function is enabled with the

I2C interface enabled for operation.

While the I2C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

31,33 29,31

P53,P55

(NchOD/H)

N-channel open-drain I/O ports.

SCL1,SCL2 I2C interface clock I/O pins. This function is enabled with the

I2C interface enabled for operation.

While the I2C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

38 to 41,

43 to 46 36 to 39,

41 to 44

P60 to P67 H

(CMOS/H)

General-purpo se I/O ports.

AN0 to AN7 A/D conv erter analog input pin. This function is enabled with

the analog input enabled.

47,48,

53 to 58 45,46,

51 to 56

P70 to P77

(CMOS/H)

General-purpo se I/O ports.

IRQ0 to IRQ7 External interrupt request input pins.

Since this input is used as required while external interrupts

remain enabled, the output by an y ot her functio n must be off

unless used intention ally.

59,60 57,58

P80,P81

(CMOS/H)

General-purpo se I/O ports.

TIN0,TIN1 Reload timer event input pins.

Since this input is used as required while the reload timer is

operating for input, the output by any ot her function must be

off unless used intentionally.

61,62 59,60 P82,P83 J

(CMOS/H)

General-purpo se I/O ports.

TOT0,TOT1 Reload timer output pins.T his function is enable d with reload

timer output enabled.

63 to 66 61 to 64

P84 to P87

(CMOS/H)

General-purpo se I/O ports.

IN0 to IN3

Input capture trigger input pins.

Since this input is used as required while the input captur e

unit is operating for input, the output by any other function

must be off unless used intentionally.

67,68 65,66 P90,P91 J

(CMOS/H) General-pur pose I/O ports.

OUT0,OUT1 Output compare event output pins.

MB90550A/550B Series

DS07-13706-6E 11

(Continued)

Pin no. Pin name Circuit type Function

QFP LQFP

69 to 74 67 to 72 P92 to P97 J

(CMOS/H)

General-purpose I/O ports.

PPG0 to

PPG5 PPG output pins. This function is enable d with the PPG output

enabled.

75,76 73,74 PA0,PA1 J

(CMOS/H) General-pur pose I/O port s.

OUT2,OUT3 Output compare event output pins.

78,79 76,77 PA2,PA3 J

(CMOS/H) General-pur pose I/O port s.

80 78 PA4 J

(CMOS/H) General-purpose I/O port.

CKOT Serves as the CKOT output while the CKOT is operating.

34 32 AVCC ⎯A/D converter power-supp ly pin.

35 33 AVRH ⎯A/D converter external reference voltage source pin.

36 34 AVRL ⎯A/D converter external reference voltage source pin.

37 35 AVSS ⎯A/D converter power-supply pin.

49,50 47,48 MD0,MD1 C Operation mode setting input pins.

Connect these pins directly to Vcc or Vss.

51 49 MD2 KOperation mode setting input pin.

Connect this pin dire ctly to Vcc or Vss. (MB90552A/552B/553A/

553B/V550A)

COperation mode setting input pin.

Connect this pin directly to Vcc or Vss. (MB90P553A/F553A)

23,84 21,82 VCC ⎯Power (5 V) input pins.

11,42,

81 9,40,

79 VSS ⎯Power (0 V) input pins.

MB90550A/550B Series

12 DS07-13706-6E

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• 3 MHz to 32 MHz

• Oscillator recove ry resistor approx. 1MΩ

• CMOS level hysteresis input

• Pull-up resistor provided

Resistor: About 50 kΩ

C• CMOS level hysteresis input

• CMOS level output

• CMOS level input

• Standby control provided

• Input pull-up resistor control provided

Resistor: About 50 kΩ

HARD,SOFT

STANDBY

CONTROL

Clock input

HARD,SOFT

STANDBY

CONTROL

Digital input

Digital output

Pull-up resistor control

MB90550A/550B Series

DS07-13706-6E 13

(Continued)

Type Circuit Remarks

• CMOS level output

• CMOS level input

• Standby control provided

• CMOS level output

• CMOS level hysteresis input

• Open-drain control provided

• N-channel open-drain output

• CMOS level hysteresis input

• Standby control provided

Note: Unlike normal CMOS I/O pins, this

pin is not provided with an y P-channel

transistor. There fore the pin does not allow

a current to flow to the Vcc side even when

applied with a voltage from an external

device with the IC’s powe r su pp ly left off.

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

• Analog input

HARD,SOFT

STANDBY

CONTROL

Digital output

Digital input

HARD,SOFT

STANDBY

CONTROL

Digital input

Open- drain

control

signal

HARD,SOFT

STANDBY

CONTROL

Digital output

Digital input

HARD,SOFT

STANDBY

CONTROL

A/D

DISABLE

Digital output

Analog input

Digital input

MB90550A/550B Series

14 DS07-13706-6E

(Continued)

Type Circuit Remarks

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

• CMOS level hysteresis input

• Pull-up resistor provided

Resistor: About 50 kΩ

HARD

STANDBY

CONTROL

Digital output

Digital input

HARD,SOFT

STANDBY

CONTROL

Digital output

Digital input

MB90550A/550B Series

DS07-13706-6E 15

■HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may cause latchup in the following situations:

• When a voltage higher than Vcc or lower than Vss is applied to input or output pins .

• When a voltage exceeding the rating is applied between Vcc and Vss.

• When AVcc power is supplied pr io r to th e Vcc voltage.

If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the

device. Use meticulous care not to let it occur.

F or the same reason, also be careful not to let the an alog power- supply volta ge exceed the digital pow er-supply

voltage.

2. Handling unused input pins

Lea ving unused input pins open ma y cause a malfunction or latch-up which leads to fa tal damage to the de vice.

Therefore they must be pulled up or pulled down through at least 2 kΩ resistance. Also, unused input/output

pins should be left open in output state or handled in the same way as unused input pins.

3. Notes on Using External Clock

In using the external clock, driv e X0 pin only and leave X1 pin open.

4. Power Supply Pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, the pins should be connected to external power and

ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by

the rise in the ground level, and to conform to the total current rating.

Make sure to connect VCC and VSS pins via lowest impedance to power lines.

It is recommended that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the

device.

•Using external clock MB90550A/550B series

Open

VCC

VSS

•Using power supply pins

MB90550A/550B

series

MB90550A/550B Series

16 DS07-13706-6E

5. Crystal Oscillator Circuit

Noise around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via shortest

distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines

of oscillation circuit do not cross the lines of other circuits.

A printed circuit board artwork surrounding the X0 and X1 pins with grand area for stabilizing the operation is

highly recommended.

6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D conv erter power supply (AVCC, A VRH, AVRL) and analog inputs ( AN0 to AN7) after

turning-on the digital power supply (VCC).

Tur n-off the dig ital power after tu r nin g off t he A/D co nver te r supp ly and analog in puts. In this ca se, make sure

that AVRH does not e xceed A V CC (turning on/off the an alog and digital pow er supplies simultaneously is accept-

able).

7. Connection of Unused Pins of A/D Conver ter

Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

8. N.C. Pin

The N.C. (internally connected) pin must be opened for use.

9. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

µs or more.

10. Indeterminate outputs from ports 0 and 1

The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during

a pow er-on reset) afte r the pow er is turned on. (MB90552A, MB90552B , MB90553A, MB90553B, MB90F553A,

MB90V550A)

The series without built-in step-down circuit has no oscillation setting time of step-down circuit, so outputs should

not become indeterminate. (MB90P553A)

Oscillation setting time *2

VCC (power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operating clock A) signal

KB (internal operating clock B) signal

PORT (port output) signal

Step-down circuit setting time *1

Period of indeterminate

*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation cloc k frequency of 16 MHz: 8.19 ms)

*2: Oscillation setting time 218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)

Timing chart of indeterminate outputs from ports 0 and 1

MB90550A/550B Series

DS07-13706-6E 17

11. Initialization

In the device, there are internal registers initialized only by a power-on reset. To initialize these registers, tur n

on the power ag ain.

12. Return from standby state

If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may

fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal

state.

13. Precautions for Use of “DIV A, Ri,” and “DIVW A, Ri” Instructions

The signed multiplication-division instructions “DIV A, Ri,” and “DIVW A, RWi” should be used when the corre-

sponding bank registers (DTB, ADB, USB, SSB) are set to value “00H.” If the corresponding bank registers (DTB,

ADB, USB , SSB) are set to a value other than “00H,” the remainder obtained after the e xecution of the instruction

will not be placed in the instruction operand register.

14. Using of REALOS

The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.

15. Caution on Operations during PLL Clock Mode

If the PLL cloc k m ode is selected in the microcont roller, it may att empt to contin ue the op eratio n using the fre e-

running frequency of the self oscillation circuit in the PLL circuitry even if the oscillator is out of place or the clock

input is stopped.

Performance of this operation, however, cannot be guaranteed.

MB90550A/550B Series

18 DS07-13706-6E

■BLOCK DIAGRAM

X0, X1

RST

HST

P00 to P07/

AD00 to AD07

P10 to P17/

AD08 to AD15

P20 to P27/

A16 to A23

P30/ALE

P31/RD

P32/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

CKOT/PA4

PA2, PA3

OUT2, OUT3/

PA0, PA1

PPG5/P97

PPG4/P96

PPG3/P95

PPG2/P94

PPG1/P93

PPG0/P92

OUT0, OUT1/

P90, P91

IN0 to IN3/

P84 to P87

T OT0, T O T1/

P82, P83

TIN0, TIN1/

P80, P81

IRQ0 to IRQ7/

P70 to P77

AN0 to AN7/

P60 to P67

AVRH, AVRL

P40/SCK

P41/SOT

P42/SIN

P43/SCK1

P44/SOT1

P45/SIN1

P46/ADTG

P47/SCK0

P50/SDA0/SOT0

P51/SCL0/SIN0

P52/SDA1

P53/SCL1

P54/SDA2

P55/SCL2

ROM

RAM

UART

Clock control

circuit*

Port 0

Port 1

Port 2

Port 3

Port 4

Communication prescaler

Extended I/O

serial interface 1

Extended I/O

serial interface 0

I2C interface 0

I2C interface 1

Port 5

CPU

Core of F2MC-16LX

family

Interrupt controller

Port A

Clock monitor function

Port 9

8/16 PPG ×

3 channels

I/O timer

16-bit output compare

unit x 4 channels

16-bit input capture

unit x 4 channels

16-bit free-run timer

16-bit reload timer

x 2 channels

Port 8

Port 7

External inter rupt

A/D converter

(8/10 bits)

Port 6

Note: Specifications of evaluation model

(MB90V550A)

Contains no internal ROM.

Contains 6 KB of internal RAM.

Contains the same internal resources

as the other products in the MB90550A/

550B series.

MB90550A/550B Series

DS07-13706-6E 19

*: The cloc k control circuit contain s a watchdog timer, time-base timer , and a low po wer consumption control circuit.

Note : P00 to P07 (8 pins): Input pull-up resistor setting register provided

P10 to P17 (8 pins): Input pull-up resistor setting register provided

P40 to P47 (8 pins): Open-d rain control setting register provided

P50 to P55 (6 pins): N-channel ope n drain

Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports.

MB90550A/550B Series

20 DS07-13706-6E

■MEMORY MAP

The R OM data of bank FF is reflect ed in the upper addre ss of bank 00, realizing eff ectiv e use of the C compiler

small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address,

enabling reference of the ta ble on the ROM without stating “far”.

For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed.

Since the R OM area of the FF bank e xceeds 48 Kb ytes , the whole a rea cannot be refl ected in the image fo r the

00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH.

Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.

RAM RAM RAM

: Internal access memory

: External access memory

: Inhibited area

Single chip mode

A mirror function

is supported

Internal ROM

external bus mode

A mirror function

is supported

External ROM

external bus mode

FFFFFFH

FF0000H

010000H

Address#1

Address#2

Address#3

004000H

002000H

000100H

0000C0H

0000D0H

ROM

area

ROM

area

ROM area

(image of

bank FF)

ROM area

(image of

bank FF)

Peripheral Peripheral Peripheral

RegisterRegisterRegister

Parts No. Address#1 Address#2 Address#3

MB90552A/552B FF0000H004000H000900H

MB90553A/553B FE0000H004000H001100H

MB90F553A FE0000H004000H001100H

MB90P553A FE0000H004000H001100H

MB90V550A (FE0000H) 004000H001900H

MB90550A/550B Series

DS07-13706-6E 21

■F2MC-16LX CPU PROGRAMMING MODEL

• Dedicated registers

AH AL

USP

SSP

DPR

PCB

DTB

USB

SSB

ADB

8 bit

16 bit

32 bit

: Accumulator (A)

Dual 16-bit register used for storing results of calculation, etc. The two 16-bit

registers can be combined and use d as a 32-bit register.

: Additional data bank register (ADB)

The 8-bit register indicating the additional data space.

: User stack bank register (USB)

The 8-bit register indicating the user stack space.

: System stack pointer (SSP)

The 16-bit pointer indicating the status of the system stack address.

: Processor status (PS)

The 16-bit register indicating the system status.

: Program bank register (PCB)

The 8-bit register indicating the program space.

: Data bank register (DTB)

The 8-bit register indicating the data space.

: Program counter (PC)

The 16-bit register indicating storing location of the current instruction code.

: Direct page register (DPR)

The 8-bit register indicating bits 8 through 15 of the operand address in the short

direct addressing mode.

: System stack bank register (SSB)

The 8-bit register indicating the system stack space.

: User stack pointer (USP)

The 16-bit pointer indicating a user stack address.

MB90550A/550B Series

22 DS07-13706-6E

■I/O MAP

(Continued)

Address Register name Abbreviated

00HPort 0 data register PDR0 R/W Port 0 XXXXXXXX

01HPort 1 data register PDR1 R/W Port 1 XXXXXXXX

02HPort 2 data register PDR2 R/W Port 2 XXXXXXXX

03HPort 3 data register PDR3 R/W Port 3 XXXXXXXX

04HPort 4 data register PDR4 R/W Port 4 XXXXXXXX

05HPort 5 data register PDR5 R/W Port 5 _ _ 1 1 1 1 1 1

06HPort 6 data register PDR6 R/W Port 6 XXXXXXXX

07HPort 7 data register PDR7 R/W Port 7 XXXXXXXX

08HPort 8 data register PDR8 R/W Port 8 XXXXXXXX

09HPort 9 data register PDR9 R/W Port 9 XXXXXXXX

0AHPort A data register PDRA R/W Port A _ _ _XXXXX

0BH to

0FH(Disabled)

10HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0

11HPort 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0

12HPort 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0

13HPort 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0

14HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0

15H(Disabled)

16HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0

17HPort 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0

18HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0

19HPort 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0

1AHPort A direction register DDRA R/W Port A _ _ _ 0 0 0 0 0

1BHPort 4 output pin register ODR4 R/W Port 4 0 0 0 0 0 0 0 0

1CHPort 0 resistor setting register RDR0 R/W Port 0 0 0 0 0 0 0 0 0

1DHPort 1 resistor setting register RDR1 R/W Port 1 0 0 0 0 0 0 0 0

1EH(Disabled)

1FHAnalog input enable register ADER R/W Port 6,

A/D converter 1 1 1 1 1 1 1 1

20HSerial mode register SMR R/W

UART

0 0 0 0 0 0 0 0

21HSerial control register SCR R/W 0 0 0 0 0 10 0

22HSerial input data register /

serial output data register SIDR/SODR R/W XXXXXXXX

23HSerial status register SSR R/W 0 0 0 0 1 _ 0 0

MB90550A/550B Series

DS07-13706-6E 23

(Continued)

Address Register name Abbreviated

24HSerial mode control status

serial interface 0

_ _ _ _ 0 0 0 0

25HSerial mode control status

26HSerial data register 0 SDR0 R/W XXXXXXXX

27HClock frequency-divider control

prescaler 0 _ _ _ 1 1 1 1

28HSerial mode control status

serial interface 1

_ _ _ _ 0 0 0 0

29HSerial mode control status

2AHSerial data register 1 SDR1 R/W XXXXXXXX

2BH(Disabled)

2CHI2C bus status register 0 IBSR0 R

I2C interface 0

0 0 0 0 0 0 0 0

2DHI2C bus control register 0 IBCR0 R/W 0 0 0 0 0 0 0 0

2EHI2C bus clock select register 0 ICCR0 R/W _ _ 0XXXXX

2FHI2C bus address register 0 IADR0 R/W _ XXXXXXX

30HI2C bus data register 0 IDAR0 R/W XXXXXXXX

31H(Disabled)

32HI2C bus status register 1 IBSR1 R

I2C interface 1

0 0 0 0 0 0 0 0

33HI2C bus control register 1 IBCR1 R/W 0 0 0 0 0 0 0 0

34HI2C bus clock select register 1 ICCR1 R/W _ _ 0XXXXX

35HI2C bus address register 1 IADR1 R/W _ XXXXXXX

36HI2C bus data register 1 IDAR1 R/W XXXXXXXX

37HI2C bus port select register ISEL R/W _ _ _ _ _ _ _ 0

38HInterrupt/DTP enable register ENIR R/W

DTP/external

interrupt

0 0 0 0 0 0 0 0

39HInterrupt/DTP factor register EIRR R/W XXXXXXXX

3AHRequest level setting register ELVR R/W 0 0 0 0 0 0 0 0

3BH0 0 0 0 0 0 0 0

3CHControl status register ADCS0 R/W

A/D convertor

0 0 0 0 0 0 0 0

3DHADCS1 R/W! 0 0 0 0 0 0 0 0

3EHData register ADCR0 R XXXXXXXX

3FHADCR1 R/W! 0 0 0 0 1 _XX

MB90550A/550B Series

24 DS07-13706-6E

(Continued)

Address Register name Abbreviated

40HReload register L (ch.0) PRLL0 R/W

8/16-bit PPG0/1

XXXXXXXX

41HReload register H (ch.0) PRLH0 R/W XXXXXXXX

42HReload register L (ch.1) PRLL1 R/W XXXXXXXX

43HReload register H (ch.1) PRLH1 R/W XXXXXXXX

44HPPG0 operating mode control

45HPPG1 operating mode control

46HPPG0 and 1 output control

47H(Disabled)

48HReload register L (ch.2) PRLL2 R/W

8/16-bit PPG2/3

XXXXXXXX

49HReload register H (ch.2) PRLH2 R/W XXXXXXXX

4AHReload register L (ch.3) PRLL3 R/W XXXXXXXX

4BHReload register H (ch.3) PRLH3 R/W XXXXXXXX

4CHPPG2 operating mode control

4DHPPG3 operating mode control

4EHPPG2 and 3 output control

4FH(Disabled)

50HReload register L (ch.4) PRLL4 R/W

8/16-bit PPG4/5

XXXXXXXX

51HReload register H (ch.4) PRLH4 R/W XXXXXXXX

52HReload register L (ch.5) PRLL5 R/W XXXXXXXX

53HReload register H (ch.5) PRLH5 R/W XXXXXXXX

54HPPG4 operating mode control

55HPPG5 operating mode control

56HPPG4 and 5 output control

57H(Disabled)

58HClock output enable register CLKR R/W Clock monitor

function _ _ _ _ 0 0 0 0

59H(Disabled)

MB90550A/550B Series

DS07-13706-6E 25

(Continued)

Address Register name Abbreviated

5AHControl status register 0 TMCSR0 R/W 16-bit

reload timer 0

0 0 0 0 0 0 0 0

5BH_ _ _ _ 0 0 0 0

5CH16 bit timer register 0/

16 bit reload register 0 TMR0/

TMRLR0 R/W XXXXXXXX

5DHXXXXXXXX

5EHControl status register 1TMCSR1 R/W 16-bit

reload timer 1

0 0 0 0 0 0 0 0

5FH_ _ _ _ 0 0 0 0

60H16 bit timer re gister 1/

16 bit reload register 1 TMR1/

TMRLR1 R/W XXXXXXXX

61HXXXXXXXX

62HInput capture register,

channel-0 lower bits IPCP0 R

16-bit

I/O timer

Input captur e

(ch.0 to ch.3)

XXXXXXXX

63HInput capture register,

channel-0 upper bits XXXXXXXX

64HInput capture register,

channel-1 lower bits IPCP1 R XXXXXXXX

65HInput capture register,

channel-1 upper bits XXXXXXXX

66HInput capture register,

channel-2 lower bits IPCP2 R XXXXXXXX

67HInput capture register,

channel-2 upper bits XXXXXXXX

68HInput capture register,

channel-3 lower bits IPCP3 R XXXXXXXX

69HInput capture register,

channel-3 upper bits XXXXXXXX

6AHInput capture control

status register ICS01 R/W 0 0 0 0 0 0 0 0

6BHInput capture control

status register ICS23 R/W 0 0 0 0 0 0 0 0

6CHTimer data register, lower bits TCDT R/W 16-bit

I/O timer

free run timer

0 0 0 0 0 0 0 0

6DHTimer data register, upper bits R/W 0 0 0 0 0 0 0 0

6EHTimer control status register TCC S R/W 0 0 0 0 0 0 0 0

6FHRO M mirroring function

selection register ROMM W ROM mirroring

function _ _ _ _ _ _ _ 1

MB90550A/550B Series

26 DS07-13706-6E

(Continued)

Address Register name Abbreviated

70HCompare register,

channel-0 lower bits OCCP0 R/W

16-bit

I/O timer

output compare

(ch.0 to ch.3)

XXXXXXXX

71HCompare register,

channel-0 upper bits XXXXXXXX

72HCompare register,

channel-1 lower bits OCCP1 R/W XXXXXXXX

73HCompare register,

channel-1 upper bits XXXXXXXX

74HCompare register,

channel-2 lower bits OCCP2 R/W XXXXXXXX

75HCompare register,

channel-2 upper bits XXXXXXXX

76HCompare register,

channel-3 lower bits OCCP3 R/W XXXXXXXX

77HCompare register,

channel-3 upper bits XXXXXXXX

78HCompare control status

79HCompare control status

7AHCompare control status

7BHCompare control status

7CH to

9DH(Disabled)

9EHProgram address detection

control register PACSR R/W Address match

detection function 0 0 0 0 0 0 0 0

9FHDelayed interrupt factor

generation/cancellation register DIRR R/W Delayed

interrupt _ _ _ _ _ _ _ 0

A0HLow-power consumption mode

control register LPMCR R/W! Low power

consumption control

circuit

0 0 0 1 1 0 0 0

A1HClock select register CKSCR R/W! 1 1 1 1 1 1 0 0

A2H to

A4H(Disabled)

A5HAutomatic ready function select

External bus pin

control circuit

0 0 1 1 _ _ 0 0

A6HExternal address output

control register HACR W 0 0 0 0 0 0 0 0

A7HBus control signal select

MB90550A/550B Series

DS07-13706-6E 27

(Continued)

Address Register name Abbreviated

A8HWatchdog timer control register WDTC R/W! Watchdog timer XXXXX 1 1 1

A9HTimebase timer control register TBTC R/W! Timebase timer 1 _ _ 0 0 1 0 0

AAH to

ADH(Disabled)

AEHFlash memory control status

interface circuit 0 0 0 0 0 _ _ 0

AFH(Disabled)

B0HInterrupt control register 00 ICR00 R/W!

Interrupt controller

0 0 0 0 0 1 1 1

B1HInterrupt control register 01 ICR01 R/W! 0 0 0 0 0 1 1 1

B2HInterrupt control register 02 ICR02 R/W! 0 0 0 0 0 1 1 1

B3HInterrupt control register 03 ICR03 R/W! 0 0 0 0 0 1 1 1

B4HInterrupt control register 04 ICR04 R/W! 0 0 0 0 0 1 1 1

B5HInterrupt control register 05 ICR05 R/W! 0 0 0 0 0 1 1 1

B6HInterrupt control register 06 ICR06 R/W! 0 0 0 0 0 1 1 1

B7HInterrupt control register 07 ICR07 R/W! 0 0 0 0 0 1 1 1

B8HInterrupt control register 08 ICR08 R/W! 0 0 0 0 0 1 1 1

B9HInterrupt control register 09 ICR09 R/W! 0 0 0 0 0 1 1 1

BAHInterrupt control register 10 ICR10 R/W! 0 0 0 0 0 1 1 1

BBHInterrupt control register 11 ICR11 R/W! 0 0 0 0 0 1 1 1

BCHInterrupt control register 12 ICR12 R/W! 0 0 0 0 0 1 1 1

BDHInterrupt control register 13 ICR13 R/W! 0 0 0 0 0 1 1 1

BEHInterrupt control register 14 ICR14 R/W! 0 0 0 0 0 1 1 1

BFHInterrupt control register 15 ICR15 R/W! 0 0 0 0 0 1 1 1

C0H to

FFH(External area)

100H to

#H(RAM area)

#H to

1FEFH(Reserved area)

MB90550A/550B Series

28 DS07-13706-6E

(Continued)

• Initial value representations

0: Initial value of 0

1: Initial value of 1

X: Initial value undefined

_: Initial value undefined (none)

• Addresses that follow 00FFH are the reserved areas.

• The boundary #H between the RAM and reserved area s is different depending on each product.

Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset.

Notice that it is not the value read from the bit.

The LPMCR, CKSCR, and WDTC registers ma y be initialized or not initializ ed, depending on the type of the

reset. Their initial values in the above list are those to which the regis te rs ar e init ialized.

“R/W!” in the access column indicates that the register contains read-only or write-only bits.

If a read-modif y-write instruction (such as a bit setting instruction) is used to access a register marked “R/

W!”, or “W” in the access column, the bit focused on by the instruction is set to the desired value but a

malfunction occurs if the other bits contain a write-only bit. Do not use such instructions to access those

registers.

Address Register name Abbreviated

1FF0HProgr am address detect ion

PADR0

R/W

Address match

detection function

XXXXXXXX

1FF1HProgr am address detect ion

1FF2HProgr am address detect ion

1FF3HProgr am address detect ion

PADR1

R/W XXXXXXXX

1FF4HProgr am address detect ion

1FF5HProgr am address detect ion

1FF6H to

1FFFH(Reserved ar ea )

MB90550A/550B Series

DS07-13706-6E 29

■INTERR UPT FACTORS

INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS

:The interrupt request flag is cleared by the EI2OS interrupt clear signal. The stop request is available.

:The interrupt request flag is cleared by the EI2OS interrupt clear signal.

:The interrupt requ est flag is not cleared by the EI2OS interrupt clear signal.

Interrupt source EI2OS

support Interrupt vectors Interrupt control registers

Number Address ICR Address

Reset ×# 08 FFFFDCH——

INT9 instruction ×# 09 FFFFD8H——

Exception ×# 10 FFFFD4H——

A/D converter # 11 FFFFD0HICR00 0000B0H

Timebase timer ×# 12 FFFFCCH

DTP0 (external interrupt 0) # 13 FFFFC8HICR01 0000B1H

DTP4/5 (external interrupt 4/5) # 14 FFFFC4H

DTP1 (external interrupt 1) # 15 FFFFC0HICR02 0000B2H

8/16-bit PPG timer 0 co un te r bo rr ow ×# 16 FFFFBCH

DTP2 (external interrupt 2) # 17 FFFFB8HICR03 0000B3H

8/16-bit PPG timer 1 counter borrow ×# 18 FFFFB4H

DTP3 (external interrupt 3) # 19 FFFFB0HICR04 0000B4H

8/16-bit PPG timer 2 counter borrow ×# 20 FFFFACH

Extended I/O serial interface 0 # 21 FFFFA8HICR05 0000B5H

8/16-bit PPG timer 3 counter borrow ×# 22 FFFFA4H

Extended I/O serial interface 1 # 23 FFFFA0HICR06 0000B6H

16-bit free-run timer (I/O timer) overflow # 24 FFFF9CH

16-bit re-load timer 0 # 25 FFFF98HICR07 0000B7H

DTP6/7 (external interrupt 6/7) # 26 FFFF94H

16-bit re-load timer 1 # 27 FFFF90HICR08 0000B8H

8/16-bit PPG timer 4/5 counter borrow ×# 28 FFFF8CH

Input capture (ch.0) include (I/O timer) # 29 FFFF88HICR09 0000B9H

Input capture (ch.1) include (I/O timer) # 30 FFFF84H

Input capture (ch.2) include (I/O timer) # 31 FFFF80HICR10 0000BAH

Input capture (ch.3) include (I /O timer) # 32 FFFF7CH

Output compare (ch.0) match (Output timer) #33 FFFF78HICR11 0000BBH

Output compare (ch.1) match (Output timer) # 34 FFFF74H

Output compare (ch.2) match (Output timer) # 35 FFFF70HICR12 0000BCH

Output compare (ch.3) match (Output timer) # 36 FFFF6CH

UART transmission complete # 37 FFFF68HICR13 0000BDH

I2C interface 0 ×# 38 FFFF64H

UART0 reception complete # 39 FFFF60HICR14 0000BEH

I2C interface 1 ×# 40 FFFF5CH

Flash memory status ×# 41 FFFF58HICR15 0000BFH

Delayed interrupt generation module ×# 42 FFFF54H

MB90550A/550B Series

30 DS07-13706-6E

Note: On using the EI2OS Function with Extended I/O Serial Interface 2

If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags

are cleared by the EI2OS interrupt clear signal. When the EI2OS function is used for one of the two

interrupt sources, theref ore, the other interrupt function cannot be used. Set t he inter rupt request ena b l e

bit for the relevant resource to “0” for software polling processing.

Interrupt source Interrupt No. Interrupt control register Resource interrupt reques t

Extended I/O serial interface 1 # 23 ICR06 Enabled

16-bit free-run timer

(I/O timer) overflow # 24 Disabled

MB90550A/550B Series

DS07-13706-6E 31

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V)

*1 : Care must be taken that AVcc, AVRH, AVRL do not exceed Vcc.

Also, care must be taken that AVRH and AVRL do not exceed AVCC, and AVRL does not exceed AVRH.

*2 : The maximum output current is a peak value for a corresponding pin.

*3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.

*5 : VI and VO should not exceed VCC + 0.3V.

*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P67, P70 to P77,

P80 to P87, P90 to P97, PA0 to PA4 (Continued)

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage

VCC VSS − 0.3 VSS + 6.0 V

AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC *

AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH ≥ AVRL

AVRL VSS − 0.3 VSS + 6.0 V

Input voltage VIVSS − 0.3 VSS + 6.0 V *5

Output voltage VOVSS − 0.3 VSS + 6.0 V *5

Maximum clamp current ICLAMP − 2.0 + 2.0 mA MB90552A/2B/3A/3B*6

− 200 + 200 µA MB90F553A*6

Total maximum clamp current Σ| ICLAMP |⎯20 mA MB90552A/2B/3A/3B*6

⎯2 mA MB90F553A*6

“L” level maximum output cur rent *2IOL1 ⎯10 mA Other than P20 to P27

IOL2 ⎯20 mA P20 to P27

“L” level average output current IOLAV1 ⎯4 mA Other than P20 to P27

IOLAV2 ⎯12 mA P20 to P27

“L” level total maximum output current ΣIOL ⎯150 mA

“L” level total average output current ΣIOLAV ⎯80 mA

“H” level maximum output current *2IOH ⎯−15 mA

“H” level average output current *3IOHAV ⎯−4mA

“H” level total maximum output curr ent ΣIOH ⎯−100 mA

“H” level total average outpu t current *4ΣIOHAV ⎯−50 mA

Power consumption PD⎯

550 mW MB90P553A

450 mW MB90F553A

200 mW MB90553A/553B

180 mW MB90552A/552B

Operating temperature TA−40 +85 °C

Storage temperature TSTG −55 +150 °C

MB90550A/550B Series

32 DS07-13706-6E

(Continued)

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• Set the value of the limiting resistance as the current to be input to the microcontroller at +B input is below

the rated value, either instantaneously or for the prolonged periods.

• Note that when the microcontroller driv e current is low, such as in the power saving modes, the +B input

potential may p ass through the protective diode and increase the pote ntial at the VCC pin, and this may

affect other de vice s.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplet e operation may result.

• Note that is the +B input is applied during power-on, the power supply is provided from the pins and r esulting

supply voltage may not be sufficient to opera te the power-on reset.

• Care mu st be taken not to leave the +B input pin open.

• Note that analog system input/output pins other th an the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits :

Note: Aver age output current = operating current × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

+B input (0 V to 16 V)

Limiting

resistance

Protective diode

• Input/output equivalent circuits

MB90550A/550B Series

DS07-13706-6E 33

2. Recommended Operating Conditions (VSS = AVSS = 0.0 V)

* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to

be connected to the VCC pin must have a capa citance value higher than CS.

For connecting smoothing capacitor CS, see the diagram below:

WARNING: The recommended oper ating conditions are required in order to ensure the normal operation of

the semiconducto r device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating cond ition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data shee t. Users consider ing application outside th e listed cond itions are advised t o contact

their representatives before hand.

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage VCC

AVCC

4.5 5.5 V Normal operation (MB90F553A,

MB90P553A, MB 90 V5 50 A)

3.5 5.5 V Normal operation (MB90553A, MB90553B,

MB90552A, MB90552B)

3.5 5.5 V Retains status at the time of operation stop

Smoothing capacitor CS0.1 1.0 µF*

Operating temperature TA–40 +85 °C

CSVSS AVSS

• C pin connection circ uit

MB90550A/550B Series

34 DS07-13706-6E

3. DC Characteristics (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = –40 °C to +85 °C)

Parameter Symbol Pin name Condition Value Unit Remarks

Min Typ Max

“H” level input

voltage

VIH CMOS input pin — 0.7VCC —VCC+0.3 V *1

VIHS CMOS hysteresys input pin —0.8VCC —VCC+0.3 V *2

VIHM MD pin input — VCC − 0.3 — VCC+0.3 V *3

“L” level input

voltage

VIL CMOS input pin — VSS − 0.3 — 0.3VCC V*1

VILS CMOS hysteresys input pin —VSS − 0.3 — 0.2VCC V*2

VILM MD pin input — VSS − 0.3 — VSS +0.3 V *3

Open-dra in ou tp ut

pin voltage VDP50 to P55 — VSS – 0.3 — VSS + 6.0 V

“H” level output

voltage VOH Other than

P50 to P55 VCC = 4.5V,

IOH = −4.0mA VCC – 0.5 — — V

“L” level out put

voltage 1 VOL1 Othe r th an

P20 to P27 VCC = 4.5V,

IOL = 4.0mA ——0.4V

“L” level out put

voltage 2 VOL2 P20 to P27 VCC = 4.5V,

IOL = 12.0mA ——0.4V

Input leakage

current IIL All output pins VCC = 5.5V,

VSS < VI < VCC –5 — 5 µA

Power supply

current *4

ICC

VCC

Internal

operation at 16

MHz

VCC = 5.5 V

Normal opera-

tion

—3040mA

MB90V550A

—80110mA

MB90P553A

—6090mA

MB90F553A

—3040mA

MB90553A/B

—2535mA

MB90552A/B

When data writ-

ten in flash

mode — 100 150 mA MB90F553A

ICCS

Internal

operation at 16

MHz

VCC = 5.5 V

In sleep mode

—710mA

MB90V550A

—2530mA

MB90P553A

—1020mA

MB90F553A

—710mA

MB90553A/B

—710mA

MB90552A/B

ICCH VCC = 5.5V,

TA = +25°C

In stop mode

—520µAMB90V550A

—0.110µAMB90P553A

—520µAMB90F553A

—520µAMB90553A/B

—520µAMB90552A/B

Input

capacitance CIN Other than AVCC,

AVSS, C, VCC and VSS ——10—pF

Open-drain output

leakage curr en t Ileak P50 to P55 — — 0.1 5 µA

Pull-up

resistance RUP P0 0 to P07 and P10

to P17 (In pull-up

setting),RST —25 50 100 kΩOther than

MB90V550A

20 40 100 kΩMB90V550A

Pull-down

resistance RDOWN MD2 —25 50 100 kΩOnly for

mask ROM

product

MB90550A/550B Series

DS07-13706-6E 35

*1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37

*2 : X0, HST, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4

*3 : MD0, MD1 and MD2

*4 : The current value is preliminary value and may be subject to change for enhanced characteristics without

pre vious notice. The power supply current is measured with an external clock.

MB90550A/550B Series

36 DS07-13706-6E

4. AC Characteristics

(1) Clock Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

* : The fr equency fluctuation r ate is the maxim um de viation r ate of the preset center f requency when the multip lied

PLL signal is locked.

Parameter Symbol Pin name Value Unit Unit

Min Typ Max

Oscillation clock

frequency FCX0, X1 3 — 16 MHz

Oscillation clock

cycle time tCX0, X1 62.5 — 333 ns

Frequency fluctuation rate

locked* ∆f———5%

Input clock pulse width PWH

PWL X0 10 — — ns Recommended duty ratio

of 40% to 60%

Input clock rising/falling

time tCR, tCF X0 — — 5 ns External clock operation

Internal oper at ing cl oc k

frequency FCP —8.0 — 16 MHz PLL operation

1.5 — 16 MHz Main clock operation

Internal oper at ing cl oc k

cycle time tCP —62.5 — 125 ns PLL operation

62.5 — 666 ns Main clock operation

+α

−α

−

⎥ α ⎥

∆f = × 100 (%) Center frequency

• X0, X1 clock timing

tHCYL

tCF

PWH PWL tCR

0.8 VCC 0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

MB90550A/550B Series

DS07-13706-6E 37

The AC ratings are measured for the following measurement reference voltages.

5.5

4.5

3.5

1.5

34 8 16

1.5 3 8 12 16

PLL Operation guarantee

range

Internal operating clock frequency FCP (MHz)

Operation guarantee range

MB90F553A, MB90P553A,

MB90V550A

Relationship between oscillation clock frequency and internal operating clock frequency

Oscillation clock frequency FC (MHz)

• PLL operation guarantee range

Relationship between internal operatin g clock frequency and power supply voltage

Power supply voltage V

(V)

Multiplied-

by-4 Multiplied-

by-3 Multiplied-by-2 Multiplied-by-1

Not multiplied

Internal operating clock frequency FCP (MHz)

Operation guarantee range MB90553A/553B,

MB90552A/552B

0.8 VCC

0.2 VCC

2.4 V

0.8 V

0.7 VCC

0.3 VCC

• Input signal waveform • Output signal waveform

Hystheresis input pin Output pin

Pins other than hystheresis input / MD input

MB90550A/550B Series

38 DS07-13706-6E

(2) Clock Output Timing (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin name Value Unit Remarks

Min Max

Cycle time tCYC CLK 62.5 — ns

CLK ↑ → CLK ↓ time tCHCL tCP/2 − 20 tCP/2+20 ns

CLK

tCYC

2.4 V 2.4 V

0.8 V

tCHCL

MB90550A/550B Series

DS07-13706-6E 39

(3) Reset, Hardware Standby Input Timing (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

* : Oscillation time of oscillator is time that the amplitude reached the 90 %.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation

time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.

Parameter Symbol Pin name Value Unit Remarks

Min Max

Reset input time tRSTL RST 16 tCP — ns Under normal operation

Oscillation time of

oscillator* + 16 tCP — ms In stop mode

Hardware standby input time tHSTL HST 16 tCP — ns Under normal operation

RST

HST 0.2 VCC

tRSTL, tHSTL

0.2 VCC

• Under normal operation

tRSTL

0.2 VCC 0.2 VCC

16 tCP

RST

90% of

amplitude

Instruction execution

Oscillation stabilize standby time

Oscillator

oscillation time

Internal operation

clock

Internal reset

• In stop mode

MB90550A/550B Series

40 DS07-13706-6E

(4) Specifi ca ti o n for Power-on Reset (VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Notes: • VCC must be kept lower than 0.2 V before power-on.

• The above values ar e used for creating a power-on rese t.

• Some registers in the device are initialized only upon a po we r-on reset. To initialize these register , turn on

the pow er supply using the above values.

Paramet er Symbo l Pin name Value Unit Remarks

Min Max

Power supply rising time tR

VCC

0.05 30 ms

Power-supply start voltage VOFF —0.2V

Power-supply end voltage VON 2.7 — V

Power supply cut-off time tOFF 4 — ms Due to repeated operations

VCC

5.0 V VCC

3.0 V

0 V VSS

0.2 V

2.7 V

tOFF

0.2 V

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to

raise the voltage smoothly to suppress fluctua ti ons as shown below.

In this case, change the suppl y voltage with the PLL clock not used. If the voltage drop is

1 V or fewer per second, however, you can use the PLL clock.

It is recommended to keep the rising speed of

the supply voltage at 50 mV/ms or slower.

RAM data being held

MB90550A/550B Series

DS07-13706-6E 41

(5) Bus Read Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter S ymbol Pin name Value Unit Remarks

Min Max

ALE pulse width tLHLL ALE tCP/2 − 20 — ns

Effective address → ALE ↓ time tAVLL ALE, A23 to A16,

AD15 to AD00 tCP/2 − 20 — ns

ALE ↓ → address effective time tLLAX ALE, AD15 to AD00 tCP/2 − 15 — ns

Effective address → RD ↓ time tAVRL A23 to A16,

AD15 to AD00, RD tCP − 15 — ns

Effective address → valid data

input tAVDV A23 to A16,

AD15 to AD00 —5 t

CP/2 − 60 ns

RD pulse width tRLRH RD 3 tCP/2 − 20 — ns

RD ↓ → valid data input tRLDV RD, AD15 to AD00 — 3 tCP/2 − 60 ns

RD ↑ → data hold time tRHDX RD, AD15 to AD00 0 — ns

RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 — ns

RD ↑ → address effective time tRHAX ALE, A23 to A16 tCP/2 − 10 — ns

Effective address → CLK ↑ time tAVCH A23 to A16,

AD15 to AD00, CLK tCP/2 − 20 — ns

RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 — ns

ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 — ns

CLK

ALE

A23 to A16

AD15 to AD00

tAVCH

tLHLL

tAVLL tRLRH

tRHAX

tRHDX

tRLDVtAVRL

tAVDV

tRHLH

tRLCH

2.4 V

2.4 V 2.4 V 2.4 V

2.4 V

0.8 V

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

tLLAX

tLLRL

• Bus read timing

• Multiplex mode

Address Read data

MB90550A/550B Series

42 DS07-13706-6E

(6) Bus Write Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin name Value Unit Remarks

Min Max

Effective address → WR ↓ time tAVWL A23 to A16, AD15 to

AD00, WRH, WRLtCP – 15 — ns

WR pulse width tWLWH WRH, WRL3 tCP/2 – 20 — ns

valid data output → WR ↑ time tDVWH AD15 to AD00,

WRH, WRL3 tCP/2 – 20 — ns

WR ↑ → data hold time tWHDX AD15 to AD00,

WRH, WRL20 — ns Multiplex

mode

WR ↑ → address effective time tWHAX A23 to A16,

WRH, WRLtCP/2 – 10 — ns

WR ↑ → ALE ↑ time tWHLH WRH, WRL, ALE tCP/2 – 15 — ns

WR ↓ → CLK ↑ time tWLCH WRH, WRL, CLK tCP/2 – 20 — ns

tWLCH

tWHLH

tWLWH

tAVWL

tDVWH tWHDX

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

CLK

ALE

A23 to A16

AD15 to AD00

(WRL, WRH)

• Multiplex mode

Address Write data

• Bus write timing

MB90550A/550B Series

DS07-13706-6E 43

(7) Ready Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Note : Use the auto matic r eady function whe n the set up tim e for the rising edge of the RDY signal is not sufficient.

Parameter Symbol Pin name Value Unit Remarks

Min Max

RDY setup time tRYHS RDY

CLK 45 — ns

RDY hold time tRYHH 0—ns

tRYHS tRYHH

0.8 V

2.4 V

0.8 VCC

0.2 VCC

0.8 VCC

CLK

ALE

(WRL, WRH)

RDY

wait not

inserted

RDY

wait inserted

(1 cycle)

• Ready input timing

MB90550A/550B Series

44 DS07-13706-6E

(8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.

(9) UART, Extended I/O Seria l 0, 1 Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Notes: • These are AC ratings in the CLK synchronous mode.

•C

L is the load capacitance value connected to pins while test ing.

Parameter Symbol Pin name Value Unit Remarks

Min Max

Pins in floating status → HAK ↓ time tXHAL HAK 30 tCP ns

HAK ↑ → pin valid time tHAHV tCP 2 tCP ns

Parameter Symbol Pin name Condition Value Unit Remarks

Min Max

Serial clock cycle time tSCYC SCK0 to SCK2

Internal shift clock

mode

CL = 80 pF

+ 1 TTL for an out-

put pin

8 tCP —ns

SCK ↓ → SOT delay time tSLOV SCK0 to SCK2,

SOT0 to SOT2 –80 80 ns

Valid SIN → SCK ↑ tIVSH SCK0 to SCK2,

SIN0 to SIN2 100 — ns

SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2,

SIN0 to SIN2 tCP —ns

Serial clock “H” pulse width tSHSL SCK0 to SCK2

External shift cloc k

mode

CL = 80 pF

+ 1 TTL for an

output pin

4 tCP —ns

Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCP —ns

SCK ↓ → SOT delay time tSLOV SCK0 to SCK2,

SOT0 to SOT2 — 150 ns

Valid SIN → SCK ↑ tIVSH SCK0 to SCK2,

SIN0 to SIN2 60 — ns

SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2,

SIN0 to SIN2 60 — ns

HAK

tXHAL tHAHV

Each Pins High-Z

• Hold timing

MB90550A/550B Series

DS07-13706-6E 45

(10) Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin name Value Unit Remarks

Min Max

Input pulse width tTIWH

tTIWL

TIN0, TIN1

IN0 to IN3 4 tCP —ns

SCK

SOT

SIN

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH tSHIX

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

tSLSH tSHSL

tSLOV

tIVSH tSHIX

0.2 VCC 0.2 VCC

0.8 VCC 0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• Internal shift clock mode

• External shift clock mode

• Timer input timing

IN0 to IN3

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTIWH tTIWL

TIN0, TIN1

MB90550A/550B Series

46 DS07-13706-6E

(11) Timer Output Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

(12) Trigger Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin name Value Unit Remarks

Min Max

CLK ↑ → TOUT transition time tTO TOT0,TOT1,OUT0,

OUT1,PPG0 to PPG5 30 — ns

Parameter Symbol Pin name Value Unit Remarks

Min Max

Input pulse width tTRGH

tTRGL IRQ0 to IRQ7 5 tCP —ns

Under normal operation

1—µsIn stop mode

CLK 2.4 V

tTO

2.4 V

0.8 V

TOT0,TOT1

OUT0,OUT1

PPG0 to PPG5

• Timer output timing

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tTRGH tTRGL

IRQ0 to IRQ7

• Trigger input timing

MB90550A/550B Series

DS07-13706-6E 47

(13) I2C Interface (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Notes: • “m” and “n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in

the clock control register “ICCR”. For details, refer to the register description in the hardware manual.

•t

DOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.

• The SDA and SCL output values indicate that that rise time is 0 ns.

Parameter Symbol Pin name Value Unit Remarks

Min Max

Internal clock cycle time tCP — 62.5 666 ns All products

Start condition output tSTAO

SDA0 to SDA2

SCL0 toSCL2

tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns Only as master

Stop condition outp ut tSTOO tCP (m × n/2 + 4)

– 20 tCP (m × n/2 + 4)

+ 20 ns

Start condition det ection tSTAI 3 tCP + 40 — ns Only as slave

Stop condition dete ctio n tSTOI 3 t CP + 40 — ns

SCL output “L” width tLOWO SCL0 to SCL2 tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns Only as master

SCL output “H” width tHIGHO tCP (m × n/2 + 4)

– 20 tCP (m × n/2 + 4)

+ 20 ns

SDA output delay time tDOO SDA0 to SDA2

SCL0 to SCL2

2 tCP – 20 2 tCP + 20 ns

Setup after SDA output

interr up t period tDOSUO 4 tCP – 20 — ns

SCL input “L” width tLOWI SCL0 to SCL2 3 tCP + 40 — ns

SCL input “H” width tHIGHI tCP + 40 — ns

SDA input setup time tSUI SDA0 to SDA2

SCL0 to SCL2 40 — ns

SDA input hold time tHOI 0—ns

MB90550A/550B Series

48 DS07-13706-6E

tLOWO

tSTAO tDOOtDOO

189

7689

tSUI

tHIGHI tLOWI

tHOI tDOO tDOO tDOSUO tSTOI

tSUI tHOI tDOSUO

tHIGHO

0.2 VCC

0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC

0.2 VCC

0.8 VCC

0.8 VCC 0.8 VCC 0.8 VCC

0.8 VCC 0.8 VCC

ACK

0.8 VCC 0.8 VCC

SCL

SDA

SCL

SDA

•I

2C interface [data transmitter (master/slave)]

•I

2C interface [data receiver (master/slave)]

MB90550A/550B Series

DS07-13706-6E 49

5. A/D Converter

(1)Electrical Characteristics

(4.5 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

*1:When FCP = 8 MHz, tCMP = 176 × tCP. When FCP = 16 MHz, tCMP = 352 × tCP.

*2: Equivalent to the time for conversion per channel if “t SMP = 64 × tCP” or “tCMP = 352 × tCP” is selected when FCP =

16 MHz.

*3: Specifies the power-supp ly c ur re n t (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the

CPU has been stopped.

Notes: • The error becomes larger relatively as |AVRH-AVRL| becomes smaller.

• Use the output impedance rS of the external circuit for analog input under the following condition:

External circuit output impedance rS = 10 kΩ Max.

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be

insufficient.

• I f you insert a DC-blocking capacitor between the external circuit and t he in put p in, select a ca pacit an ce

that is about several thousands times the sampling capacitance CSH in the chip to suppress the effect of

capacity potential division with CSH.

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Resolution — — — 10 — bit

Total error — — — — ±5.0 LSB

Non-linearity error — — — — ±2.5 LSB

Differential linearity error — — — — ±1.9 LSB

Zero transition voltage VOT AN0 to AN7 AVRL−

3.5LSB AVRL+

0.5LSB AVRL+

4.5LSB V1LSB=

(AVRH−AVRL)

/1024

Full-scale transition

voltage VFST AN0 to AN7 AVRH−

6.5LSB AVRH−

1.5LSB AVRH+

1.5LSB V

Sampling period tSMP — 64 — 4096 tCP

Compare time tCMP —22——

µs*1

A/D Conversion time tCNV —26.3— —

µs*2

Analog port inpu t curr ent IAIN AN0 to AN7 — — 10 µA

Analog input voltage VAIN AN0 to AN7 AVRL — AVRH V

Reference voltage — AVRH AVRL + 4.5 — AVCC V

— AVRL 0 — AVRH − 4.5 V

Power supply current IAAVCC —3.57.0

IAH —— 5

µA*3

Reference voltage

supply current IRAVRH — 300 500 µA

IRH —— 5

µA*3

Offset bet ween channels — AN0 to AN7 — — 4 LSB

MB90550A/550B Series

50 DS07-13706-6E

RSH CSH

Microcontroller internal circuit

Input pin AN0

Input pin AN7

External circuit Analog channel selector

Comparator

rS = 10 kΩ or less

RSH = About 3 kΩ

CSH = About 25 pF

Note: Device pa rameter values ar e prov ided as ref erence valu es for de sign p urposes; t hey

are not guaranteed.

S/H circuit

• Analog input circuit model

MB90550A/550B Series

DS07-13706-6E 51

(2) Definitions of Terms

• Resolution: Analog transition identifiable by the A/D converter.

Analog voltage can be divided into 1024 (210) components at 10-bit resolution.

• Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error,

non-linearity error an d an error caused by noise.

• Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00

0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device

from actual conversion characteristics

• Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB

• 10-bit A/D converter conversion characteristics

11 1111 1111

11 1111 1110

11 1111 1101

11 1111 1100

00 0000 0011

00 0000 0010

00 0000 0001

00 0000 0000

•

1LSB × N + VOT

VOT VNT VFSTV(N + 1)T

Analog input

1LSB =VFST − VOT

1022

Linearity error =VNT − (1LSB × N + VOT)

1LSB [ LSB ]

Differential linearity error =V (N + 1) T − VNT

1LSB − 1 [ LSB ]

Linearity error

Digital output

MB90550A/550B Series

52 DS07-13706-6E

6. Flash Memory Program/Erase Characteristics

Parameter Condition Value Unit Remarks

Min Typ Max

Sector erase tim e

TA = + 25 °C

VCC = 5.0 V

—1.530s

Excludes 00H programming

prior erasure

Chip erase time — 10.5 — s Excludes 00H programming

prior erasure

Word (16-bit width)

programming time —16500µsExcludes system-level

overhead

Program/Erase cycle — 100,000 — — cycle Guaranteed 100,000 cycles

10,000 — — cycle Guaranteed 10,000 cycles

Data hold time — 100,000 — — h

MB90550A/550B Series

DS07-13706-6E 53

■EXAMPLE CHARACTERISTICS

1. “L” level output voltage

700

600

500

400

300

200

100

00246810

IOL (mA)

VOL (mV)

VCC = 3.5 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

TA = + 25 °C

700

600

500

400

300

200

100

00 5 10 15

IOL (mA)

VOL (mV)

20 25 30

VOL − IOL

Other than P20 to P27

VOL − IOL

P20 to P27

MB90550A/550B Series

54 DS07-13706-6E

2. “H” level output voltage

3. “H” level input voltage / “L” level input voltage (CMOS input)

VCC = 3.5 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

TA = + 25 °C

700

600

500

400

300

200

100

00−2−4−6−8−10

IOH (mA)

VCC − VOH (mV)

(VCC − VOH) − IOH

Other than P50 to P55

4.5

3.5

2.5

1.5

03.5 4 4.5 5 5.5

VCC (V)

VIH/VIL (V)

TA = + 25 °C

VIH / VIL − VCC

MB90550A/550B Series

DS07-13706-6E 55

4. “H” level input voltage / “L” level input voltage (CMOS hysteresis input)

4.5

3.5

2.5

1.5

03.5 4 4.5 5 5.5

VIHL

VIHS

VCC (V)

VIHS/VILS (V)

TA = + 25 °C

VIHS / VILS − VCC

MB90550A/550B Series

56 DS07-13706-6E

5. Power supply current

(fCP = internal operating clock frequency)

(Continued)

03.5 4 4.5 5 5.5

fCP = 8 MHz

VCC (V)

ICC (mA)

fCP = 10.6 MHz

fCP = 16 MHz

TA = + 25 °C

fCP = 4 MHz

03.5 4 4.5 5 5.5

fCP = 8 MHz

VCC (V)

ICCS (mA)

fCP = 10.6 MHz

fCP = 16 MHz

TA = + 25 °C

fCP = 4 MHz

ICC − VCC

ICCS − VCC

• MB90552A/B

• Measurement conditions: External clock mode, ROM read loop operation,

without resource operation, Typ sample,

internal operating frequency = 4 MHz (external rectangular wave

clock at 8MHz), TA = + 25 °C

MB90550A/550B Series

DS07-13706-6E 57

(Continued)

104.5 5 5.5

fCP = 4 MHz

fCP = 10 MHz

VCC (V)

ICC (mA)

fCP = 16 MHz

TA = + 25 °C

04.5 5 5.5

TA = + 25 °C

fCP = 16 MHz

fCP = 4MHz

fCP = 10 MHz

VCC (V)

ICCS (mA)

ICC − VCC

ICCS − VCC

• MB90F553A

• Measurement conditions: External clock mode, ROM read loop operation,

without resource operation, Typ sample,

internal operating frequency = 4MHz (external rectangular wave

clock at 8MHz), TA = +25 °C

MB90550A/550B Series

58 DS07-13706-6E

6. Pull-up resistance

TA = + 85 °C

TA = + 25 °C

TA = −40 °C

10 4 4.5 5 5.5

VCC (V)

Pull-up resistance − VCC

Pull-up resistance (kΩ)

MB90550A/550B Series

DS07-13706-6E 59

■ORDERING IN FORMATION

Part number Package Remarks

MB90552APF

MB90552BPF

MB90553APF

MB90553BPF

MB90T552APF

MB90T553APF

MB90F553APF

MB90P553APF

100-pin plastic QFP

(FPT-100P-M06)

MB90552APMC

MB90552BPMC

MB90553APMC

MB90553BPMC

MB90T552APMC

MB90T553APMC

MB90F553APMC

MB90P553APMC

100-pin plastic LQFP

(FPT-100P-M20)

MB90550A/550B Series

60 DS07-13706-6E

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

100-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 14.0 mm × 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm Max

Weight 0.65 g

Code

(Reference) P-LFQFP100-14×14-0.50

100-pin plastic LQFP

(FPT-100P-M20)

2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

125

76 50

100

0.50(.020) 0.20±0.05

(.008±.002) M

0.08(.003)0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX .059

–.004

+.008

–0.10

+0.20

1.50

(Mounting height)

0°~8°

0.50±0.20

(.020±.008)

(.024±.006)

0.60±0.15

0.25(.010)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB90550A/550B Series

DS07-13706-6E 61

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

100-pin plastic QFP Lead pitch 0.65 mm

Package width ×

package length 14.00 × 20.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

3.35 mm MAX

Code

(Reference) P-QFP100-14×20-0.65

100-pin plastic QFP

(FPT-100P-M06)

(

FPT-100P-M06

)

2002 FUJITSU LIMITED F100008S-c-5-5

130

5180

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20

(.551±.008)

17.90±0.40

(.705±.016)

INDEX

0.65(.026) 0.32±0.05

(.013±.002) M

0.13(.005)

"A"

0.17±0.06

(.007±.002)

0.10(.004)

Details of "A" part

(.035±.006)

0.88±0.15

(.031±.008)

0.80±0.20

0.25(.010)

3.00 +0.35

–0.20

+.014

–.008

.118

(Mounting height)

0.25±0.20

(.010±.008)

(Stand off)

0~8˚

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

MB90550A/550B Series

62 DS07-13706-6E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

Page Section Change Results

⎯⎯

The package code is changed.

(FPT-100P-M05 →FPT-100P-M20)

■ ORDERING INFORMATION Order informations are changed.

(MB90552APFV →MB90552APMC

MB90552BPFV →MB90552BPMC

MB90553APFV →MB90553APMC

MB90553BPFV →MB90553BPMC

MB90T552APFV →MB90T552APMC

MB90T553APFV →MB90T553APMC

MB90F553APFV →MB90F553APMC

MB90P553APFV →MB90P553APMC)

60 ■ PACKAGE DIMENSIONS The package fi gure is changed.

(FPT-100P-M05 →FPT-100P-M20)

MB90550A/550B Series

DS07-13706-6E 63

MEMO

MB90550A/550B Series

FUJITSU MICROELECTRONICS LIMITED

7-1, Nishishinjuku 2-chome, Shinjuku Dai-Ichi Seimei Bldg.,

Shinjuku-ku, Tokyo 163-0722, JAPAN

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRO NICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, F. R. GERMANY

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTR ONICS K OREA LTD .

1002 Daechi-Dong, 206 KOSMO TOWER,

Kangnam-Gu, Seoul 135-280, KOREA

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTR ONICS ASIA PTE LTD .

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741, SINGAPORE

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

FUJITSU MICROELECTR ONICS SHANGHAI CO ., LTD.

No.222 Yan An Road(E), Rm.3102, Bund Center,

Shanghai 200002, P. R. CHINA

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTR ONICS PACIFIC ASIA LTD .

11 Canton Road, 10/F., World Commerce Centre,

Tsimshatsui, Kowloon, HONG KONG

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The informatio n, such as desc riptions of function and application circuit examples, in this document a re present ed solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use b ased on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of functio n and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

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other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and househo ld use, but are not designed, developed and manufactured

as contemplated ( 1) for use acco mpanying fatal risks or dangers that, unless extremely high saf ety is secured, could h ave a ser ious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redund ancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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