MT88L85AE - Mitel Semiconductor - Datasheet.Directory

4-71



Features

• External power down pin

• Lo w vol tage operati on (2. 7V - 3.6V)

• Central office quality DTMF transmitter/

receiver

• Lo w pow er co nsump tion

• H igh sp eed adapti ve mic ro in terface

• Adjustable guard time

• A utoma tic ton e bu rst mode

• C all prog ress t one de tectio n to -3 0dBm

• DTM F transmitter/receiver pow er down via

Applications

• Cre dit card systems

• Paging systems

• Rep eater systems/mobile radi o

• I nterco nnec t dial ers

• P erso nal comp uters

Description

The MT88L85 is a monolithic DTMF transceiver with

call progress filter. It is fabricated in CMOS

technology offering low power consumption and high

reliability.

The receiver section is based upon the industry

standard MT8870 DTMF receiver while the

transmitter utilizes a switched capacitor D/A

converter for low distortion, high accuracy DTMF

signalling. Internal counters provide a burst mode

such that tone bursts c an be transm itted with precise

timing. A call progress filter can be selected allowing

a microprocessor to analyze ca ll progress tones.

The MT88L85 utilizes an adaptive micro interface,

which allows the device to be connected to a number

of popular microcontrollers with minimal external

logic. The MT88L85 provides enhanced power down

features. The transmitter and receiver may

independently be powered down via register

control. A full chip power down pin provides simple

power and control capability.

Figure 1 - Functiona l Block Diagram

TONE

IN+

IN-

OSC1

OSC2

VDD VRef VSS ESt St/GT

IRQ/CP

DS/RD

R/W/WR

RS0

∑D/A

Converters Row and

Column

Counters

Transmit Data

Data

Bus

Buffer

Tone Burst

Gating Cct.

Oscillator

Circuit

Bias

Circuit

Control

Logic

Digital

Algorithm

and Cod e

Converter

Control

Logic

Steering

Logic

Status

Control

Receive Data

Interrupt

Logic

I/O

Control

Low Group

Filter

Hig h Group

Filter

Dial

Tone

Filter

PWDN

ISSUE 1 May 1995

MT88L85

3V Integrated DTMFTransceiver

with Power Down & Adaptive

Micro Interface

Ordering Information

MT88L85AE 24 Pin Plast ic DIP

MT8 8L85A N 24 P in SSO P

MT88L85AP 28 Pin PLCC

-40°C to +85°C

Advance Information

MT88L85 Advance Information

4-72

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

24 28

1 1 IN+ Non-inverting op-am p input .

22 IN- Inverting op-amp input .

34 GS Gai n Se lect. Gives ac cess to output of front end differen tial ampl ifier for co nnection of

feedback resistor.

46 V

Ref Reference Voltage output (VDD/2).

57 V

SS Ground (0V).

68 OSC1Oscillator input. This pin can also be driven directl y by an e xternal clock.

79 OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes

the internal oscillato r circuit. Leave open circuit when OSC1 is driven externally.

10 12 T ONE Output from internal DTMF transmitter.

11 13 R/W(WR)(Motorola) Read/Write or (Int el) Write microprocessor input . CM OS comp atible.

12 14 CS Chip Se lect inpu t. This signal must be quali fie d externall y by eit her address strobe (AS),

valid memory address (VM A) or address latch enable (ALE ) signal, see Figure 12.

13 15 RS0 Register Se lec t input. Refer to Tab le 3 f or bit interpret ati on. CMOS compa tib le.

14 17 DS (RD) (Motorola) Data Stro be or (Intel) Read microprocessor input. Act ivity on t his input is only

required when the device is being accessed. CMOS compat ible.

15 18 IRQ/CP Interrup t Request/Call P rogress (open drain) outpu t. In interrupt mode, this outp ut goes

low when a valid DTMF tone b urst has been tran smitted or received. In call progress mode,

this pin will output a rectangular signal representative of the input signal applied at the input

op-amp. The input signal must be within t he bandwidth lim it s of the call progress filte r, see

Figure 8.

16 19 PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ

and TO NE out put are high impedance. Data bus is held in tri-stat e. T his pin is inte rnally

pulled down.

14-

17 18-

21 D0-D3 Microprocessor data bus. High impedan ce when CS = 1 or DS =0 (Motorola) or RD = 1

(Intel). TTL compatible.

18 22 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid

tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return

to a logic low.

19 23 St/GT Steerin g Inpu t/Guard Time output (bidirect ional ). A volt age greater than VTSt det ected at

St causes the device to registe r the detected to ne pair and update the out put latch. A

voltage less than VTSt frees the device to a ccep t a new tone pai r. The GT output act s to

reset the external steering time-constant; its state is a function of ESt and the voltage on St.

20 24 VDD Positive power supply (3V t yp.).

12 13

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

R/W/WR

VDD

St/GT

ESt

PWDN

IRQ/CP

DS/RD

RS0

24 PIN DIP/SSOP

•

VRef

VSS

OSC1

OSC2

IN-

IN+

VDD

St/GT

ESt

PWDN

TONE

R/W/WR

RS0

DS/RD

IRQ/CP

28 PIN PLCC

Advance Information MT88L85

4-73

Functional Descri ption

The MT 88L85 Integrated DTMF Transceiver consists

of a high performance DTMF receiver with an

int ernal gain setting amplifier and a DTMF generator,

which em ploys a burst count er to synthesize precise

tone bursts and pauses. A call progress mode can

be selected so that frequencies within the specified

passband can be detected. The adaptive micro

interface allows microcontrollers, such as the

68HC11, 80C51 and TMS370C50, to access the

MT88L85 internal registers.

Power Dow n

The MT88L85 provides enhanced power down

functionality to facilitate minimization of supply

current consum ption. DTMF tr ansmitter and receiver

circuit blocks may be independently powered down

via register control. When asserted, the RxEN

control bit powers down all analog and digital

circuitry associated solely with the DTMF and Call

Progress receiver. The TOUT control bit is used to

disable the transmitter and put all circuitry

associated only with the DTMF transmitter in power

down mode. With the TOUT control bit asserted, the

TONE output pin is held in a high impedance

(floating) state. When both power down control bits

are asserted, circuits utilized by both the DTMF

transmitter and receiver are also powered down.

This includes the crystal oscillators, and the VRef

generator. In addition, the IRQ , TONE output and

DATA pins are held in a high impedance state.

Finally, t he whole dev ice is put in a power down state

when the PWDN pin is asserted.

Input Configuration

The input arrangement of the MT88L85 provides a

differential-input operational amplifier as well as a

bias source (VRef), wh ic h i s u s ed to b ia s th e i npu ts at

VDD/2. Provision is made for connection of a

feedback resistor to the op-amp output (GS) for gain

adjustment. In a single-ended configuration, the

input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a

differential input configuration.

Rec eiv er S ec tion

Separation of the low and high group tones is

achieved by applying the DTMF signal to the inputs

of two sixth-order switched capacitor bandpass

filters, the bandwidths of which correspond to the low

and high group frequencies (see Table 1). The filters

also incorporate notches at 350 Hz and 440 Hz for

exceptional dial tone rejection. Each filter output is

followed by a single order switched capacitor filter

section, which smooths the signals prior to limiting.

Limiting is performed by high-gain comparators

which are provided with hysteresis to prevent

detec tion of unwanted low-level signals. The outputs

of the comparators provide full rail logic swings at

the frequencies of the incoming DTMF signals.

Figure 3 - Single-Ende d Input Configuration

Figure 4 - Differential Input Configura tion

CRIN

IN+

IN-

VRef

VOLTAGE GAIN

(AV) = RF / RIN

MT88L85

R4 R5

IN+

IN-

VRef

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF

R1 = R4 = R5 = 100 kΩ

R2 = 60kΩ, R3 = 37.5 kΩ

R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

(AV diff) - R5/R1 INPUT IMPEDANCE

(ZINdiff) = 2 R12 + (1/ωC)2

MT88L85

8,9

17 3,5,

10,11

16,

20,

NC No Connection.

Pin Description

Pi n # Name Description

24 28

MT88L85 Advance Information

4-74

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Decode Ta ble

Following the filter section is a decoder employing

digital counting techniques to determine the

frequencies of the incoming tones and to verify that

they correspond to standard DTMF frequencies. A

complex averaging algorithm protects against tone

simulation by extraneous signals such as voice while

providing tolerance to small frequency deviations

and variations. This averaging algorithm has been

developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of

interfering frequencies (third tones) and noise. When

the detector recognizes the presence of two valid

tones (this is referred to as the “signal condition” in

some industry specifications) the “Early Steering”

(ESt) output will go to an active state. Any

subsequent loss of signal condition will cause ESt to

assume an inactive state.

Steering C ircuit

Before registration of a decoded tone pair, the

receiver checks for a valid signal duration (referred

to as character recognition condition). This check is

perform ed by an external RC time constant driven by

ESt. A logic high on ESt causes vc (see Figure 5) to

rise as the capacitor discharges. Provided that the

signal condition is maintained (ESt remains high) for

the validation period (tGTP), vc reaches the threshold

FLOW FHIGH DIGIT D3D2D1D0

6971209 1 0001

6971336 2 0010

6971477 3 0011

7701209 4 0100

7701336 5 0101

7701477 6 0110

8521209 7 0111

8521336 8 1000

8521477 9 1001

9411336 0 1010

9411209 * 1011

9411477 # 1100

6971633 A 1101

7701633 B 1110

8521633 C 1111

9411633 D 0000

(VTSt) of the steering logic to register the tone pair,

latching its corresponding 4-bit code (see Table 1)

into the Receive Data Register. At this point the GT

output is activated and drives vc to VDD. GT

continues to drive high as long as ESt remains high.

Finally, after a short delay to allow the output latch to

settle, the delayed steering output flag goes high,

signalling that a received tone pair has been

registered. The status of the delayed steering flag

can be monitored by checking the appropriate bit in

the status register. If Interrupt mode has been

selected, the IRQ/CP pin will pull low when the

delayed steering flag is act ive.

The contents of the output latch are updated on an

active delayed steering transition. This data is

presented to the four bit bidirectional data bus when

the Receive Data Register is read. The steering

circuit works in reverse to validate the interdigit

pause between signals. Thus, as well as rejecting

signals t oo short to be considered valid, the receiver

will tolerate signal interruptions (drop out) too short

to be considered a valid pause. This facility, together

with the capability of selecting the steering time

constants externally, allows the designer to tailor

performance to meet a wide variety of system

requirements.

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is

adequate for most applications. Component values

are chosen according to the following inequalities

(see Figure 7):

tREC ≥ tDPmax + tGTPmax - tDAmin

tREC ≤ tDPmin + tGTPmin - tDAmax

tID ≥ tDAmax + tGTAmax - tDPmin

tDO ≤ tDAmin + tGTAmin - tDPmax

The value of tDP is a device parameter (see AC

Electrical Characteristics) and tREC is the minimum

VDD

St/GT

ESt

tGTA = (R1C1) In (VDD / VTSt)

tGTP = (R1C1) In [VDD / (VDD-VTSt)]

MT88L85

Advance Information MT88L85

4-75

signal duration to be recognized by the receiver. A

value for C1 of 0.1 µF is recommended for most

Fig ur e 6 - Gu ar d Tim e A dju stm en t

VDD

St/GT

ESt

VDD

St/GT

ESt

R1 R2

tGTA = (R1C1) In (VDD/VTSt)

tGTP = (RPC1) In [VDD / (VDD-VTSt)]

RP = (R1R2) / (R1 + R2)

tGTA = (RpC1) In (VDD/VTSt)

tGTP = (R1C1) In [VDD / (VDD-VTSt)]

RP = (R1R2) / (R1 + R2)

a) decrea sing tGTP; (tGTP < tGTA)

b) decreasing tGTA; (tGTP > tGTA)

applications, leaving R1 to be selected by the

designer. Different steering arrangements may be

used to select independent tone present (tGTP) and

tone absent (tGTA) guard times. This may be

necessary to m eet system spec ifications which place

both accept and reject limits on tone duration and

interdigital pause. Guard time adjustm ent also allows

the designer to tailor system parameters such as talk

off and noise immunit y.

Increasing tREC improves talk-off performance since

it reduces the probability that tones simulated by

speech will maintain a valid signal condition long

enough to be registered. Alternatively, a relatively

short tREC with a long tDO would be appropriate for

extremely noisy environments where fast acquisition

time and immunity to tone drop-outs are required.

Design information for guard time adjustment is

shown in Figure 6. The receiver timing is shown in

Figure 7 with a description of the events in Figure 9.

Call Progre ss Filter

A call progress mode, using the MT88L85, can be

selected allowing the detection of various tones,

which identify the progress of a telephone call on th e

network. The call progress tone input and DTMF

input are common, however, call progress tones can

only be detected when CP mode has been selected.

Fi gure 7 - R ece iver Tim ing Diag ram

Vin

ESt

St/GT

RX0-RX3

Read

Status

IRQ/CP

EVENTS ABCDEF

REC tREC tID tDO

TONE #n TONE

#n + 1 TONE

#n + 1

tDP tDA

tGTP tGTA

tPStRX

tPStb3

DECODED TONE # (n-1) # n # (n + 1)

VTSt

MT88L85 Advance Information

4-76

Fi gur e 9 - De sc ript ion of Tim in g Ev en ts

EXPLANATION OF EVENTS

A) TONE BURST S DETECTED, TONE DURATION INVALID, RX DATA REGIS TER NOT UPDATED.

B) TONE #n DET ECTED, TONE DURATION VALID, TONE DECODED AND L ATCHED IN RX DATA REGISTER.

C) END OF TONE #n DE TECT ED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTE R

RETAINED UNTIL NEXT VALID TONE PAIR.

D) TONE #n+1 DET ECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABS ENT DURATION INVALID, DATA REMAINS UNCHANGED.

F) END OF TONE #n+1 DE TECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTE R

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS

Vin DTMF C OMPO S ITE INPU T SIGN A L.

ESt EARLY STEERING OUTPU T. INDICATES DETECTION OF VALID TONE FREQUENCIES.

St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES E XTERNAL RC TIMING CIRCUIT.

RX0-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER

b3 DEL AYED STEE RING . I NDICATES TH AT VALID FREQ UEN CIES HAVE BEEN PRESEN T/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A

VALID D TMF SIGNAL.

b2 INDICATES THAT VALID DATA IS IN T HE RECEIVE DATA REGISTER. THE BIT IS CLEARED A FTER THE STATUS

REGI STER IS READ .

IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEAR ED AFTER T HE STAT US REG I STER IS R EAD.

tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.

tID MINIM UM TIM E BET WEEN VALID S E QUEN TI AL D TMF SIG NAL S.

tDO MAXIMUM ALLOWAB LE DROPOUT DURING VALID DTMF SIGNAL.

tDP TIME TO DE TECT VALID FREQU ENCIES PR ESENT.

tDA TIME TO DE TECT VALID FREQU ENCIES ABSEN T.

tGTP GUARD T IM E, TONE PRESENT.

tGTA GUARD T IM E, TO NE ABSEN T.

DTMF signals cannot be detected if CP mode has

been selected (see Table 7). Figure 8 indicates the

useful detect bandwidth of the call progress filter.

Frequenc ies presented to the input, which are within

the ‘accept’ bandwidth limits of the filter, are hard-

limited by a high gain comparator with the IRQ/CP

pin serving as the output. The squarewave output

obtained from the schmitt trigger can be analyzed by

a microprocessor or counter arrangement to

determine the nature of the call progress tone being

detected. Frequencies which are in the ‘reject’ area

will not be detected and consequently the IRQ/CP

pin will remain low.

DTMF Generator

The DTMF transmitter employed in the MT88L85 is

capable of generating all sixteen standard DTMF

tone pairs with low distortion and high accuracy. All

frequencies are derived from an external 3.579545

MHz crystal. The sinusoidal waveforms for the

individual tones are digitally synthesized using row

and column programmable dividers and switched

capacitor D/ A converters. The row and column tones

are mixed and filtered providing a DTMF signal with

low total harmonic distortion and high accuracy. To

specify a DTMF signal, data conforming to the

encoding format shown in Table 1 must be written to

the transmit Data Register. Note that this is the

same as the receiver output code. The individual

tones which are generated (fLOW and fHIGH) are

ref erred to as Low Group and High Group tones. As

seen from the table, the low group frequencies are

697, 770, 852 and 941 Hz. The high group

frequencies are 1209, 1336, 1477 and 1633 Hz.

Typically, the high group to low group amplitude ratio

(twist) is 2 dB to com-pensate for high group

attenuation on long loops.

Figure 8 - Call Progress Respons e

AAAA

AAA

AAAA

AAA

AAAA

LEVEL

(dBm)

FREQUENCY (Hz)

-25

0250500750

= Reject

= Ma y Ac cept

= Accept

Advance Information MT88L85

4-77

Figure 10 - Spectrum Plot

Scaling Information

10 dB/Div

Start Frequency = 0 Hz

Stop Frequency = 3400 Hz

Marker Frequency = 697 Hz and

1209 Hz

The period of each tone consists of 32 equal time

segments. The period of a tone is controlled by

varying the length of these time segments. During

write operations to the Transmit Data Register the 4

bit data on the bus is latched and converted to 2 of 8

coding for use by the programmable divider circuitry.

This code is used to specify a time segment length,

which will ultimately determine the frequency of the

tone. When the divider reaches the appropriate

count, as determined by the input code, a re set pulse

is issued and the counter starts again. The number

of time segments is fixed at 32, however, by varying

the segment length as described above the

frequency can also be varied. The divider output

clocks another counter, which addresses the

sinewav e lookup ROM.

The lookup table contains codes which are used by

the switched capacitor D/A converter to obtain

discrete and highly accurate DC voltage levels. Two

identical circuits are employed to produce row and

column tones, which are then mixed using a low

noise summing amplifier. The oscillator described

needs no “start-up” time as in other DTMF

generators since the crystal oscillator is running

continuously thus providing a high degree of tone

burst accuracy. A bandwidth limiting filter is

incorporated and serves to attenuate distortion

products above 8 kHz. It can be seen from Figure 6

that the distortion products are very low in amplitude.

Burst Mode

In certain telephony applications it is required that

DTMF signals being generated are of a specific

duration determined either by the particular

application or by any one of the exchange transmitter

specifications currently existing. Standard DTMF

signal timing can be accomplished by m aking use of

the B ur st M o de. T h e tra n sm i tte r is ca p abl e of is sui n g

symmetric bursts/pauses of predetermined duration.

This burst/pause duration is 51 ms±1 ms which is a

standard interval for autodialer and central office

applications. After the burst/pause has been issued,

the appropriate bit is set in the Status Register

indica tin g th at the tra ns mi tter is re a dy fo r more d at a.

The timing described above is available when DTMF

mode has been selected. However, when CP mode

(Call Progress mode) is selected, the burst/pause

dur at ion is d oub l e d to 1 02 ms ±2 m s . No te th a t wh e n

CP mode and Burst mode have been selected,

DTMF tones may be transmitted only and

not

received. In applications where a non-standard

burst/pause time is desirable, a software timing loop

or external timer can be used to provide the timing

pulses when the burst mode is disabled by enabling

and disabling the transmitter.

Single Tone G enera tion

A single tone mode is available whereby individual

tones from the low group or high group can be

generated. This mode can be used for DTMF test

equipment applications, acknowledgment tone

generation and distortion measurements. Refer to

Control Register B description for details.

MT88L85 Advance Information

4-78

Table 2. Actual Frequencies Versus Standard

Requirements

Distortion C alculations

The MT88L85 is capable of producing precise tone

bursts with minimal error in frequency (see Table 2).

The internal summing amplifier is followed by a first-

order lowpass switched capacitor filter to minimize

harmonic components and intermodulation products.

The t otal harmonic distortion for a

single tone

can be

calculated using Equation 1, which is the ratio of the

total power of all the extraneous frequencies to the

power of the fundamental frequency expressed as a

percentage.

Equation 1. THD (%) For a Single Tone

The Fourier components of the tone output

correspond to V2f.... Vnf as measured on the output

waveform. The total harmonic distortion for a

dual

tone

can be calculated using Equation 2. VL and VH

correspond to the low group amplitude and high

group amplitude, respectively and V2IMD is the sum

of all the intermodulation components. The internal

switched-capacitor filter following the D/A converter

keeps distortion products down to a v ery low level as

shown in Figure 10.

Equa tion 2. T HD (%) For a D ual Tone

ACTIVE

INPUT OUTPUT FREQUENCY (Hz) %ERROR

SPECIFIED ACTUAL

L1 697 699.1 +0.30

L2 770 766.2 -0.49

L3 852 847.4 -0.54

L4 941 948.0 +0.74

H1 1209 1215.9 +0.57

H2 1336 1331.7 -0.32

H3 1477 1471.9 -0.35

H4 1633 1645.0 +0.73

THD (%) = 100 Vfundamental

V22f + V23f + V24f + .... V2nf

V2L + V2H

V22L + V23L + .... V2nL + V22H +

V23H + .. V2nH + V2IMD

THD (%) = 100

DTMF Clock Circuit

The internal clock circuit is completed with the

addition of a standard television colour burst crystal

having a resonant frequency of 3.579545 MHz. A

number of MT88L85 devices can be connected as

shown in Figure 11 such that only one crystal is

required. Alternatively, the OSC1 inputs on all

devices can be driven from a TTL buffer with the

OSC2 outputs left unconnected.

Figure 11 - Common Crystal Connection

Microproce ssor I nterface

The MT88L85 design incorporates an adaptive

interface, which allows it to be connected to various

kinds of microprocessors. Key functions of this

interface include the following:

• Co ntinuous activity on DS/RD is not necessary

to update the internal status registers.

• sen s es w het h er i npu t tim i ng i s t ha t of an I nte l o r

Motorola controller by monitoring the DS (RD),

R/W (WR) an d CS inputs.

• g ene rate s e quiva lent CS sign al fo r internal

opera tio n for all pr ocess ors.

• d ifferent iates bet ween m ultip lex ed and n on-

multiplexed microp rocessor buse s. Ad dress

and d ata ar e lat ched in a ccord ingly.

• co mpatible with Motorola and Intel p rocessors.

Figure 16 shows the timing diagram for Motorola

microprocessors with separate address and data

buses. Members of this microprocessor family

include 2 MHz versions of the MC6800, MC6802 and

MC6809. For the M C6809, the chip select (CS) inp u t

signal is formed by NANDing the (E+Q) clocks and

address decode output. For the MC6800 and

MC6802, CS is formed by NANDing VMA and

address decode output. On the falling edge of CS,

the internal logic senses the state of data strobe

MT88L85

OSC1 OSC2

MT88L85

OSC1 OSC2

MT88L85

OSC1 OSC2

3.579545 MHz

Advance Information MT88L85

4-79

(DS). When DS is low, Motorola proc essor operation

is selected.

Figure 17 shows the tim ing diagram for the Motorola

MC68HC11 (1 MHz) microcontroller. The chip select

(CS) input is formed by NANDing address strobe

(AS) and address decode output. Again, the

MT88L85 examines the state of DS on the falling

edge of CS to determine if the micro has a Motorola

bus (when DS is low). Additionally, the Texas

Instruments TMS370CX5X is qualified to have a

Motorola interface. Figure 12(a) summarizes

connection of these Motorola processors to the

MT88L85 DTMF transceiver.

Figures 18 and 19 are the timing diagrams for the

Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-

controllers w it h multiplexed address and data buses.

The MT88L85 latches in the state of RD on the

falling edge of CS. Wh en RD is high, Intel processor

operation is selected. By NANDing the address

latch enable (ALE) output with the high-byte address

(P2) decode output, CS can be generated. Figure

12(b) summarizes the connection of these Intel

processors t o the MT88L85 trans ceiver.

NOTE: The adaptive micro interface relies on high-

to-low transition on CS to recognize the

microcontroller int erface and this pin must not be tied

permanently low.

The adaptive micro interface provides access to five

internal registers. The read-only Receive Data

valid DTMF digit received. Data entered into the

write-only Transmit Data Register will determine

which tone pair is to be generated (see Table 1 for

coding details). Transceiver control is accomplished

with two control registers (see Tables 6 and 7), CRA

and CRB, which have the same address. A write

operation to CRB is executed by first setting the

most significant bit (b3) in CRA. The following write

operation to the same address will then be directed

to CRB, and subsequent write c ycles w ill b e d irected

back to CRA. The read-only status register indicates

the current transceiver state (see Table 8).

A software reset must be included at the beginning

of all programs to initialize the control registers upon

power-up or power reset (see Figure 14). Refer to

Tables 4-7 for bit descriptions of the two control

registers.

The multiplexed IRQ/CP pin can be programmed to

generate an interrupt upon validation of DTMF

signals or when the transmitter is ready for more

data (burst mode only). Alternatively, this pin can be

configured to provide a square-wave output of the

call progress signal. The IRQ/ CP pin is an open drain

output and requires an external pull-up resistor (see

Figure 13).

Figu re 12 a) & b) - M T88 L85 Inte rface Connec tions fo r Var ious In tel and Motoro la Mi cros

MC6800/6802 MT88L85 MT88L85

A0-A15

VMA

D0-D3

MC68HC11

MC6809 MT88L85 MT88L85

8031/8051

8080/8085

Φ2

RS0

D0-D3

R/W/WR

DS/RD

A8-A15

AD0-AD3

RS0

D0-D3

R/W/WR

DS/RD

A0-A15

D0-D3

R/W

RS0

D0-D3

R/W/WR

DS/RD

A8-A15

ALE

D0-D3

RS0

DS/RD

R/W/WR

(a)

(b)

MT88L85 Advance Information

4-80

Tabl e 3. Intern al Re gist er Fun ctions

Ta ble 4. CRA B it Positions

Ta ble 5. CRB B it Positions

Motorola Intel

RS0 R/W WR RD FUNCTION

0001

Write to Transmit

Da ta Registe r

0110

Read from Receive

Da ta Registe r

1001

Write to Control Register

1110

Read from Status Register

b3 b2 b1 b0

R SEL IRQ CP/DTMF TOUT

b3 b2 b1 b0

C/R S/D TEST BURST

ENABLE

Table 6. Control Register A Description

BIT NAME DESCRIPTION

b0 T OUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone output

off and places the complete DTMF transmitter circuit in power down mode. This bit

control s all transmi t tone functions.

b1 CP/DTMF Call Progre ss or DTM F Mode Sel ect. A logic high enables the r eceive call progress mode;

a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and

transmit ting DTM F signals. I n CP mode a re tang ular wave rep r esentatio n of the re ceived

tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control

specifi ed in t he A C Electrical Charact eristi cs for Call P rogress.

Note: DTMF signals cannot be detect ed when CP mode is selected .

b2 IRQ Interrupt Enable. A logic high enable s the interrupt function; a logic low de-activates the

interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,

b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been

received fo r a val id guard t ime duration, or 2) the transm itter is read y for m ore data (b urst

mode only).

b3 RSEL Register Select. A logic high selects control register B for the next write cycle to the

control register address. After writing to control register B, the following control register

write cycle will be directed to cont rol register A .

Advance Information MT88L85

4-81

Table 7. C ontrol Register B Descriptio n

Table 8. Status Re gister Description

BIT NAME DESCRIPTION

b0 BURST Bu rst Mode S el ect. A logic hig h de-act ivate s burst mod e; a logi c low e nables b ur st mode.

When acti vated, the d igital co de representing a DTMF sig nal (see Table 1) can be written

to the transmit register, which will re sult in a transm it DTMF to ne burst and pause of equ al

durations (typically 51 msec). Following the pause, the status register will be updated (b1 -

Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been

enabled.

When CP mode (control register A, b1) is enabled the normal tone burst and pause

durations are extended f rom a typi cal duratio n of 51 msec to 102 mse c.

When BURST is high (de-activated) the transmit tone burst duration is determined by the

TO UT bit (control registe r A, b0).

b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both

cir cuits. A l ogic high deactivate s and puts both receiver cir cuits int o power down mod e.

b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low

selects t he dual tone (DTMF ) o utput. The single tone generation funct ion requires furt her

selecti on of either the r ow or colum n tones (l ow or hi gh group ) through t he C/ R bit (control

registe r B, b3).

b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects

a row t one outp ut. Th is funct ion is used in conjunctio n wi th the S /D bi t (control regi ster B,

b2).

BIT NAME STAT US FL AG S ET STATUS FLA G CLEARE D

b 0 IRQ Int errupt has occurred. Bit one

(b1) or bit two (b2) is set. Interrupt is inactive. Cleared aft er

Status Register is read.

b 1 T RA NSM IT DATA

(BURS T MODE ONLY)

Pause durat ion has terminat ed

and transmitter is ready for new

data.

Cleared after S tatus Registe r is

read or when in non-burst mode.

b2 RECEIVE DATA REGISTER

FULL Valid data is in the Receive Data

read.

b3 DELAYED STE ER ING Set upon the valid detect ion of

the absence of a DTMF signal. Cleared upon the detection of a

valid DTM F signal.

MT88L85 Advance Information

4-82

Figure 13 - Application Circuit (Single-Ended Input)

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

R/W/WR

VDD

St/GT

ESt

IRQ/CP

DS/RD

RS0

DTMF/CP

INPUT

DTMF

OUTPUT

C1 R1

X-tal

VDD

To µP

or µC

Notes:

R1, R2 = 100 kΩ 1%

R3 = 374 Ω 1%

R4 = 3.3 kΩ 10%

RL = 10 k Ω (min.)

C1 = 100 nF 5%

C2 = 100 nF 5%

C3 = 100 nF 10%*

X-tal = 3.579545 MHz

* Microprocessor based systems can inject undesirable noise into the supply rails.

The performance of the MT88L85 can be optimized by keeping

noise on the supply rails to a m inimu m. The decoupli ng capacit or (C3) shou ld be

conn ected close to the device an d ground loops s h ould be avoided.

MT88L85

PWDN

Advance Information MT88L85

4-83

Figure 14 - Application Notes

INITIALI ZATION PROCE DU RE

A software reset must be included at the beginning of all programs to initialize the control registers after

power up.

Description: Motorola Intel Data

RS0 R/W WR RD b3 b2 b1 b0

1) Read Status Register 1 1 1 0 X X X X

2) Write to Control Register 1 0 0 1 0 0 0 0

3) Write to Control Register 1 0 0 1 0 0 0 0

4) Write to Control Register 1 0 0 1 1 0 0 0

5) Write to Control Register 1 0 0 1 0 0 0 0

6) Read Status Register 1 1 1 0 X X X X

TYPIC AL CONTROL SE QUENCE FOR BURST MODE APPLICATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence: RS0 R/W WR RD b3 b2 b1 b0

1) Write to Control Register A 1 0 0 1 1 1 0 1

(to n e ou t, DTM F, IRQ, S elect Control Regist er B)

2) Write to Control Register B 1 0 0 1 0 0 0 0

(burst mode)

3) Write to Tra ns mi t Da ta R e gis te r 0 0 0 1 0 1 1 1

(send a digit 7)

4) Wait for an Interrupt or Poll Status Register

5) Read the Status Register 1 1 1 0 X X X X

-if bit 1 is set, the Tx is ready for the next tone, in which case ...

Write to Transmit Register 0 0 0 1 0 1 0 1

(send a digit 5)

-if b i t 2 is se t, a DT MF to n e ha s b ee n rec e ive d, i n w hic h ca se ....

Re a d th e Rece i v e Da ta R e gis te r 0 1 1 0 X X X X

-if both bits are set .. .

Re a d th e Rece i v e Da ta R e gis te r 0 1 1 0 X X X X

Write to Tra ns mi t Da ta R e gis te r 0 0 0 1 0 1 0 1

NOT E: I N THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SE T UNTIL 100 ms ( ± 2 ms) AFTER T HE DATA IS

WRITT EN TO TH E TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 2 00 ms (± 4 m s)

MT88L85 Advance Information

4-84

* Excee ding these values ma y cause perm an ent dama ge. Functi onal operati on u nder the se conditi ons is not implie d.

‡ Typ ical figures are at 25 °C a n d f or de sign ai d only: n o t g uaran te ed and not subject to prod ucti on testin g.

† Characteri stics are over recom mende d o pera ting cond itions unle ss o therwise stated.

‡ Typ ical figures are at 25 °C, VDD =3V a nd for desig n aid only: n ot guara nt eed and not subject to pro ductio n testi ng .

* See “Not es” foll owi ng AC Electrical Chara ct erist ic s Tables.

Ab solu te Maximum Rating s *

Parameter Symbol Min Max Units

1 Power supply voltage VDD-VSS VDD 6V

2 Voltage on any pin VIVSS-0.3 VDD+0.3 V

3 Current at any pin (Except VDD and VSS)10mA

4 Storage Temperatu re TST -65 +150 °C

5 Package power dissipat ion PD1000 mW

Recomme nded Operating Con ditions - Voltages are with respect to ground (VSS) unless otherwise stated.

Parameter Sym Min Typ‡Max Units Test Con di tio ns

1 Positive po wer supply VDD 2.7 3 3.6 V

2 Operating temperature TO-40 +85 °C

3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz

DC Electrical Characteristics† - VSS=0 V.

Characteristics Sym Min Typ‡Max Units Test Conditio ns

Operat ing supply volt age VDD 2.733.6V

2 Operat ing supply current IDD 3 mA Device fully enabled

3 Standby supply current 25 µA PWDN= VDD

H igh level inpu t voltage

(OSC1) VIHO 2.1 V VDD=3V

5 Low level input voltage

(OSC1) VILO 1.9 V VDD=3V

6 Steering threshold voltage VTSt 1.4 V VDD=3V

L ow level out put volt age

(OSC2) VOLO 0.1 V No load

VDD=0V

8 H igh level out put voltage

(OSC2) VOHO 2.97 V No load

VDD=3V

9 Out put lea kage current

(IRQ) IOZ 110µAV

OH=2.4 V

10 VRef output voltage VRef 1.5 V No load, VDD=3V

11 VRef output re si sta nce ROR 1.3 kΩ

12 D

Low level input voltage VIL .9 V

13 H igh level inpu t voltage V IH 2.1 V

14 Inpu t leakage current IIZ 10 µAV

IN=VSS to VDD

15 Data

Bus Sou rce current IOH -6.6 mA VOH=2.4V

16 Sink current IOL 4.0 mA VOL=0.4V

17 ESt

and

St/GT

Sou rce current IOH -3.0 mA VOH=2.4V

18 Sink current IOL 4mAV

OL=0.4V

19 IRQ/

CP Sink current IOL 16 mA VOL=0.4V

Advance Information MT88L85

4-85

‡ Typ ical figures are at 25°C and fo r desig n aid o nly: n ot guara ntee d and n ot subje ct to prod uctio n testing .

† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.

† Characteri stics are over recom mende d o pera ting conditi ons unle ss o therwise stated.

‡ Typ ical figures are at 25°C, VDD = 3V, and fo r desig n a id only: not gu arante ed and not subj ect to produ ctio n t estin g .

* *Se e “Notes” foll owi ng AC Elect rical Charact eri sti cs Tables.

Electrical Characteristics

Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=3V, TO=25°C.

Characteristics Sym Min Typ‡M ax Un its Test Con di tio ns

1 Input leakage current IIN ±100 nA VSS ≤ VIN ≤ VDD

2 Input re sista n ce RIN 10 MΩ

3 Input offset volta ge VOS 25 mV

4 Power supply reject ion PSRR 60 dB 1 kHz

5 Co mm on mo de rejecti on CMR R 60 dB 0.75 ≤ VIN ≤ 4.25V

6 DC open loop voltage gain AVOL 65 dB

7 Un ity gain ba n dwidt h BW 1. 5 MH z

8 O utput volt age swing VO4.5 Vpp RL ≥ 100 k Ω to VSS

9 Allowable capacitive load (GS) CL100 pF

10 Allowable resistive load (GS) RL50 kΩ

11 Co mm on mo de ran ge VCM 3.0 Vpp No Load

MT88 L85 AC Electrical Cha racterist ics † - Volta ges are with respe ct to ground (VSS) unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Notes*

Valid input signal levels

(each tone of composite

signal)

-34 -4 dBm 1,2,3,5,6

min @ VDD=3.6V

max @ VDD=2.7V

15.4 489 mVRMS 1,2,3,5,6

AC Electrical Characteristics† - V oltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz.

Characteristics Sym Min Typ‡Max Units Notes*

Positive tw ist accept 8 dB 2,3,6,9

2 Negative twist accept 8 dB 2,3,6,9

3 Freq. deviati on accept ±1.5% ± 2Hz 2 ,3,5

4 Freq. deviation reject ±3.5% 2,3,5

5 Third tone tolerance -16 dB 2 ,3,4, 5,9 ,10

6 Noise tolerance -12 dB 2 ,3,4,5,7,9,10

7 Dial tone tole ra nce 22 dB 2 ,3, 4, 5,8 ,9

MT88L85 Advance Information

4-86

† Characteri stics are over recom mende d o pera ting cond itions unle ss o therwise stated

‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing

† Characteri stics are over recom mende d o pera ting cond itions unle ss o therwise stated

‡ Typical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unle ss o therwi se stated.

Characteristics Sym Min Typ‡Max Units Conditions

1 Ac ce pt Bandwidth fA310 500 Hz @ -25 dBm,

N ote 9

2 Lower freq. (REJECT) fLR 290 Hz @ -25 dBm

3 Upper freq. (REJECT) fHR 540 Hz @ -25 dBm

4 Call progress tone dete ct level (total

power) -30 dBm

AC Electrical Characteristics†- DTMF Reception - Typ ical DTM F tone accep t a nd reject req uireme nts. Actual

values are user selectable as per Figures 5, 6 and 7.

Characteristics Sym Min Typ‡Max Units Conditions

1 Minimum tone accept durati on tREC 40 ms

2 Maximum tone reject duration tREC 20 ms

3 Minimum int erdigit pause durat ion tID 40 ms

4 Maximum tone drop-out duration tOD 20 ms

AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Conditions

Tone present dete ct time tDP 5 11 14 ms Not e 11

2 Tone absent detect ti me tDA 0.5 4 8.5 ms Not e 11

3 Delay St to b3 tPStb3 13 µs See Fi gure 7

4 Delay St to RX0-RX3tPStRX 8µs See Figure 7

Tone burst duration tBST 50 52 ms DTMF mode

6 Tone pause duration tPS 50 52 ms DTMF mode

7 Tone burst duration (extended) tBSTE 1 00 104 m s Cal l Progress mode

8 Tone pause duration (extended) tPSE 100 104 m s Cal l Progress mode

9 High group output level VHOUT -15.1 -11.1 dBm RL=10kΩ

10 Low group output level VLOUT -17.1 -13.1 dBm RL=10kΩ

11 Pre-emphasis dBP2dBR

=10kΩ

12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth

13 RL=10kΩ

14 Frequency deviation fD±0.7 ±1.5 % fC=3.579545 M Hz

15 Ou tput load resista n ce RLT 10 50 kΩ

16 X

Crystal/clock frequ en cy fC3.5759 3.5795 3.5831 MHz

17 Clock input rise and fall time t CLRF 110 ns E xt. cl o c k

18 Clock input duty c ycle DCCL 40 5 0 60 % E xt. clo ck

19 Capaci tive loa d (OSC2) CLO 30 pF

Advance Information MT88L85

4-87

† Ch aracteri stics are over recommended operating conditions unless otherwise stated

‡ Typ ical figures are at 25°C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing

NOTES: 1) dBm=decibels above or below a reference power of 1 mW int o a 600 ohm load.

2) Digit se que nc e co ns is ts o f all 16 D TM F to nes.

3) Tone duration=40 ms. Tone pause=40 ms.

4) Nominal DTMF frequencies are used.

5) Both tones in the composite signal have an equal amplitude.

6) The ton e pa ir is de v iated b y ± 1 .5 %±2 H z.

7) Band w id th li mited ( 3 k H z) G au s si an no is e.

8) The preci se dial tone frequencies are 350 and 440 Hz (±2 %).

9) Guaranteed by design and ch aracterization. Not subject to production testing.

10) R e fe ren c ed to the lowest amp li tu de tone in th e D TM F si gn al .

11) For gu ar d t im e c a lc ul ati on p ur p os es .

Fi gure 15 - DS /RD/WR Clock Pulse

AC Electrical Characteristics†- MPU Interface - Voltag es are with respe ct to ground (VSS), unless otherwi se stated .

Characteristics Sym Min Typ‡Max Units Conditions

1DS/RD

/WR clock frequency fCYC 4.0 M Hz Figure 15

2DS/RD

/WR cycle period tCYC 2 50 ns Fi gure 15

3DS/RD

/WR low pulse width tCL 1 50 ns Figure 15

4DS/RD

/WR high pulse width t CH 1 00 n s Fi gure 15

5DS/RD

/WR rise and fall tim e t R,tF20 ns Figure 15

6R/W

setup time tRWS 0 ns Figures 1 6 & 17

7R/W

hold time tRWH 26 ns Figures 16 & 17

8 Address setup time (RS 0) tAS 0 ns Fi gures 16 - 19

9 Address hold time (RS0) tAH 26 ns Figures 1 6 - 19

10 Data hold time (read) tDHR 22 ns Figures 1 6 - 19

11 DS/RD to valid data delay (read) tDDR 80 100 ns Figures 16 - 19

12 Data setup time (writ e) tDSW 35 ns Figures 1 6 - 19

13 Data hold time (write) tDHW 10 ns Fi gures 16 - 19

14 Chip select setup time tCSS 45 ns Figures 1 6 - 19

15 Chip select hold time tCSH 40 ns Figures 16 - 19

tCYC

tCH tCL

DS/RD/WR

MT88L85 Advance Information

4-88

Figure 16 - MC6800/MC6802/MC6809 Timing Diagram

➀ tDSW is fr o m da ta to DS fal li ng ed ge ; t CSH i s f r om D S r isin g ed ge to CS risin g edge

Fi gure 17 - M C6 8HC11 Bus Tim ing (w ith m ultipl exed a ddress and d ata bu ses)

Q clk*

A0-A15

(RS0)

R/W(read)

Read Data

(D3-D0)

R/W (wri te)

Write data

(D3-D0)

CS = (E + Q).Addr [MC6809]

CS = VMA.Addr [MC6800, MC6802]

*microprocess or pin

tRWS tRWH

16 byte s of Addr

tDDR

tDSW➀tDHW

tCSH➀

tCSS

tAS tAH

tAS tCSS tCSH➀

tAH

tDHR

R/W

Read

AD3-AD0

(RS0, D0-D3)

Write

AD3-AD0

(RS0-D0-D3)

Addr *

non-mux

AS *

CS = AS.Addr

* microprocessor pi ns

tRWS

tRWH

tAS tDDR tDHR

Data

tAH

tDSW tDHW

tCSH

tCSS

Hi gh Byte of Addr

Addr

Advance Information MT88L85

4-89

Fi gure 18 - 8 031 /805 1/8085 Rea d Timing Dia gram

Figu re 19 - 80 31/8 05 1/80 85 Write Ti min g Diag ra m

ALE*

P0*

(RS0,

D0-D3)

P2 *

(Addr)

CS = ALE.Addr

* microprocessor pins

tCSS

tAS tAH tDDR tDHR

Data

A8-A15 Address

tCSH

A0-A7

ALE*

P0*

(RS0,

D0-D3)

P2 *

(Addr)

CS = ALE.Addr

* microprocessor pi ns

tCSS

tAS tAH tDSW tDHW

Data

A8-A15 Address

tCSH

A0-A7

MT88L85 Advance Information

4-90

NOTES: