W83176G-735 - Winbond Electronics Corporation America

W83176R-735

W83176G-735

Winbond 3 DIMM DDR ZERO

DELAY BUFFER

Date: Mar/31/2006 Revision: 1.1

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- I - Revision 1.1

W83176R-735/W83176G-735 Data Sheet Revision History

PAGES DATES VERSION VERSION

ON WEB MAIN CONTENTS

1 n.a. n.a.

All of the versions before 0.50 are for internal

use.

2 3.7 12/18/03 0.5 n.a.

Correction IC version, add register default

value and correction some description and

default value

3 05/03/04 1.0 1.0 Update to web

4 03/31/06 1.1 1.1 Add lead-free part number W83176G-735

Please note that all data and specifications are subject to change without notice. All the trademarks of

products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury. Winbond

customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- II -

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 1

2. PRODUCT FEATURES .............................................................................................................. 1

3. PIN CONFIGURATION............................................................................................................... 1

3.1 Block diagram ................................................................................................................. 2

4. PIN DESCRIPTION..................................................................................................................... 3

4.1 Clock Outputs ................................................................................................................. 3

4.2 Power Pins...................................................................................................................... 3

5. REGISTER 0 ~ REGISTER 4 RESERVED.............................................................................. 4

5.1 Register 5 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH).......................... 4

5.2 Register 6 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH).......................... 4

6. ACCESS INTERFACE................................................................................................................ 5

6.1 Block Write protocol........................................................................................................ 5

6.2 Block Read protocol........................................................................................................ 5

6.3 Byte Write protocol ......................................................................................................... 5

6.4 Byte Read protocol ......................................................................................................... 5

7. SPECIFICATIONS ...................................................................................................................... 6

7.1 ABSOLUTE MAXIMUM RATINGS ................................................................................. 6

7.2 AC CHARACTERISTICS................................................................................................ 6

7.3 DC CHARACTERISTICS................................................................................................ 7

8. ORDERING INFORMATION ...................................................................................................... 8

9. HOW TO READ THE TOP MARKING........................................................................................ 8

10. PACKAGE DRAWING AND DIMENSIONS................................................................................ 9

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- 1 - Revision 1.1

1. GENERAL DESCRIPTION

The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735

can support 3 D.D.R. DRAM DIMMs.

The W83176R-735 provides I2C serial bus interface to program the registers to enable or disable each

clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.

2. PRODUCT FEATURES

• Zero-delay clock outputs

• Feedback pins for synchronous

• Supports up to 3 D.D.R. DIMMs

• One pairs of additional outputs for feedback

• Low Skew outputs (< 100ps)

• Supports 400MHz D.D.R. SDRAM

• I

2C 2-Wire serial interface and supports Byte or Block Date RW

• 48-pin SSOP package

3. PIN CONFIGURATION

GND 1 48 GND

CLKC0 2 47 CLKC5

CLKT0 3 46 CLKT5

VDD 4 45 VDD

CLKT1 5 44 CLKT6

CLKC1 6 43 CLKC6

GND 7 42 GND

GND 8 41 GND

CLKC2 9 40 CLKC7

CLKT210 39CLKT7

VDD 11 38 VDD

* SCLK 12 37 SDATA *

C L K _ IN T 1 3 3 6 N /C

N/C 14 35 FB_INT

VDD 15 34 VDD

A V D D 16 33 FB _O U TT

A G N D 17 32 N C

GND 18 31 GND

CLKC319 30CLKC8

CLKT320 29CLKT8

VDD 21 28 VDD

CLKT422 27CLKT9

CLKC423 26CLKC9

GND 24 25 GND

*: Internal pull-up resistor 120K to VDD

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- 2 -

3.1 Block diagram

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- 3 - Revision 1.1

4. PIN DESCRIPTION

IN - Input

OUT - Output

I/O - Bi-directional Pin

*- Internal 120kΩ pull-up

4.1 Clock Outputs

SYMBOL PIN I/O FUNCTION

CLKC[9:0] 26,30,40,43,4

7,23,19,9,6,2 OUT Complementory Clocks of differential pair outputs

CLKT[9:0] 27,29,39,44,4

6,22,20,10,5,3 OUT True Clocks of differential pair outputs

SDATA * 37 I/O Serial data of I2C 2-wire control interface

Internal pull-up resistor 120K to Vdd

SCLK * 12 IN Serial clock of I2C 2-wire control interface

Internal pull-up resistor 120K to Vdd

CLK_INT 13 IN

True reference clock input, 3.3V tolerant input

NC 14, 32,36 NONE Not connected

FB_OUTT 33 OUT

True Feedback output, dedicated for external

feedback. It switches at the same frequency as the

CLK. This output must be wired to FB_INT.

FB_INT 35 IN

True Feedback input, provides feedback signal to the

internal PLL for synchronization with CLK_INT to

eliminate phase error.

4.2 Power Pins

SYMBOL PIN FUNCTION

GND 1,7,8,18,24,25,31,41,42,48 　 Ground

VDD 4,11,15,21,28,34,38,45 Power Supply 2.5V

AVDD 16 Analog power supply, 2.5V

AGND 17 Analog ground

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- 4 -

5. REGISTER 0 ~ REGISTER 4 RESERVED

5.1 Register 5 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH)

BIT @POWERUP PIN DESCRIPTION

7 1 2,3 CLKC0,CLKT0 output control

6 1 6,5 CLKC1,CLKT1 output control

5 1 9,10 CLKC2,CLKT2 output control

4 1 19,20 CLKC3,CLKT3 output control

3 1 23,22 CLKC4,CLKT4 output control

2 1 26,27 CLKC9,CLKT9 output control

1 1 - Reserved

0 1 - Reserved

5.2 Register 6 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH)

BIT @POWERUP PIN DESCRIPTION

7 1 - Reserved

6 1 - Reserved

5 1 - Reserved

4 1 30,29 CLKC8,CLKT8 output control

3 1 40,39 CLKC7,CLKT7 output control

2 1 43,44 CLKC6,CLKT6 output control

1 1 47,46 CLKC5,CLKT5 output control

0 1 - Reserved

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- 5 - Revision 1.1

6. ACCESS INTERFACE

The W83176R-735 provides I2C Serial Bus for microprocessor to read/write internal registers. In

the W83176R-735 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C

write address is defined at 0xD4. The I2C read address is defined at 0xD5.

Block Read and Block Write Protocol

6.1 Block Write protocol

6.2 Block Read protocol

## In block mode, the command code must filled 00H

6.3 Byte Write protocol

6.4 Byte Read protocol

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- 6 -

7. SPECIFICATIONS

7.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused

inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

SYMBOL PARAMETER RATING

VDD , AVDD Voltage on any pin with respect to GND - 0.5 V to + 3.6 V

TSTG Storage Temperature - 65°C to + 150°C

TBAmbient Temperature - 55°C to + 125°C

TAOperating Temperature 0°C to + 70°C

7.2 AC CHARACTERISTICS

VDD = AVDD = 2.5V ( 5 % , TA = 0(C to +70(C, Test load = 10 pF

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Operating clock

frequency FIN 100 200 MHz

Input Clock Duty Cycle Dtin 40 60 %

Dynamic Supply Current Idd 300 mA Fin=100 to 200Mhz

Cycle to Cycle Jitter C-Cjitter 200 ps

Fout=100 to

200Mhz

Output to Output Skew Tskew 100 ps

Fout=100 to

200Mhz

Output clock Rise time Tor 650 950 ps

Fout=100 to

200Mhz

Output clock Fall time Tof 650 950 ps

Fout=100 to

200Mhz

Output clock Duty Cycle Dtot 45 55 %

Fout=100 to

200Mhz

Output differential-pair

crossing voltag Voc (Vdd/2)-

0.2

Vdd/

(Vdd/2)

+ 0.2 V Fout=100 to

200Mhz

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- 7 - Revision 1.1

7.3 DC CHARACTERISTICS

Vdd = AVDD= 2.5V ( 5 %, TA = 0(C to +70(C

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

SDATA, SCLK Input

Low Voltage SVIL 1.0 Vdc

SDATA, SCLK Input

High Voltage SVIH 2.2 Vdc

CLKIN, FBIN Input

Voltage Low VIL 0.4

Vdc

Fin=100 to 200Mhz

CLKIN, FBIN Input

Voltage High VIH 2.1 Vdc

Fin=100 to 200Mhz

Input Pin Capacitance CIN 5 pF

Output Pin

Capacitance COUT 6 pF

Input Pin Inductance LIN 7 nH

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- 8 -

8. ORDERING INFORMATION

PART NUMBER PACKAGE TYPE PRODUCTION FLOW

W83176R-735 48 PIN SSOP Commercial, 0°C to +70°C

W83176G-735 48 PIN SSOP (Pb-free

package)

Commercial, 0°C to +70°C

9. HOW TO READ THE TOP MARKING

W83176R-735

28051234

342G

W83176G-735

28051234

342GB

1st line: Winbond logo and the type number: W83176R-735/W83176G-735.

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 342 G B

342: packages made in '2003, week 42

G: assembly house ID; O means OSE, G means GR

B: IC revision

All the trade marks of products and companies mentioned in this data sheet belong to their

respective owners.

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

Publication Release Date: March 31, 2006

- 9 - Revision 1.1

10. PACKAGE DRAWING AND DIMENSIONS

Please note that all data and specifications are subject to change without notice. All the trade marks

of products and companies mentioned in this data sheet belong to their respective owners.

W83176R-735/W83176G-735

3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

- 10 -

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.