4094B 8 Stage Bus Compatible Shift/Store Register 105 WE SHEL VIRV YAP EVER AYYA+FAVIFSL Aen teak aay STROBE 1 16 Yoo A LUT WV ea RIVA TP SERIA OUTPUT iN 2 15 ENABLE 207 wl cuock 3 4a THeyh ZL ae ae 3AF-EILL Qa, 5 12 Qy hs, nat on 1104 mess Q, 7 10 Og: * aTcu Vss 8 9 Qs yt Yoo 1 - stare Vs5 * ALL INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK @ 03 04 05 06 O7 o8 ae BA vty TRH @ X-AT Sh VbD| typ | max | Bir Ny PY Po A RB se S 5V) 100] 200| ns DIP_[ SOP war VOUT RUTAP tr wv] 50! 100] ns [ye | MSMa0SaERS | @ LUTRRLES ANGLIA, NILIMBAOY I KLYRY. RAO-TCE SHANG o HME LUA ATL IAF A at et Se Yy % 3, ns PRED S. POI POMBLNNTY TTS tf iov | 50 [1007 ns _| TC40945P el| suey. _ 15sV{_40[ 80] ns |e | UPD | ele RGR GIiYIT+Frb 7 V | 420 840 T ns | Bi lev | 195] 390 [ns |e Puaner | Se CLK -> P.OUT | cune Resta [Sei cock ( ) Fi5V 135] 270 | as [BSF | aNa094B ee CU | Enable | Strobe | Oa cara ww | ea V {420} 840] ns | =3e _| mOs4BP < ai] on | as] as ; ty ' 10V | 195] 390 | ns | oZs | BU40946 Ca) rile |x |x foc] oc] a7 | ne srrooef 1 oaytl{l UST (CLK -> POUT) Fasv]a351 270 ns T MOT | mC140948 ele Allg Tx |x locloc | nel a gurpur phy ATT og 5V | 300/ 600[ ns |NS | CD4094B e S- 1 0 x | NC] NC ] Q7 | NC weremmas 2 SLIT LT (CLK -> S. OUT) 10V | 125] 250) ns | RCA | cb40s4B 4, 1 ' o lant} a2 | ac oro FLT ee . 16V $5| 180} ns | SGS | HCC4094B e Vv} 300{ 600[ ns |S1G | HFE409P | @ | 1 1 + 11 dona] a7 | ne InTeRNat 2? ity | + PA < 1 ; 7 10V | 125] 250| ns_| SSS | SCL4094B e 1_i1 [1 jc} we | ne} ourpur at hive pL [SEO EMD av aos * At the positive clock edge information in the 7th shift register Se SS it uh me 1s il 4 stage is transferred to the Ath reqister stage and the Os output. wl ' r | Mie semac St yi te iov| 2.57 5) Mt 7] Iv] 3] 5 | Miz a