0.1 GHz to 24 GHz, Low Noise,
Programmable Divider
Data Sheet HMC862A
Rev. A Document Feedback
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Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Low noise floor: −153 dBc/Hz at 100 kHz offset
Programmable frequency divider (N)
N = 1, 2, 4, or 8
Wide bandwidth: 0.1 GHz to 24 GHz
Low current consumption: 81 mA in the N = 8 divide state
HBM ESD sensitivity, Class 2 classification
FICDM ESD sensitivity, Class C3 classification
16-lead, 3 mm × 3 mm LFCSP package: 9 mm2
APPLICATIONS
Satellite communication systems
Point to point and point to multipoint radios
Military applications
Test equipment
FUNCTIONAL BLOCK DIAGRAM
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
IN
IN
GND
÷1,2,4,8
HMC862A
GND
VCC
GND
GND
VCC
OUT
OUT
GND
PACKAGE
BASE
GND
S0
S1
S2
GND
13599-001
Figure 1.
GENERAL DESCRIPTION
The HMC862A is a low noise, programmable frequency divider
in a 3 mm × 3 mm, leadless, surface-mount package. The
frequency divider, N, can be programmed to divide from 1,
2, 4, or 8 in the 0.1 GHz to 24 GHz input frequency range.
The low phase noise, wide frequency range, and flexible division
ratio make this device ideal for high performance and wideband
communication systems.
HMC862A Data Sheet
Rev. A | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
RF Specifications .......................................................................... 3
DC Specifications ......................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Divide by 1 ..................................................................................... 7
Divide by 2 .....................................................................................8
Divide by 4 .....................................................................................9
Divide by 8 .................................................................................. 10
Current Consumption (ICC) ...................................................... 11
Theory of Operation ...................................................................... 12
Input Interface ............................................................................ 12
Output Interface ......................................................................... 12
Applications Information .............................................................. 13
Evaluation Printed Circuit Board (PCB) ................................ 13
Evaluation Board Overview ...................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/2019—Rev. 0 to Rev. A
Added Thermal Resistance Section and Table 4 .......................... 5
Changes to Theory of Operation Section .................................... 12
Changes to Ordering Guide .......................................................... 15
10/2017—Revision 0: Initial Version
Data Sheet HMC862A
Rev. A | Page 3 of 15
SPECIFICATIONS
RF SPECIFICATIONS
VCC = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT CHARACTERISTICS
RF Input Frequency
Maximum Sine wave or square wave input
N = 1 18 GHz
N = 2, 4, 8 24 GHz
Minimum Square wave input1 0.1 GHz
RF Input Power Range
N = 1, 2 0.1 GHz< fIN < 18 GHz, sine or square wave input1 −15 +10 dBm
N = 2 18 GHz < fIN < 24 GHz, sine or square wave input −5 +10 dBm
N = 4, 8 0.1 GHz < fIN < 20 GHz, sine or square wave input1 −15 +10 dBm
20 GHz < fIN < 24 GHz, sine or square wave input −5 +10 dBm
Reverse Leakage
N = 1 fIN = 6 GHz, input power (PIN) = 0 dBm −10 dBm
N = 2 fIN = 6 GHz, PIN = 0 dBm −55 dBm
N = 4, 8 fIN = 6 GHz, PIN = 0 dBm −70 dBm
RF OUTPUT CHARACTERISTICS, N = 1
Output Power, Single-Ended 0.1 GHz < fIN < 10 GHz −1 +3 +5 dBm
10 GHz < fIN < 15 GHz −5 −2 +3 dBm
15 GHz < fIN < 18 GHz −11 −6 0 dBm
Single-Sideband (SSB) Residual Phase Noise
at 100 kHz Offset
fIN = 12 GHz, PIN = 5 dBm −155 dBc/Hz
Second Harmonic fIN = 6 GHz, PIN = 0 dBm −27 dBm
Third Harmonic fIN = 6 GHz, PIN = 0 dBm −6 dBm
RF OUTPUT CHARACTERISTICS, N = 2
Output Power, Single-Ended 0.1 GHz < fIN < 18 GHz 0 3 5 dBm
18 GHz < fIN < 24 GHz −3 0 +3 dBm
SSB Residual Phase Noise at 100 kHz Offset fIN = 12 GHz, PIN = 5 dBm −153 dBc/Hz
Second Harmonic (Feedthrough) fIN = 6 GHz, PIN = 0 dBm −28 dBm
Third Harmonic fIN = 6 GHz, PIN = 0 dBm −7 dBm
RF OUTPUT CHARACTERISTICS, N = 4
Output Power, Single-Ended 0.1 GHz < fIN < 18 GHz 0 2 4 dBm
18 GHz < fIN < 24 GHz −1 +3 +6 dBm
SSB Residual Phase Noise at 100 kHz Offset fIN = 12 GHz, PIN = 5 dBm −154 dBc/Hz
Second Harmonic fIN = 6 GHz, PIN = 0 dBm −35 dBm
Third Harmonic fIN = 6 GHz, PIN = 0 dBm −6 dBm
RF OUTPUT CHARACTERISTICS, N = 8
Output Power, Single-Ended 0.1 GHz < fIN < 24 GHz 0 2 4 dBm
SSB Residual Phase Noise at 100 kHz Offset fIN = 12 GHz, PIN = 5 dBm −155 dBc/Hz
Second Harmonic fIN = 6 GHz, PIN = 0 dBm −45 dBm
Third Harmonic fIN = 6 GHz, PIN = 0 dBm −7 dBm
1 A square wave input is recommended to be below 650 MHz for best phase noise performance. If a sine wave input below 650 MHz is used, it is recommended that the
drive level be >5 dBm for best operation, including phase noise. Refer to the Typical Performance Characteristics section.
HMC862A Data Sheet
Rev. A | Page 4 of 15
DC SPECIFICATIONS
VCC = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLIES
VCC Analog supply 4.75 5 5.25 V
CURRENT CONSUMPTION, ICC
N = 1 55 61 71 mA
N = 2 64 73 84 mA
N = 4 68 78 90 mA
N = 8 71 81 94 mA
DIGITAL INPUT S (S0, S1, S2)
Logic Voltage
Low 0 0.4 V
High 3 5 V
Data Sheet HMC862A
Rev. A | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
RF Input Power (IN, IN) 13 dBm
Supply Voltage (VCC) 5.5 V
Logic Inputs (S0, S1, S2) −0.5 V to (0.5 V + VCC)
Storage Temperature Range −65°C to +125°C
Reflow Temperature 260°C
Operating Temperature Range (TA) −40°C to +85°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM), JS-001-2012 Class 2
Field Induced Charged Device Model
(FICDM), JS-002
Class C3
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Thermal impedance simulated values are based on the use of
the EV1HMC862ALP3 evaluation board with the exposed pad
soldered to GND. VCC = 5 V and Divider Ratio (N) = 8.
Table 4.
Package Type Thermal Impedance (θJB) Unit
HCP-16-1 34 °C/W
ESD CAUTION
HMC862A Data Sheet
Rev. A | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
IN
IN
GND
GND
V
CC
GN
D
GN
D
V
CC
OUT
OUT
PACKAGE
BASE
GND
GND
S0
S1
S2
GND
HMC862A
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
13599-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 8, 9,
12, 14, 15
GND Ground. The backside of the package has an exposed metal ground slug that must be connected to RF/dc ground.
2 IN RF Input. This pin must be dc blocked.
3 IN RF Input, 180° Out of Phase with Pin 2 for Differential Operation. This pin must be ac grounded for single-ended
operation. DC block this pin for differential operation.
5, 6, 7 S0, S1, S2 CMOS Compatible Division Ratio Control Bits. See Table 6.
10 OUT Divider Output, 180° Out of Phase with Pin 11. This RF output must be dc blocked. See Figure 31 for proper termination.
11 OUT Divided Output. This RF output must be dc blocked. See Figure 31 for proper termination.
13, 16 VCC Supply Voltage Pins, 5 V. Connect both VCC pins to a 5 V supply. These pins are internally connected.
EPAD Exposed Pad. Exposed pad must be connected to RF/dc ground.
Data Sheet HMC862A
Rev. A | Page 7 of 15
TYPICAL PERFORMANCE CHARACTERISTICS
DIVIDE BY 1
6
–12
–10
–18
–6
–4
–2
0
2
4
0 2 4 6 8 10 12 14 16 18 20
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
+85°C
+25°C
–40°C
13599-009
Figure 3. Output Power vs. Sine Wave Input Frequency for Various
Temperatures, PIN = 0 dBm
15
–25
–20
–15
–10
–5
0
5
10
0 2 4 6 8 1012141618 2220
INPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
+85°C
+25°C
–40°C
13599-011
MAX P
IN
MIN P
IN
Figure 4. Allowable Range of Input Power vs. Sine Wave Input Frequency
for Various Temperatures
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
SQUARE 100MHz
SINE 100MHz (5dBm)
SINE 12GHz
SINE 6GHz
13599-013
Figure 5. SSB Phase Noise vs. Offset Frequency for Various Input Frequencies,
PIN = 0 dBm, TA = 25°C
6
–12
–10
–18
–6
–4
–2
0
2
4
0 2 4 6 8 10 12 14 16 18 20
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
V
CC
= 5.25V
V
CC
= 5.0V
V
CC
= 4.75V
13599-010
Figure 6. Output Power vs. Sine Wave Input Frequency for Various VCC
Voltages, PIN = 0 dBm
0
–60
–50
–40
–30
–20
–10
024681012141618
HARMONIC POWER (dBm)
OUTPUT FREQUENCY (GHz)
SECOND HARMONIC
THIRD HARMONIC
13599-012
Figure 7. Output Harmonics, PIN = 0 dBm, TA = 25°C
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
P
IN
= +10dBm
P
IN
= +5dBm
P
IN
= 0dBm
P
IN
= –5dBm
P
IN
= –10dBm
13599-014
Figure 8. SSB Phase Noise vs. Offset Frequency for Various Input Power (PIN)
Levels, fIN = 12 GHz Sine Wave, TA = 25°C
HMC862A Data Sheet
Rev. A | Page 8 of 15
DIVIDE BY 2
6
–6
–4
–2
0
2
4
024681012141618202224
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
+85°C
+25°C
–40°C
13599-021
Figure 9. Output Power vs. Sine Wave Input Frequency for Various
Temperatures, PIN = 0 dBm
15
–25
–20
–15
–10
–5
0
5
10
024681012141618 242220
INPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
13599-023
+85°C
+25°C
–40°C
MAX P
IN
MIN P
IN
Figure 10. Allowable Range of Input Power vs. Sine Wave Input Frequency
for Various Temperatures
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
SQUARE 100MHz
SINE 100MHz (5dBm)
SINE 18GHz
SINE 12GHz
SINE 6GHz
13599-025
Figure 11. SSB Phase Noise vs. Offset Frequency for Various Input
Frequencies, PIN = 0 dBm, TA = 25°C
6
–6
–4
–2
0
2
4
024681012141618 242220
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
V
CC
= 5.25V
V
CC
= 5.00V
V
CC
= 4.75V
13599-022
Figure 12. Output Power vs. Sine Wave Input Frequency for Various VCC
Voltages, PIN = 0 dBm
0
–60
–50
–40
–30
–20
–10
024681012
HARMONIC POWER (dBm)
OUTPUT FREQUENCY (GHz)
FEEDTHROUGH
THIRD HARMONIC
13599-024
Figure 13. Output Harmonics, PIN = 0 dBm, TA = 25°C
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
P
IN
= +10dBm
P
IN
= +5dBm
P
IN
= 0dBm
P
IN
= –5dBm
P
IN
= –10dBm
13599-026
Figure 14. SSB Phase Noise vs. Offset Frequency for Various Input Power (PIN)
Levels, fIN = 12 GHz Sine Wave, TA = 25°C
Data Sheet HMC862A
Rev. A | Page 9 of 15
DIVIDE BY 4
6
–2
–1
0
1
2
3
4
5
024681012141618202224
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
+85°C
+25°C
–40°C
13599-033
Figure 15. Output Power vs. Sine Wave Input Frequency for Various
Temperatures, PIN = 0 dBm
15
10
5
0
–5
–10
–15
–20
–25
024222018161412108642
INPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
13599-027
+85°C
+25°C
–40°C
MAX P
IN
MIN P
IN
Figure 16. Allowable Range of Input Power vs. Sine Wave Input Frequency
for Various Temperatures
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
SQUARE 100MHz
SINE 100MHz (5dBm)
SINE 18GHz
SINE 12GHz
SINE 6GHz
13599-037
Figure 17. SSB Phase Noise vs. Offset Frequency for Various Input
Frequencies, PIN = 0 dBm, TA = 25°C
6
–2
–1
0
1
2
3
4
5
024681012141618202224
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
V
CC
= 5.25V
V
CC
= 5.00V
V
CC
= 4.75V
13599-034
Figure 18. Output Power vs. Sine Wave Input Frequency for Various VCC
Voltages, PIN = 0 dBm
0
–60
–50
–40
–30
–20
–10
0123456
HARMONIC POWER (dBm)
OUTPUT FREQUENCY (GHz)
FEEDTHROUGH
SECOND HARMONIC
THIRD HARMONIC
13599-036
Figure 19. Output Harmonics, PIN = 0 dBm, TA = 25°C
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
P
IN
= +10dBm
P
IN
= +5dBm
P
IN
= 0dBm
P
IN
= –5dBm
P
IN
= –10dBm
13599-038
Figure 20. SSB Phase Noise vs. Offset Frequency for Various Input Power (PIN)
Levels, fIN = 12 GHz Sine Wave, TA = 25°C
HMC862A Data Sheet
Rev. A | Page 10 of 15
DIVIDE BY 8
6
–2
–1
0
1
2
3
4
5
024681012141618202224
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
+85°C
+25°C
–40°C
13599-045
Figure 21. Output Power vs. Sine Wave Input Frequency for Various
Temperatures, PIN = 0 dBm
15
–25
–20
–15
–10
–5
0
5
10
024681012141618 242220
INPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
13599-035
+85°C
+25°C
–40°C
MAX P
IN
MIN P
IN
Figure 22. Allowable Range of Input Power vs. Sine Wave Input Frequency
for Various Temperatures
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
SQUARE 100MHz
SINE 100MHz (5dBm)
SINE 18GHz
SINE 12GHz
SINE 6GHz
13599-049
Figure 23. SSB Phase Noise vs. Offset Frequency for Various Input
Frequencies, PIN = 0 dBm, TA = 25°C
6
–2
–1
0
1
2
3
4
5
024681012141618202224
OUTPUT POWER (dBm)
SINE WAVE INPUT FREQUENCY (GHz)
V
CC
= 5.25V
V
CC
= 5.00V
V
CC
= 4.75V
13599-046
Figure 24. Output Power vs. Sine Wave Input Frequency for Various Vcc
Voltages, PIN = 0 dBm
0
–70
–60
–50
–40
–30
–20
–10
0 0.51.01.52.02.53.0
HARMONIC POWER (dBm)
OUTPUT FREQUENCY (GHz)
FEEDTHROUGH
SECOND HARMONIC
THIRD HARMONIC
13599-048
Figure 25. Output Harmonics, PIN = 0 dBm, TA = 25°C
–
115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
100 1k 10k 100k 1M
SSB PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
P
IN
= +10dBm
P
IN
= +5dBm
P
IN
= 0dBm
P
IN
= –5dBm
P
IN
= –10dBm
13599-050
Figure 26. SSB Phase Noise vs. Offset Frequency for Various Input Power (PIN)
Levels, fIN = 12 GHz Sine Wave, TA = 25°C
HMC862A Data Sheet
Rev. A | Page 12 of 15
THEORY OF OPERATION
The HMC862A is a wideband, configurable RF divider with
minimal additive phase noise.
The divide ratio, N, can be programmed to N = 1, 2, 4, or 8 by
setting the digital input pins—S0, S1, and S2—to the logic high
(1) or logic low (0) states indicated in Table 6.
Table 6. Programming Truth Table for Frequency Division
Ratios1
S0 S1 S2 Divide Ratio (N)
0 0 0 1
1 0 0 2
1 1 0 4
1 1 1 8
1 0 means logic low and 1 means logic high.
The HMC862A does not support any other combination of the S0,
S1, and S2 programming states other than those listed in Table 6.
Using other programming states causes the HMC862A to
generate an unstable output.
Enable the HMC862A by applying a voltage (VCC) to the supply
pins, VCC. These pins are internally connected.
Note that the VCC voltage must be applied before the logic level
signals (S0, S1, and S2) can be driven to a logic high to prevent
the ESD diodes from turning on.
The HMC862A toggles on the rising edge of the IN input for all
divide ratios where N = 1, 2, 4, or 8.
INPUT INTERFACE
The HMC862A can be driven by differential or single-ended
input signals, and can provide differential or single-ended
output signals.
Figure 28 shows the input interface schematic for the IN and
IN pins.
IN IN
50Ω50Ω
13599-053
Figure 28. Input Interface Schematic
For differential input signals, ac couple the IN and IN pins as
shown in Figure 29. Off-chip termination is not required because
the IN and IN pins have internal 50 Ω termination resistors.
For single-ended input signals, ac couple the IN input. AC
ground the IN pin as close to the IN pin as possible.
IN
IN
IN
IN
13599-054
Figure 29. Recommended Input Configuration for Single-Ended Operation
(Left) and Differential Operation (Right)
OUTPUT INTERFACE
Figure 30 shows the output interface schematic for the OUT
and OUT pins.
OUT OUT
50Ω50Ω
13599-055
Figure 30. Output Interface Schematic
To provide a differential output or two single-ended outputs, ac
couple the OUT and OUT pins. Off-chip termination is not
required because the OUT and OUT pins have internal 50 Ω
termination resistors.
If only one output pin is used, connect the unused output pin to
ground through a capacitor and a 50 Ω termination
OUT
OUT
OUT
OUT
13599-056
Figure 31. Recommended Output Configuration for Single-Ended Operation
(Left) and Differential Operation (Right)
Data Sheet HMC862A
Rev. A | Page 13 of 15
APPLICATIONS INFORMATION
EVALUATION PRINTED CIRCUIT BOARD (PCB)
13599-100
FOUT
600-01663-00-1
NFOUT
FIN
S0 S2
S1
GND VCC
GND
NFIN
J5
C6
J7
J1
C1
C2
C3
C4
U1
J3
C5
C7 +
J2 J4
R1
R2 R3
J6
Figure 32. Evaluation PCB
13599-101
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
GND
IN
IN
GND
÷1,2,4,8
GND
V
CC
GND
GND
V
CC
OUT
OUT
GND
S0
S1
S2
GND
K_SRI-NS
J1
K_SRI-NS
J2
C1
100nF
C2
100nF
J7
J6
K_SRI-NS
J3
K_SRI-NS
J4
C3
100nF
C4
100nF
NC
C7
2.2µF
C5
100nF
+
C6
1nF
U1
HMC862ALP3E
21
43
65
J5
87759-0614
R1
10kΩ
R2
10kΩ
R3
10kΩ
Figure 33. Evaluation PCB Schematic
HMC862A Data Sheet
Rev. A | Page 14 of 15
EVALUATION BOARD OVERVIEW
Use the EV1HMC862ALP3 evaluation board to evaluate the
HMC862A.
The HMC862A is enabled by applying 5 V between J6 (VCC)
and J7 (GND). Note that J6 only provides power to Pin 13 on
the HMC862A; however, because Pin 13 and Pin 16 are
internally connected, both VCC pins receive power.
The divide ratio, N, is selected by inserting pin jumpers on
Component J5, as shown in Table 7. When installed, a jumper
pulls the digital input pin to ground and sets a logic low. When
removed, the R1, R2, and R3 pull-up resistors pull the digital
input to VCC and set a logic high.
Table 7. Jumper Configuration for EV1HMC862ALP3
Divide Ratio (N) S0 Jumper S1 Jumper S2 Jumper
1 Installed Installed Installed
2 Open Installed Installed
4 Open Open Installed
8 Open Open Open
By default, the evaluation board is set up to accept a single-
ended input and provide a differential output. A differential
input can be used by removing Component C5; a single-ended
output can be generated by terminating J4 with a 50 Ω
termination.
It is recommended that the circuit board used in the application
use RF circuit design techniques with a 50 Ω impedance on the
signal lines and with the package ground leads and backside
ground pad connected directly to the ground plane. Use a
sufficient number of via holes to connect the top and bottom
ground planes. The evaluation circuit board shown is available
from Analog Devices, Inc., upon request.
Table 8. List of Materials for EV1HMC862ALP3
Item Description
J1 to J4 PCB-mount K connector
J5 DC connector header, Molex 2 mm
C1 to C5 ATC550L104KTT, 100 nF, 16 V, broadband capacitor,
0402 package
C6 1000 pF capacitor, 0603 package
C7 2.2 μF capacitor, tantalum, 3216 package
R1 to R3 10 kΩ resistor, 0402 package
J6, J7 Mill-Max 0.040 inch diameter PC pin, 3101-2-00-21-00-
00-08-0
U1 HMC862A, programmable divider
Heatsink Custom heatsink, alumimum
PCB 600-01663-00-1 evaluation board
Data Sheet HMC862A
Rev. A | Page 15 of 15
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.95
1.70 SQ
1.50
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
58
9
12
13
4
EXPOSED
PAD
0.45
0.40
0.35
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.90
0.85
0.80
03-15-2017-B
PKG-004863
COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Lead Finish
MSL
Rating2 Package Option
HMC862ALP3E −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] 100% Matte Sn MSL3 HCP-16-1
HMC862ALP3ETR −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] 100% Matte Sn MSL3 HCP-16-1
EV1HMC862ALP3 Evaluation Board
1 The HMC862ALP3E and HMC862ALP3ETR are RoHS compliant.
2 The maximum peak reflow temperature is 260°C. See the Absolute Maximum Ratings section for more information.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13599-0-4/19(A)
