ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 1/13
Revision History :
Revision 1.0 (Jul. 5, 2007)
- Original
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 2/13
PSRAM 8-Mbit (512K x 16)
Pseudo Static RAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 20 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The M24D816512DA is a high-performance CMOS Pseudo
Static RAM organized as 512K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( 1CE HIGH or CE2 LOW or both BHE and
BLE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected ( 1CE
HIGH or CE2 LOW), outputs are disabled ( OE HIGH), both
Byte High Enable and Byte Low Enable are disabled
(BHE ,BLE HIGH), or during a write operation ( 1CE LOW
and CE2 HIGH and WE LOW). Writing to the device is
accomplished by taking Chip Enable( 1CE LOW and CE2
HIGH) and Write Enable ( WE ) input LOW. If Byte Low
Enable ( BLE ) is LOW, then data from I/O pins (I/O0through
I/O7), is written into the location specified on the address pins
(A0 through A18). If Byte High Enable ( BHE ) is LOW, then
data from I/O pins (I/O8 through I/O15) is written in to the
location specified on the address pins (A0 through
A18).Reading from the device is accomplished by taking Chip
Enables ( 1CE LOW and CE2 HIGH) and Output Enable
(OE )LOW while forcing the Write Enable ( WE ) HIGH. If
Byte Low Enable ( BLE ) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable ( BHE ) is LOW, then data from
memory will appear on I/O8 to I/O15. Refer to the truth table for
a complete description of read and write modes..
Logic Block Diagram
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 3/13
Pin Configuration[2, 3]
48-Ball VFBGA
Top View
Product Portfolio [4]
Power Dissipation
Operating ICC(Ma)
VCC Range (V)
f = 1MHz f = fmax
Standby ISB2(µA)
Product
Min. Typ.[4] Max.
Speed(ns)
.Typ.[4] Max. .Typ.[4] Max. .Typ. [4] Max.
55 20 35
M24D816512DA 1.7 1.8 1.95
70
3 5
18 25
32 70
Note:
2.Ball G2, H6 and E3 can be used to upgrade to a 16-Mbit, 32-Mbit and a 64-Mbit density, respectively.
3.NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C. Tested initially and after design changes that may affect the parameters.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 4/13
Power-up Characteristics
The initialization sequence is shown in Figure1. Chip Select should be 1CE HIGH or CE2 LOW for at least 200 µs after VCC has
reached a stable value. No access must be attempted during this period of 200 µs.
Parameter Description Min. Typ. Max. Unit
Tpu 1CE LOW and CE2 HIGH After Stable VCC 200 µs
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 5/13
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to
Ground Potential . ............................−0.2V to VCCMAX + 0.3V
DC Voltage Applied to Outputs
in High-Z State[5, 6, 7] ...................... −0.2V to VCCMAX + 0.3V
DC Input Voltage[5, 6, 7].................... −0.2V to VCCMAX + 0.3V
Output Current into Outputs (LOW) ...............................20 mA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range Ambient
Temperature (TA) VCC
Industrial −40°C to +85°C 1.7V to 1.95V
DC Electrical Characteristics (Over the Operating Range)[5,6,7]
-55 -70
Parameter Description Test Conditions Min. Typ
.[4] Max. Min. Typ.
[4] Max. Unit
VCC Supply Voltage 2.7 1.8 1.95 1.7 1.8 1.95 V
VOH Output HIGH
Voltage
IOH = −0.1 mA
VCC = 1.7V to 1.95V
VCC-
0.2
VCC-
0.2 V
VOL Output LOW
Voltage
IOL = 0.1 mA
VCC = 1.7V to 1.95V 0.2 0.2 V
VIH Input HIGH
Voltage VCC = 1.7V to 1.95V 0.8*
VCC VCC+
0.3V
0.8*
VCC VCC
+0.3V V
VIL Input LOW Voltage VCC = 1.7V to 1.95V -0.2 0.2*
VCC -0.2 0.2*
VCC V
IIX Input Leakage
Current GND ≤VIN ≤ V
CC -1 +1 -1 +1
µA
IOZ Output Leakage
Current GND ≤ V
OUT ≤ V
CC -1 +1 -1 +1
µA
f = fMAX = 1/tRC
VCC = VCCMAX
IOUT = 0mA
CMOS levels
20 35 18 25 mA
ICC VCC Operating
Supply Current
f = 1 MHz
3 5
3 5 mA
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
1CE ≥ V
CC−0.2V or CE2 ≤ 0.2V
VIN ≥ V
CC − 0.2V or VIN ≤ 0.2V,
f = 0, VCC = VCCMAX
32 40 32 40 µA
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance 8 pF
COUT Output Capacitance
TA = 25°C, f = 1 MHz
VCC = VCC(typ) 8 pF
Thermal Resistance[8]
Parameter Description Test Conditions BGA Unit
ΘJA Thermal Resistance(Junction to Ambient) 56 °C/W
ΘJC Thermal Resistance (Junction to Case)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51. 11 °C/W
Notes:
5.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
6.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
7.Overshoot and undershoot specifications are characterized and are not 100% tested.
8.Tested initially and after any design or process changes that may affect these parameters.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 6/13
AC Test Loads and Waveforms
Parameters 1.8V (VCC) Unit
R1 14000 Ω
R2 14000 Ω
RTH 7000 Ω
VTH 0.90 V
Switching Characteristics Over the Operating Range [9, 10, 11, 12]
-55 -70
Parameter Description
Min. Max. Min. Max.
Unit
Read Cycle
tRC[14] Read Cycle Time 55 80000 70 80000 ns
tCD [15] Chip Deselect Time 1CE = HIGH orCE2 = LOW,
BLE /BHE High Pulse Time
5 5
ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE 1CE LOW and CE2 HIGH to Data Valid 55 70
ns
tDOE OE LOW to Data Valid 25 35
ns
tLZOE OE LOW to Low Z[10, 11, 13] 5 5
ns
tHZOE OE HIGH to High Z[10, 11, 13] 20 25
ns
tLZCE 1CE LOW and CE2 HIGH to Low Z[10, 11, 13] 10 10
ns
tHZCE 1CE HIGH or CE2 LOW to High Z[10, 11, 13] 20 25
ns
tDBE BLE /BHE LOW to Data Valid 55 70
ns
tLZBE BLE /BHE LOW to Low Z[10, 11, 13] 5 5
ns
tHZBE BLE /BHE HIGH to Low Z[10, 11, 13] 20 25
ns
Notes:
9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels
of VCC(typ.)/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and
Waveforms” section.
10.At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V)
11.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12.The internal Write time of the memory is defined by the overlap of WE , 1CE = VIL and CE2 = VIH, BHE and/or BLE = VIL.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input
set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13.High-Z and Low-Z parameters are characterized and are not 100% tested.
14.If invalid address signals shorter than min. tRC are continuously repeated for 80 µs, the device needs a normal read timing (tRC)
or needs to enter standby state at least once in every 80 µs.
15.Whenever 1CE = HIGH or CE2 = LOW, BHE /BLE are taken inactive, they must remain inactive for a minimum of 5 ns.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 7/13
Switching Characteristics Over the Operating Range[9, 10, 11, 12] (continued)
-55 -70 Unit
Parameter Description Min. Max. Min. Max.
Write Cycle [12]
tWC Write Cycle Time 50 80000 70 80000 ns
tSCE 1CE LOW and CE2 HIGH to Write
End 50 60 ns
tAW Address Set-Up to Write End 50 60 ns
tCD[15]
Chip Deselect Time 1CE = HIGH or
CE2 = LOW, BLE /BHE High
Pulse Time
5 5 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 45 50 ns
tBW BLE /BHE LOW to Write End 50 60 ns
tSD Data Set-Up to Write End 25 25 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[10, 11, 13] 20 25
ns
tLZWE WE HIGH to Low-Z[10, 11, 13] 10 10 ns
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 8/13
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
Read Cycle 2 (OE Controlled)[15, 17]
Notes:
15. Device is continuously selected. OE , 1CE = VIL and CE2 = VIH.
16. WE is HIGH for Read Cycle.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 9/13
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 15, 18, 19]
Notes:
18.Data I/O is high impedance if OE ≥ V
IH.
19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 10/13
Switching Waveforms (continued)
Write Cycle 2 ( 1CE or CE2 Controlled) [12, 13, 15, 18, 19]
Write Cycle 3 (WE Controlled, OE LOW)[15, 19]
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 11/13
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, O
E
LOW) [12, 15, 18, 19]
Truth Table[20]
1CE CE2 WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X X High Z Deselect/Power-Down Standby (ISB)
X L X X X X High Z Deselect/Power-Down Standby (ISB)
X X X X H H High Z Deselect/Power-Down Standby (ISB)
L H H L L L Data Out (I/O0–I/O15) Read Active (ICC)
L H H L H L Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z Read Active (ICC)
L H H L L H
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z Read Active (ICC)
L H H H L L High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (ICC)
L H H H L H High Z Output Disabled Active (ICC)
L H L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC)
L H L X H L
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z Write (Lower Byte Only) Active (ICC)
L H L X L H
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z Write (Upper Byte Only) Active (ICC)
Note:
20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 12/13
Ordering Information
Speed (ns) Ordering Code Package Type Operating Range
55 M24D816128DA-55BIG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial
70 M24D816128DA-70BIG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm)
ESMT
M24D816512DA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 13/13
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this document without notice.
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property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
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but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
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application, purchaser must do its own quality assurance testing appropriate
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