TDC1025 Vi vy Monolithic A/D Converter Features 8-Bit, 50Msps 8-Bit Resolution ; e 50Msps Conversion Rate The TRW TDC1025 is a 50Msps (MegaSampie Per * Sample-And-Hold Circuit Not Required Second) full-parallel (flash) analog-to-digital converter, : : ; Cm capable of converting an analog signal with full-power Differential Or Single-Ended ECL Compatible frequency components up to 12MHz into 8-bit digital e Single 5.2V Power Supply words. A sample-and-hold circuit is not necessary. All digital inputs and outputs are ECL compatible. Available In 68 Contact Or Leaded Chip Carrier Applications The T0C1025 consists of 255 latching comparators, . 6 ng t Medical Electronics combining logic, and an output register. A differential ECL convert signal controls the conversion operation. The Fluid Flow Analysis digital outputs will interface with differential or single- Seismic Analysis ended ECL. The device requires a single 5.2V power Radar/Sonar supply. Transient Analysis High-Speed Image Processing Functional Block Diagram conv >. cow > . > %y fr A Ris % R a 1 $+! inne R 2 a as : . x * * 255 108 ENCODER aren 17 6 Ry [7 > ot Ru 1-8 Rio hy 3 a { Dr) 1 < . . 4 : : . , j 255 | X fa *F DIFFERENTIAL gs >____~] ) COMPARATORS %g >____} A 2 51 TRW LSI Products Inc. Phone: {619} 457-1000 TRW Inc. 1990 PQ. Box 2472 FAX: (619) 455-6314 40601330 Rev. F11/90 La Jolla, CA 92038 Printed in the U.S.A.TDC1025 71trw Functional Block Diagram cory > _ cow >__] Vin ag wae Pts ANA A as pn 3 : ~ a A Re JN > - Bg as . AY . e e . \ e e e \ A 255 TO 8 3 po ENCODER ware 7 127 16 25 = 3 5, ius we J 1-8 Amu a S J nN g > _ g 3 e ~~ . 1 e eo e A e : pc ose < a "3 LN > g as Ry j DIFFERENTIAL Ras Waa COMPARATORS Rg A> ial Pin Assignments ze g og 322388 23222202 SREGRESRUGRESEESS NC 61 43 NC Rr 42 NC Rts 63 41 Rg Denp 64 4 Res NC 65 33 Deno (mse) 0, 66 38 NC (MSB) D, 67 37 Dg (LSB) D> 8 36 Dg (LSB) D2 1 3% Oy By 2 4 0; Dy 3 33 Og Oy 4 2 0 Dy 5 31 Ds NC 6G 0 Os Veen 7 2 Veep Ogun 8 28 Denn NC 9 27 NC FSreeerteeree 222 582 s2g2 52 3 = > > = ~~ =~ Vera 23 NC 24 NC 25 NC 26 68 Contact Or Leaded Chip Carrier - C1, L1 Package 52 TRW LS! Products Inc.TDC1025 om Functional Description General Information The TDC1025 has three functional sections: a comparator array, encoding logic, and output latches. The comparator array compares the input signal with 255 reference voltages to produce an N-of-255 code (sometimes referred to as a itv: thermometer code, as all the comparators below the signal will be on, and all those above the signa! will be off). The encoding logic converts the N-of-255 code into binary format. The output latch holds the output constant between updates. Power The TDC1025 operates from a single -5.2V power supply. The separate analog and digital power pins, Vegq and Veep, beth require ~5.2V, and may be connected to the same power supply. However, separate decoupling of the analog and digital power pins is recommended (refer to Figure 5 for a typical decoupling circuit). The return for Egg, the current drawn from the Vegp supply, is Dgnp. The return for lega, the current drawn from the Vega supply, is Agnp. The analog and digital ground planes should be separated to minimize ground noise and prevent ground loops, and connected back at the power supply. All power and ground pins must be connected. Name Function Value C1, Li Package Veep Digital Supply Voltage -6.2V Pins 7, 29 VEEA Analog Supply Voltage -.2V Pins 13, 14, 16, 18, 20, 22, 23 Oeno Digital Ground 0.0V Pins 8, 28, 39, 64 Aenp Analog Ground 0.0V Pins 46, 50, 55, 58 Reference The TDC1025 converts analog signals in the range Vag S Vin S Var into digital form. Vap {the voltage applied to the pin at the bottom of the reference resistor chain) and Vat (the voltage applied to the pin at the top of the reference resistor chain) should be between +0.1V and ~2.1V. VaT should be more positive than VaR within that range. The voltage applied across the reference resistor chain (VpT-Vap} must be between 1.8V and 2.2V. The nominal voltages are Vat = O.0V, Vag = -2.0V. Two sense points, Rtg and Ras, may be used to minimize the offset errors and temperature sensitivity. With sensing, resistors Ry and Ro {fas shown in the Functional Block Diagram) are contained within the feedback loop, and no longer contribute to the offset error. The remaining offset errors, Eqs and Eggs, can be eliminated by the calibration method discussed under Calibration. The temperature sensitivity of this remaining offset error is specified by tegs, Temperature Coefficient, Sensed. The sense resistors, Ry and Aq (as shown in the Functional Block Diagram) are approximately 1 kOhm. These resistors are not designed to carry the total reference current, and should not be used as reference inputs. If the sensed points are not used, these pins should be left open. The circuit in Figure 5 shows a typical sensing configuration. TRW LS! Products Inc. A midpoint tap, Ry, allows the converter to be adjusted for optimum linearity, although adjustment is not necessary to meet the linearity specification. lt can also be used to achieve a non-linear transfer function. The circuit shown in Figure 7 will provide approximately 1/2 LSB adjustment of the linearity midpoint. The characteristic impedance at this node is approximately 75 Ohms, and should be driven from a low-impedance source. Note that any load applied to this nade will affect linearity, Noise introduced at this point, as well as the reference inputs and sense ocints may degrade the quantization process, resulting in encoding errors. Due to the variation in the reference currents with clock and input signals, Ry and Rg should be low-impedance -to-ground points. For circuits in which the reference is not varied, a bypass capacitor to ground is recommended. lf the reference inputs are exercised dynamically, (as in an Automatic Gain Control circuit), a low-impedance reference source is required. The reference voltages may be varied dynamically at rates up to 70MHz. 53 QuDC102 TiCLA T 5 artes Reference (Cont.) Name Function Value C1, L1 Package Ry Reference Resistor (Top) O.0V Pin 62 Rts Reference Resistor Sense (Top) Pin 63 Ru Reference Resistor (Middle) -1.0V Pin 49 Rg Reference Resistor (Bottom) -2.0V Pin 41 Res Reference Resistor Sense (Bottom) Pin 40 Convert The TDC1025 requires a differential ECL Convert (CONV) signal. Both convert inputs must be connected, with CONV being the complement of CONV. A sample is taken {the comparators are latched) within 10ns after the rising edge on the CONV pin. This time is ts7g, Sampling Time Offset. This delay may vary from part to part and as a function of temperature, but the short-term uncertainty (jitter) in sampling time offset is less than 50 picoseconds. The 255 to 8 encoding is performed on the falling edge of the CONV signal. The coded output is transferred to the output latches on the next rising edge. Data is held valid at the output register for at least tyo, Output Hold Time, after the rising edge of CONV. New data becomes valid after a Digital Output Delay, tp. This permits the previous conversion result to be acquired by external circuitry on that rising edge, i.e. data for sample N is acquired by the external circuitry while the TDC1025 is taking input sample N + 2. Note that there are minimum pulse width (tpyy, and tpyyy) requirements on the waveshape of the CONV signal. (Refer to Figure 1} Name Function Value C1, L1 Package CONV Convert ECL Pin 54 CONV Convert Complement ECL Pin 53 Analog Input The TDC1025 comparator array causes the input impedance to vary slightly with the signal level, as comparator input transistors are cut-off or become active. For optimal performance, the source impedance driving the device must be less than 25 Ohms. The input signal will not damage the TDC1025 if it remains within the range of +0.5V to Vega. If the input signal is between the Vay and Vpp references, the output will be a binary number between 0 and 255, proportional to the magnitude of the analog input. A signal outside this range will indicate either full-scale positive or full-scale negative, depending on whether the signal is off~scale in the positive or negative direction. All eight analog input pins should be connected through resistors near the chip to provide a balanced analog input to all portions of the comparator array. The optimized values are shown in Figure 6. The analog input bandwidth, specified for a full-power input, is limited by the slew rate capabilities of the internal comparators. Decreasing the analog input amplitude will reduce the slew rate, and thus increase the effective bandwidth. Note that other system performance characteristics are specified for the recommended 2V p-p amplitude, and may degrade with the decreased analog input signal. A sample-and-hold circuit at the analog input will also extend performance beyond the specified bandwidth. Name Function Value C1, L1 Package Vin Analog Signat input OV to -2V Pins 44, 47, 48, 51, 52, 56, 57, 54 TRW LS! Products Inc.TDC1025 vitve Outputs The outputs of the TDC1025 are both differential and single-ended ECL compatible. The outputs should be terminated with a 1.5 kOhm impedance into a -5.2V source to meet the specified logic levels. Using the outputs in a differential mode will provide increased noise immunity. Name Function Value C1, Li Package 0, MSB Output, Complement ECL Pin 66 D, MSB Output ECL Pin 67 D> ECL Pin 68 Dy ECL Pin 1 D3 ECL Pin 2 Dy ECL Pin 3 Dy ECL Pin 4 Dy ECL Pin D5 ECL Pin 30 Ds ECL Pin 31 Og ECL Pin 32 Dg ECL Pin 33 0; ECL Pin 34 0; ECL Pin 35 De LSB Qutput, Complement ECL Pin 36 Dg LSB Qutput ECL Pin 37 No Connects There are several pins labeled No Connect {NC}, which have no connections to the chip. These pins should be left open. Function Value C1, L1 Package NC No Connect Open Pins 6, 9, 10, 11, 12, 15, 17, 19, 21, 24, 25, 26, 27, 3B, 42, 43, 45, 59, 61, 65 Thermal Design The case temperature must be limited to a maximum of 80C for the standard temperature range and 126C for the extended temperature range. For ambient temperatures above TRW LS! Products Inc. 45C, 500 L.F.P.M. moving air is required for specified performance. In addition to moving air, heat sinking is an efficient method to optimize thermal management. 55TDC1025 arte Figure 1. Timing Diagram 1 om - COoNv SAMPLE N ANALOG INPUT tpwH | m| | X__X xX __X__ SAMPLE SAMPLE DIGITAL OUTPUT tuo | Figure 2. Simplified Analog Input Equivalent Circuit | 1 OF 255 | VIN T ? I ' VIN 1-OF-255 C i Rin COMPARATORS N cB | | |pias Vag ! Veea REFERENCE Veen CHAIN Cyy IS A NONLINEAR JUNCTION CAPACITANCE VEEA Vpp IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN R RB B Figure 3. Convert Input Equivalent Circuit Figure 4. Output Circuits > -O GND conv O_J con TT O 56 4 O GND --o Hh DATA OUTPUT DATA OUTPUT COMPLEMENT OUTPUT EQUIVALENT CIRCUIT To = an OUTPUT 40pF = PIN 1.5K LOAD 1 TEST LOAD FOR DELAY MEASUREMENTS Veep (-5.2V) TRW LSI Products Inc.TDC1025 atv? ts ed Figure 5. CONVert, CONVert Switching Levels | 0.0V Te oT oT TT sO vi VipF aN N aN SS oe er Ns Os Oeenreeesee an a . -- CONV N View max ~ -- CONV il Absolute maximum ratings {beyond which the device will be damaged) | a Supply Voltages Veep (measured to Dgqp) +0.5 to -7.0V Vera 1 to Agyp) +0.5 to -7.0V Agnp {measured to Denp} +0.5 to -0.5V Vega {measured to Veep) +0.5 to -0.5V Input Voltages CONV, CONV (measured to Ogyp} +05 to VegpV Vin: Yat: Yrg (measured to Agyp} +05 to Vega Ver d to Vap) 0 to +2.5V Output Short-circuit duration {single output in high state to ground) Indefinite Temperature Operating, ambient ~5 to + 126C junction +176C Lead, soldering (10 seconds) +300C Storage -65 to +150C Note: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. TRW LSI Products Inc. 57TDC1025 arty Operating conditions Temperature Range Standard Extended Parameter Min Nom Max Min Nom Max Units Veep Digital Supply Voltage ~-49 ~62 65 ~49 ~2 -65 V VeEA Analog Supply Voltage -49 ~.2 -5 -49 -.2 -55 Vv Veca-Veep Supply Voltage Differential -O1 0.0 +01 -01 00 +01 V Vacno Analog Ground Voltage {measured to Dgnp) i 0.0 +0.1 -04 60 +01 v tpw CONV Pulse Width, LOW 8 8 ns tpwH CONV Pulse Width, HIGH 12 12 ns View CONV Input Voltage, Common Mode -05 ~25 ~05 -25 V Vipr CONV Input Voltage, Differential 0.3 12 0.3 12 V Vet Most Positive Reference Input | 0.1 0.0 +01 -0.1 0.0 +01 Vv Vp Most Negative Reference Input | ~19 -20 -24 -19 -20 -21 V Vat-Vrp Voltage Reference Ditferential 18 2.0 22 18 2.0 2.2 v Vin Input Voltage Vep Vet Vpp Vet v Ty Ambient Temperature 2 0 70 C Te Case Temperature? 0 100 -55 +125 c Notes: 1. Vpy Must be more positive than Vpp, and voltage reference differential must be within specified range. 2. 600 L.F.P.M. maving air required above 45C ambient. Electrical characteristics within specified operating conditions Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units lee Supply Current Veen Veep = MAX Ta = OC to 70C -18 mA Ta = 70C ~575 mA Tp = ~56C to 126C ~ 1000 mA Tp = 125C - 500 mA Incr Reference Current Vet Yap ~ NOM 10 Ec] 10 45 mA Rrer Total Reference Resistance 57 200 4 200 Ohms Rin Input Equivalent Resistance Vet. Vre - NOM, Viy = Yep 4 4 kOhms Cy Input Capacitance 160 160 pF leg Input Constant Bias Current Veen Veep = MAX, Viy = 0.0V 750 1200 HA i Digital Input Current Veen: Veep = MAX, Vy = -0.7V 160 240 HA Vo_ Output Voltage, Logic LOW Vega. Veep = NOM, Ip, = Test Load! -18 -15 Von Output Voltage, Logic HIGH Veca. Veep = NOM, Igy = Test Load! -095 -11 Vv C Digitat Input Capacitance Ty = 25C, F = IMHz 20 20 pF Note: 1. Test Load = 1.5 kOhms te -5.2V, C = 40pF. 58 TRW LSI Products Inc.TDC1025 aitvy IX Switching characteristics within specified operating conditions x Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units Fg Maximum Conversion Rate Veea Veep = MIN 50 50 MSPS tgtq Sampling Time Offset Veen, Veep ~ MIN 10 10 ns tp _ Digital Output Delay Veea. Veep = MIN, Load ! 20 a ns typ _ Digital Output Hold Time Veea, Veep ~ MIN, Load! 2 2 ns Gu Note: System performance characteristics within specified operating conditions 1. Test load = 1.5 kOhms ta -5.2V, C = 40pF. om Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units Ey Linearity Integral, Independent Vat. Yap - NOM 0.3 0.3 % Etp Linearity Differential 03 0.3 % Qa Code Size Vet Vag = NOM 15 185 5 185 % Nominal Egy _Offset Error Top Vin = Vat +40 +45 mV Egts Offset Error = Top, Sensed +10 +10 mV Egg sOffset Error Bottom Vin - Yee -40 -45 mv Eggs Offset Error Bottom, Sensed +10 +15 mV Teog _Dffset Error Temperature Coefficient, Sensed 80 80 prec BW Bandwidth, Full Power Input 12.5 125 MHz ttR Transient Response, Full Scale Input Change 10 10 ns SNR Signal-to-Noise Ratio 20MHz Bandwidth, SOMSPS Conversion Rate Peak SignalRMS Noise 1.25MHz Input 59 53 dB 5.34MHz Input 51 51 dB 10.0MHz Input 47 dB 12.0MHz Input 47 dB RMS Signal{RMS Noise 1.25MHz input 44 44 dB 5.34MHz Input 42 42 dB 10.0MHz [Input 38 dB 12.0MHz Input 38 dB EAP Aperture Error 40 4 ps TRW LSI Products Inc. 59TDC1025 7 mtvy Figure 6. Typical Interface Schematic BI-B3, B12~B15, B17, B19-B21 Ly) Gno2 pre wy wy we B23, 824 Seno1 o7 &. A 826-832 + cna > Ve 03 1N4001 tw > p CL UZ CA3127E 833 GY + cs 10K #2.2K ba 10 RzB 3 14001 Ta x = y yk 10-TURN OFFSET 1 CONV A ' JS R58 \ D5 * d+ cas CcONY } 330 , 14001 + 10 2v A18,.B18 Vee2 60 TRW LSI Products Inc.TDC1025 Notes for Figure 6 62 = = a3 oS 12. . Values for components C5, R15, R62, R65, R66 are determined during the atv All resistor values are in Ohms. All resistors are 1/8W unless otherwise noted. All capacitor values are in microFarads unless otherwise noted. All capacitors are 50WVDC unless otherwise noted. All diodes are 1N4148 unless otherwise noted. R58 is a quad 220/330 Ohm terminator SIP. Z\ is a digital delay line, 2ns per tap, 20ns total Rhombus TZB12-5. L1 is a ferrite bead inductor, Fair-rite part number 2743001112. AGND pins on the TDC1025L1 are: 46, 50, 55, 58. Deno pins on the TDC1025L1 are: 8, 28, 39, 64. VeEA pins an the TOC1O26L1 are: 13, 14, 16, 18, 20, 22, 23. Veep pins on the TDC1025L1 are: 7, 29. manufacturing process. Component designators C32, R49, R57, R63, R64, J1 are not used on the TDC1025E1C board. . Components R30, R31, R45, R47, R48, R54, R56, R59, R60, R61, J4, are user options and are not included with the board. TRW LS! Products Inc.TDC1025 arty Typical Interface Figure 6 shows an example of a typical interface circuit for the bottom of the resistor chain. Additional gain adjustment the TDC1025. The analog input amplifier is a discrete can be made by varying the input voltage to the sensing differential amplifier followed by an NPN transistor. The opamp. transistor satisfies the input drive requirement of the A/D converter. The analog input resistors, attached close to the Vij The differential clock is provided by an ECL gate, with pins, provide frequency stability and a balanced analog input to termination close to the TDC1025 to minimize ringing or all portions of the comparator array. All eight Vij pins are overshoot. The convert clock is delayed by approximately connected together close to the device package, and the 5-10ns to latch the data at the output. The data outputs are Qu feedback loop should be clased at that point. Bipolar inputs terminated with 1.5 kOhms to ~5.2V. The standard Thevenin may be used by adjusting the offset control. The amplifier has equivalent (220 Ohms~330 Ohms to -5.2V) is used where a gain of two, increasing a 1 Volt p~p input signal to the additional termination is required. recommended 2 Volt p-p input for the A/D. The analog and digital ground planes are separated to minimize The top reference, Ry, is grounded, with the sense point, RTS, ground neise and prevent ground joops, and are connected left open. The offset error introduced at the top of the back at the power supply. The independent ECL digital ground reference chain is cancelled by the offset adjustment. The aids in maintaining the chip digital ground, especially in a bottom reference voltage, Vag is supplied by an amplifier, and system with high-speed ECL logic. Protective diodes between a PNP transistor. The feedback loop through the sense, Rgs, all three ground planes avoid damage due to excessive minimizes the offset error and related temperature variations at differences in ground potential. Figure 7. Power Decoupling and Input Network Figure 8. Typical Reference Midpoint Adjust Circuit Ri a AAA WV Yin Pog Po ag R ANALOG ZS y INPUT f 'N ae: VA Vin TDC1025 TDC1025 AAA L 13,14,16,18, ~ 20,22,23 Agno -52v Veep tinal D 828,28 L_GNO = FERRITE BEAD INDUCTOR Ry = 1082, 1% CARBON COMPOSITION OR CERAMIC CHIP RESISTOR Ry = 1082, 1% CARBON COMPOSITION OR CERAMIC CHIP RESISTOR C = O.1yF CERAMIC DISC CAPACITOR W = ANALOG GROUND -L = DIGITAL GROUND Note: Pins are shown for L1, C1 packages TRW LSI Products Ine. 63TDC1025 #mIXNvy Output Coding Binary Offset Two's Complement Step Range True inverted True Inverted -2.0000V FS ~2.0480V FS All Outputs Dy Do-Dg 7.8431 mV Step 8.000 mV Step Inverted Inverted Inverted 000 0.0000 0.0000 oooc00000 WNIT 100000000 O1t111911 001 -0.0078V ~0.0080V 000000001 111911110 100000001 O111t1110 e e e e e e e e e e e e e e e e e es e e e 127 -0.9961V ~1.0160V ona Jooo00000 110011111 000000000 128 -1,0039V ~1,0240V 100000000 Oni 000000000 WI 129 ~1.0118V -1.0320V ~ 100000001 017111110 000000001 1949111110 e e e e e e e e e . e e e e e e e e e e e 254 -1,9921V -2.0392V 119119110 000000001 O11119110 100000001 255 ~2.0000V ~2.0400V 141911111 00000000 Oni 100000000 Note: 1. Voltages are code midpoints after calibration. 2. Any output may be inverted by interchanging connections to the true (Dy) and complement (Oy! output pins. a a Calibration To calibrate the TOC1025, adjust VAT and Vpp to set the 1st and 265th thresholds to the desired voltages. Note that Ry is greater than R, ensuring calibration with a positive voltage on Ry. Assuming a OV to -2V desired range, continuously strobe the converter with -0.0039V (1/2 LSB from OV) on the analog input, and adjust VT for output toggling between codes 00 and 01. Then apply -1.996V (1/2 LSB from -2V} and adjust Vap for toggling between codes 254 and 256. The degree of required adjustment is indicated by the offset errors, Eqy and Egg. Offset errors are generated by the inherent parasitic resistance between the package pin and the actual resistor chain on the integrated circuit. These parasitic resistors are shown as Rj and Ro in the Functional Black 64 Diagram. Calibration will cancel all offset voltages, eliminating offset and gain errors. The above method of calibration requires that both ends of the resistor chain, Rt and Rp, are driven by buffered operational amplifiers. Instead of adjusting VpT, Ry can be connected to analog ground and the OV end of the range calibrated with a buffer offset control. The offset error at the bottom of the resistor chain results in a slight gain error, which can be compensated for by varying the voltage applied to Rp. The bottom reference is a convenient point for gain adjust that is not in the analog signal path. These techniques are employed in Figure 5. TAW LSI! Products Inc.TDC1025 7itvy | IX Ordering Information Product Temperature Range Screening Package Package Number Marking TDC1025C1C STD-Tp=0C to 80C Commercial 68 Contact Chip Carrier 1025C1C TDC1025C1A EXT-Tc= 55C to 125C High Reliability 68 Contact Chip Carrier 1025C1A TDC1025L1C STD-Te =0C to 80C Commercial 68 Contact Chip Carrier 1025L1C TDC1025L1A EXTTp = 58C to 125C High Reliability 68 Leaded Chip Carrier 1025L1A All parameters contained in this specification are guaranteed by design, characterization, sample testing or 100% testing as appropriate. TRW reserves the right to change products and specifications without notice. This information does not convey any license under patent rights of TRW Inc. or others. Life Support Policy TRW LSI Products inc. components are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably be expected to result in personal injury. The user of TRW LSI Products Inc. components in life support applications assumes all risk of such use and indemnifies TRW LS! Products Inc. against all damages. TRW LSI Products Inc. 65 Gu