512K x 8 Static RA
M
WCFS4008V1
C
S4008V1C
Features
• High speed
—tAA = 12 ns
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE featu res
Functional Description
The WCFS4008V1C is a high-performance CMOS Static RAM
organized as 524K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Ou tput Enabl e (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW . Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE ) and Ou tput Enabl e (OE) LO W while forcing Wr ite
Enable (WE) HIGH. Under these conditions, the contents of
the memo ry l ocatio n spec ified by the add ress pi ns will a ppear
on the I/O pins.
The eight inp ut/o utp ut pin s (I/O0 thro ug h I/ O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or d ur i ng a w rit e
operation (CE LOW, and WE LOW).
The WCFS4008V1C is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and grou nd pin out .
14
15
Logic Block Diagram Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
CE
A
A16
A17
1
2
3
4
5
6
7
8
9
10
11
14 23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15 21
22
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
A
18
A
15
A
12
A
14
I/O
5
I/O
4
A
9
A
0
I/O
0
I/O
1
I/O
2
OE
A
17
A
16
A
13
CE
A9
A18
18
17 19
20
GND
I/O
7
I/O3
I/O
6
V
CC
A
10
A
11
NC
NC
A10
A
6
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15 29
30
V
CC
A
7
A
8
A
9
NC
NC
NC
NC
A
18
V
SS
NC
A
15
A
0
A
3
I/O
0
A
4
CE
A
17
A
12
A
1
A
2
18
17
20
19
I/O
1
27
28
25
26
22
21 23
24
NC
V
SS
WE
I/O
2
I/O
3
A
5
NC
A
16
V
CC
OE
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
13
A
11
A
10
NC
NC
NC
Selection Guide WCFS4008V1C 12ns
Maximum Access Time (ns) 12
Maximum Operating Current (mA) Comm’l 85
Maximum CMOS Standby Current (mA) Comm’l 10
WCFS4008V1
C
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature ................................–65×C to +150×C
Ambient Temperature with
Power Applied............................................–55×C to +125 ×C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage [1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C3.3V ± 0.3V
Electrical Characteristi cs Ov er the Op erating Range
Paramete r Descripti on Test Conditions WCFS400 8V1 C 12ns
Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 µA
IOZ Output Leakage
Current GND < VOUT < VCC,
Output Disabled –1 +1 µA
ICC VCC Operating
Supply Current VCC = Max.,
f = fMAX = 1/tRC Comm’l 85 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Comm’ll 10 mA
Capacitance[2]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 3.3V 8pF
COUT I/O Capacitance 8 pF
Note:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns
2. Tested initially and after any design or process changes that may affect these parameters.
WCFS4008V1
C
3
AC Test Loads and Waveforms
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.3V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE (a)
R1 317Ω
R2
351Ω
OUTPUT 50Ω
Z0=50Ω
VTH = 1.5V
30pF*
(c)
(b)
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
Rise time > 1 V/ns Fall time:
> 1 V/ns
WCFS4008V1
C
4
AC Switching Characteristics[3] Over the Operating Range
WCFS4008V1C 12ns
Parameter Description Min. Max. Unit
READ CYCLE
tpower[4] VCC(typical) to the first access 1 ns
tRC Read Cycle Time 12 ns
tAA Address to Data Valid 12 ns
tOHA Data Hold from Address Change 3 ns
tACE CE LOW to Data Valid 12 ns
tDOE OE LOW to Data Valid 6 ns
tLZOE OE LOW to Low Z 0 ns
tHZOE OE HIGH to High Z[5, 6] 6ns
tLZCE CE LOW to Low Z[6] 3ns
tHZCE CE HIGH to High Z[5, 6] 6ns
tPU CE LOW to Power-Up 0 ns
tPD CE HIGH to Power-Down 12 ns
WRITE CYCLE[7, 8]
tWC Write Cycle T im e 12 ns
tSCE CE LOW to Write End 8 ns
tAW Address Set-Up to Write End 8 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 8 ns
tSD Data Set-Up to Write End 6 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low Z[6] 3ns
tHZWE WE LOW to High Z[5, 6] 6ns
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. tPOWER gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed.
5. tHZOE, tHZCE, and tHZWE are specif ied wi th a load cap acit ance of 5 p F as in part (b) of AC Test Loads . T rans ition is measu red ±500 mV from s teady -state volt age.
6. At any given temperature and voltage condition, tHZCE is le ss t han t LZCE, t HZOE is less than tLZOE, and tHZWE is less tha n tLZWE for any gi ven d evice .
7. The internal write time of the memory is defined by the overlap of CE LOW , a nd WE LOW. CE and WE must be LOW to initiate a writ e, and the transi tion of either of
these sign als can terminat e the write. The input data set-up and hold ti ming should be refer enced to the leading edg e of the signal that ter minates the writ e.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
WCFS4008V1
C
5
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH f or read cycle .
11. Address valid prior to or coincident with CE t ransiti on LOW.
PREVIOUS DATA VALID DATA VALI D
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
WCFS4008V1
C
6
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[12, 13]
Write Cycle No. 2 (WE Controlled, OE LOW)[13]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 14
Truth Table
CE OE WE I/O0 – I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Notes:
12. Data I/O is high-impedance if OE = VIH.
13. If CE goes HIGH simult aneo usly w ith WE go ing H IGH, t he output remains in a h igh-imped ance s tate.
14. During this period the I/Os are in the output state and input signals should not be applied.
WCFS4008V1
C
7
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 WCFS 4008V1C-JC12 J 36-Lead (4 00-Mil) Molded SOJ Commercial
WCFS4008V1C-TC12 T 44-pin TSOP II
Package Diagrams
36-Lead (400-M il) Mol ded SOJ J
WCFS4008V1
C
8
Package Diagrams (continued)
44-Pin TSOP II T
512K x 8 Static RA
M
WCFS4008V1
C
Revision History
Document Title: WCFS4008V1C 32K x 8 3.3V Static RAM
REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE
** 4/12/2002 XFL New Datasheet
