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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 1
Virtex Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
Table 1 correlates the current status of each Virtex device
with a corresponding speed file designation.
All specifications are subject to change without notice.
0
Virtex™ 2.5 V
Field Programmable Gate Arrays
DS003-3 (v2.9) October 29, 2001 03Product Specification
R
Table 1: Virtex Device Speed Grade Designations
Device
Speed Grade Designations
Advance Preliminary Production
XCV50 –6, –5, –4
XCV100 –6, –5, –4
XCV150 –6, –5, –4
XCV200 –6, –5, –4
XCV300 –6, –5, –4
XCV400 –6, –5, –4
XCV600 –6, –5, –4
XCV800 –6, –5, –4
XCV1000 –6, –5, –4
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
2 1-800-255-7778 Product Specification
Virtex DC Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Symbol Description(1) Units
VCCINT Supply voltage relative to GND(2) 0.5 to 3.0 V
VCCO Supply voltage relative to GND(2) 0.5 to 4.0 V
VREF Input Reference Voltage 0.5 to 3.6 V
VIN
Input voltage relative to GND(3) Using VREF 0.5 to 3.6 V
Internal threshold 0.5 to 5.5 V
VTS Voltage applied to 3-state output 0.5 to 5.5 V
VCC Longest Supply Voltage Rise Time from 1V-2.375V 50 ms
TSTG Storage temperature (ambient) 65 to +150
°
C
TJJunction temperature(4) Plastic Packages +125
°
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. Power supplies can turn on in any order.
3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more than 3.6 V.
4. For soldering guidelines and thermal considerations, see the Device Packaging infomation on the Xilinx website.
Symbol Description Min Max Units
VCCINT(1) Input Supply voltage relative to GND, TJ = 0
°
C to +85
°
CCommercial 2.5 5% 2.5 + 5% V
Input Supply voltage relative to GND, TJ = 40
°
C to +100
°
C Industrial 2.5 5% 2.5 + 5% V
VCCO(4) Supply voltage relative to GND, TJ = 0
°
C to +85
°
CCommercial1.43.6V
Supply voltage relative to GND, TJ = 40
°
C to +100
°
C Industrial 1.4 3.6 V
TIN Input signal transition time 250 ns
Notes:
1. Correct operation is guaranteed with a minimum VCCINT of 2.375 V (Nominal VCCINT 5%). Below the minimum value, all delay
parameters increase by 3% for each 50-mV reduction in VCCINT below the specified range.
2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report.
3. Input and output measurement threshold is ~50% of VCC.
4. Min and Max values for VCCO are I/O Standard dependant.
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 3
DC Characteristics Over Recommended Operating Conditions
Symbol Description Device Min Max Units
VDRINT
Data Retention VCCINT Voltage
(below which configuration data can be lost) All 2.0 V
VDRIO
Data Retention VCCO Voltage
(below which configuration data can be lost) All 1.2 V
ICCINTQ Quiescent VCCINT supply current(1,3) XCV50 50 mA
XCV100 50 mA
XCV150 50 mA
XCV200 75 mA
XCV300 75 mA
XCV400 75 mA
XCV600 100 mA
XCV800 100 mA
XCV1000 100 mA
ICCOQ Quiescent VCCO supply current(1) XCV50 2 mA
XCV100 2 mA
XCV150 2 mA
XCV200 2 mA
XCV300 2 mA
XCV400 2 mA
XCV600 2 mA
XCV800 2 mA
XCV1000 2 mA
IREF VREF current per VREF pin All 20
m
A
ILInput or output leakage current All 10 +10
m
A
CIN Input capacitance (sample tested) BGA, PQ, HQ, packages All 8 pF
IRPU Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample
tested) All Note (2) 0.25 mA
IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Note (2) 0.15 mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
3. Multiply ICCINTQ limit by two for industrial grade.
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
4 1-800-255-7778 Product Specification
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device(1) from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal
voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms).
DC Input and Output levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed output currents over the
recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen
to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO for each standard
with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
Product Description(2) Current Requirement(1,3)
Virtex Family, Commercial Grade Minimum required current supply 500 mA
Virtex Family, Industrial Grade Minimum required current supply 2 A
Notes:
1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents can result if ramp rates are forced to be faster.
Input/Output
Standard
VIL VIH VOL VOH IOL IOH
V, min V, max V, min V, max V, Max V, Min mA mA
LVTTL(1) 0.5 0.8 2.0 5.5 0.4 2.4 24 24
LVCMOS2 0.5 .7 1.7 5.5 0.4 1.9 12 12
PCI, 3.3 V 0.5 44% VCCINT 60% VCCINT VCCO + 0.5 10% VCCO 90% VCCO Note (2) Note (2)
PCI, 5.0 V 0.5 0.8 2.0 5.5 0.55 2.4 Note (2) Note (2)
GTL 0.5 VREF 0.05 VREF + 0.05 3.6 0.4 n/a 40 n/a
GTL+ 0.5 VREF 0.1 VREF + 0.1 3.6 0.6 n/a 36 n/a
HSTL I 0.5 VREF 0.1 VREF + 0.1 3.6 0.4 VCCO 0.4 8 8
HSTL III 0.5 VREF 0.1 VREF + 0.1 3.6 0.4 VCCO 0.4 24 8
HSTL IV 0.5 VREF 0.1 VREF + 0.1 3.6 0.4 VCCO 0.4 48 8
SSTL3 I 0.5 VREF 0.2 VREF + 0.2 3.6 VREF 0.6 VREF + 0.6 8 8
SSTL3 II 0.5 VREF 0.2 VREF + 0.2 3.6 VREF 0.8 VREF + 0.8 16 16
SSTL2 I 0.5 VREF 0.2 VREF + 0.2 3.6 VREF 0.61 VREF + 0.61 7.6 7.6
SSTL2 II 0.5 VREF 0.2 VREF + 0.2 3.6 VREF 0.80 VREF + 0.80 15.2 15.2
CTT 0.5 VREF 0.2 VREF + 0.2 3.6 VREF 0.4 VREF + 0.4 8 8
AGP 0.5 VREF 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note (2) Note (2)
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 5
Virtex Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation net list.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in , page 6.
Description Device Symbol
Speed Grade
UnitsMin -6 -5 -4
Propagation Delays
Pad to I output, no delay All TIOPI 0.39 0.8 0.9 1.0 ns, max
Pad to I output, with delay XCV50 TIOPID 0.8 1.5 1.7 1.9 ns, max
XCV100 0.8 1.5 1.7 1.9 ns, max
XCV150 0.8 1.5 1.7 1.9 ns, max
XCV200 0.8 1.5 1.7 1.9 ns, max
XCV300 0.8 1.5 1.7 1.9 ns, max
XCV400 0.9 1.8 2.0 2.3 ns, max
XCV600 0.9 1.8 2.0 2.3 ns, max
XCV800 1.1 2.1 2.4 2.7 ns, max
XCV1000 1.1 2.1 2.4 2.7 ns, max
Pad to output IQ via transparent
latch, no delay
All TIOPLI 0.8 1.6 1.8 2.0 ns, max
Pad to output IQ via transparent
latch, with delay
XCV50 TIOPLID 1.9 3.7 4.2 4.8 ns, max
XCV100 1.9 3.7 4.2 4.8 ns, max
XCV150 2.0 3.9 4.3 4.9 ns, max
XCV200 2.0 4.0 4.4 5.1 ns, max
XCV300 2.0 4.0 4.4 5.1 ns, max
XCV400 2.1 4.1 4.6 5.3 ns, max
XCV600 2.1 4.2 4.7 5.4 ns, max
XCV800 2.2 4.4 4.9 5.6 ns, max
XCV1000 2.3 4.5 5.1 5.8 ns, max
Sequential Delays
Clock CLK to output IQ All TIOCKIQ 0.2 0.7 0.7 0.8 ns, max
Setup and Hold Times with respect to Clock CLK at IOB input
register(1) Setup Time / Hold Time
Pad, no delay All TIOPICK/TIOICKP 0.8 / 0 1.6 / 0 1.8 / 0 2.0 / 0 ns, min
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Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
6 1-800-255-7778 Product Specification
IOB Input Switching Characteristics Standard Adjustments
Pad, with delay XCV50 TIOPICKD/TIOICKPD 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min
XCV100 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min
XCV150 1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min
XCV200 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV300 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV400 2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min
XCV600 2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min
XCV800 2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min
XCV1000 2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min
ICE input All TIOICECK/TIOCKICE 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max
Set/Reset Delays
SR input (IFF, synchronous) All TIOSRCKI 0.49 1.0 1.1 1.3 ns, max
SR input to IQ (asynchronous) All TIOSRIQ 0.70 1.4 1.6 1.8 ns, max
GSR to output IQ All TGSRQ 4.9 9.7 10.9 12.5 ns, max
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Description Device Symbol
Speed Grade
UnitsMin -6 -5 -4
Description Symbol Standard(1)
Speed Grade
UnitsMin-6-5-4
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
TILVTTL LVTTL 0 0 0 0 ns
TILVCMOS2 LVCMOS2 0.02 0.04 0.04 0.05 ns
TIPCI33_3 PCI, 33 MHz, 3.3 V 0.05 0.11 0.12 0.14 ns
TIPCI33_5 PCI, 33 MHz, 5.0 V 0.13 0.25 0.28 0.33 ns
TIPCI66_3 PCI, 66 MHz, 3.3 V 0.05 0.11 0.12 0.14 ns
TIGTL GTL 0.100.200.230.26 ns
TIGTLP GTL+ 0.06 0.11 0.12 0.14 ns
TIHSTL HSTL 0.02 0.03 0.03 0.04 ns
TISSTL2 SSTL2 0.04 0.08 0.09 0.10 ns
TISSTL3 SSTL3 0.02 0.04 0.05 0.06 ns
TICTT CTT 0.010.020.020.02 ns
TIAGP AGP 0.03 0.06 0.07 0.08 ns
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 7
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8.
Description Symbol
Speed Grade
UnitsMin-6-5-4
Propagation Delays
O input to Pad TIOOP 1.2 2.9 3.2 3.5 ns, max
O input to Pad via transparent latch TIOOLP 1.4 3.4 3.7 4.0 ns, max
3-State Delays
T input to Pad high-impedance(1) TIOTHZ 1.0 2.0 2.2 2.4 ns, max
T input to valid data on Pad TIOTON 1.4 3.1 3.3 3.7 ns, max
T input to Pad high-impedance via
transparent latch(1) TIOTLPHZ 1.2 2.4 2.6 3.0 ns, max
T input to valid data on Pad via
transparent latch TIOTLPON 1.6 3.5 3.8 4.2 ns, max
GTS to Pad high impedance(1) TGTS 2.5 4.9 5.5 6.3 ns, max
Sequential Delays
Clock CLK to Pad delay with OBUFT
enabled (non-3-state) TIOCKP 1.0 2.9 3.2 3.5 ns, max
Clock CLK to Pad high-impedance
(synchronous)(1) TIOCKHZ 1.1 2.3 2.5 2.9 ns, max
Clock CLK to valid data on Pad delay, plus
enable delay for OBUFT TIOCKON 1.5 3.4 3.7 4.1 ns, max
Setup and Hold Times before/after Clock CLK(2) Setup Time / Hold Time
O input TIOOCK/TIOCKO 0.51 / 0 1.1 / 0 1.2 / 0 1.3 / 0 ns, min
OCE input TIOOCECK/TIOCKOCE 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
SR input (OFF) TIOSRCKO/TIOCKOSR 0.52 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min
3-State Setup Times, T input TIOTCK/TIOCKT 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
3-State Setup Times, TCE input TIOTCECK/TIOCKTCE 0.41 / 0 0.9 / 0 0.9 / 0 1.1 / 0 ns, min
3-State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR 0.49 / 0 1.0 / 0 1.1 / 0 1.3 / 0 ns, min
Set/Reset Delays
SR input to Pad (asynchronous) TIOSRP 1.6 3.8 4.1 4.6 ns, max
SR input to Pad high-impedance
(asynchronous)(1) TIOSRHZ 1.6 3.1 3.4 3.9 ns, max
SR input to valid data on Pad
(asynchronous) TIOSRON 2.0 4.2 4.6 5.1 ns, max
GSR to Pad TIOGSRQ 4.9 9.7 10.9 12.5 ns, max
Notes:
1. 3-state turn-off delays should not be adjusted.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
8 1-800-255-7778 Product Specification
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Description Symbol Standard(1)
Speed Grade Unit
sMin-6-5-4
Output Delay Adjustments
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive load,
Csl)
TOLVTTL_S2 LVTTL, Slow, 2 mA 4.2 14.7 15.8 17.0 ns
TOLVTTL_S4 4 mA 2.5 7.5 8.0 8.6 ns
TOLVTTL_S6 6 mA 1.8 4.8 5.1 5.6 ns
TOLVTTL_S8 8 mA 1.2 3.0 3.3 3.5 ns
TOLVTTL_S12 12 mA 1.0 1.9 2.1 2.2 ns
TOLVTTL_S16 16 mA 0.9 1.7 1.9 2.0 ns
TOLVTTL_S24 24 mA 0.8 1.3 1.4 1.6 ns
TOLVTTL_F2 LVTTL, Fast, 2mA 1.9 13.1 14.0 15.1 ns
TOLVTTL_F4 4 mA 0.7 5.3 5.7 6.1 ns
TOLVTTL_F6 6 mA 0.2 3.1 3.3 3.6 ns
TOLVTTL_F8 8 mA 0.1 1.0 1.1 1.2 ns
TOLVTTL_F12 12 mA 0 0 0 0 ns
TOLVTTL_F16 16 mA 0.10 0.05 0.05 0.05 ns
TOLVTTL_F24 24 mA 0.10 0.20 0.21 0.23 ns
TOLVCMOS2 LVCMOS2 0.10 0.10 0.11 0.12 ns
TOPCI33_3 PCI, 33 MHz, 3.3 V 0.50 2.3 2.5 2.7 ns
TOPCI33_5 PCI, 33 MHz, 5.0 V 0.40 2.8 3.0 3.3 ns
TOPCI66_3 PCI, 66 MHz, 3.3 V 0.10 0.40 0.42 0.46 ns
TOGTL GTL 0.6 0.50 0.54 0.6 ns
TOGTLP GTL+ 0.7 0.8 0.9 1.0 ns
TOHSTL_I HSTL I 0.10 0.50 0.53 0.5 ns
TOHSTL_III HSTL III 0.10 0.9 0.9 1.0 ns
TOHSTL_IV HSTL IV 0.20 1.0 1.0 1.1 ns
TOSSTL2_I SSTL2 I 0.10 0.50 0.53 0.5 ns
TOSSLT2_II SSTL2 II 0.20 0.9 0.9 1.0 ns
TOSSTL3_I SSTL3 I 0.20 0.50 0.53 0.5 ns
TOSSTL3_II SSTL3 II 0.30 1.0 1.0 1.1 ns
TOCTT CTT 0 0.6 0.6 0.6 ns
TOAGP AGP 0 0.9 0.9 1.0 ns
Notes:
1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see
Table 2 and Tabl e 3 .
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Product Specification 1-800-255-7778 9
Calculation of Tioop as a Function of
Capacitance
Tioop is the propagation delay from the O Input of the IOB to
the pad. The values for Tioop were based on the standard
capacitive load (Csl) for each I/O standard as listed in
Table 2.
For other capacitive loads, use the formulas below to calcu-
late the corresponding Tioop.
Tioop = Tioop + Topadjust + (Cload Csl) * fl
Where:
Topadjust is reported above in the Output Delay
Adjustment section.
Cload is the capacitive load for the design.
Table 2: Constants for Calculating Tioop
Standard
Csl
(pF)
fl
(ns/pF)
LVTTL Fast Slew Rate, 2mA drive 35 0.41
LVTTL Fast Slew Rate, 4mA drive 35 0.20
LVTTL Fast Slew Rate, 6mA drive 35 0.13
LVTTL Fast Slew Rate, 8mA drive 35 0.079
LVTTL Fast Slew Rate, 12mA drive 35 0.044
LVTTL Fast Slew Rate, 16mA drive 35 0.043
LVTTL Fast Slew Rate, 24mA drive 35 0.033
LVTTL Slow Slew Rate, 2mA drive 35 0.41
LVTTL Slow Slew Rate, 4mA drive 35 0.20
LVTTL Slow Slew Rate, 6mA drive 35 0.100
LVTTL Slow Slew Rate, 8mA drive 35 0.086
LVTTL Slow Slew Rate, 12mA drive 35 0.058
LVTTL Slow Slew Rate, 16mA drive 35 0.050
LVTTL Slow Slew Rate, 24mA drive 35 0.048
LVCMOS2 35 0.041
PCI 33MHz 5V 50 0.050
PCI 33MHZ 3.3 V 10 0.050
PCI 66 MHz 3.3 V 10 0.033
GTL 0 0.014
GTL+ 0 0.017
HSTL Class I 20 0.022
HSTL Class III 20 0.016
HSTL Class IV 20 0.014
SSTL2 Class I 30 0.028
SSTL2 Class II 30 0.016
SSTL3 Class I 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See Xilinx Application Note XAPP133
for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Table 3: Delay Measurement Methodology
Standard VL(1) VH(1) Meas.
Point
VREF
Typ(2)
LVTTL 0 3 1.4 -
LVCMO S2 0 2.5 1.125 -
PCI33_5 Per PCI Spec -
PCI33_3 Per PCI Spec -
PCI66_3 Per PCI Spec -
GTL VREF 0.2 VREF +0.2 VREF 0.80
GTL+ VREF 0.2 VREF +0.2 VREF 1.0
HSTL Class I VREF 0.5 VREF +0.5 VREF 0.75
HSTL Class III VREF 0.5 VREF +0.5 VREF 0.90
HSTL Class IV VREF 0.5 VREF +0.5 VREF 0.90
SSTL3 I & II VREF 1.0 VREF +1.0 VREF 1.5
SSTL2 I & II VREF 0.75 VREF +0.75 VREF 1.25
CTT VREF 0.2 VREF +0.2 VREF 1.5
AGP VREF
(0.2xVCCO)
VREF +
(0.2xVCCO)
VREF Per
AGP
Spec
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and
Minimum. Worst-case values are reported.
3. I/O parameter measurements are made with the capacitance
values shown in Table 2 . See Xilinx Application Note
XAPP133 for appropriate terminations.
4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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10 1-800-255-7778 Product Specification
Clock Distribution Guidelines
Clock Distribution Switching Characteristics
Description
Device Symbol
Speed Grade
Units-6 -5 -4
Global Clock Skew(1)
Global Clock Skew between IOB Flip-flops XCV50 TGSKEWIOB 0.10 0.12 0.14 ns, max
XCV100 0.12 0.13 0.15 ns, max
XCV150 0.12 0.13 0.15 ns, max
XCV200 0.13 0.14 0.16 ns, max
XCV300 0.14 0.16 0.18 ns, max
XCV400 0.13 0.13 0.14 ns, max
XCV600 0.14 0.15 0.17 ns, max
XCV800 0.16 0.17 0.20 ns, max
XCV1000 0.20 0.23 0.25 ns, max
Notes:
1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case
conditions. Precise values for a particular design are provided by the timing analyzer.
Description Symbol
Speed Grade
UnitsMin -6 -5 -4
GCLK IOB and Buffer
Global Clock PAD to output. TGPIO 0.33 0.7 0.8 0.9 ns, max
Global Clock Buffer I input to O output TGIO 0.34 0.7 0.8 0.9 ns, max
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 11
I/O Standard Global Clock Input Adjustments
Description Symbol Standard(1)
Speed Grade
UnitsMin -6 -5 -4
Data Input Delay Adjustments
Standard-specific global clock input
delay adjustments
TGPLVTTL LVTTL 0 0 0 0 ns,
max
TGPLVCMOS
2
LVCMOS2 0.02 0.04 0.04 0.05 ns,
max
TGPPCI33_3 PCI, 33 MHz, 3.3
V
0.05 0.11 0.12 0.14 ns,
max
TGPPCI33_5 PCI, 33 MHz, 5.0
V
0.13 0.25 0.28 0.33 ns,
max
TGPPCI66_3 PCI, 66 MHz, 3.3
V
0.05 0.11 0.12 0.14 ns,
max
TGPGTL GTL 0.7 0.8 0.9 0.9 ns,
max
TGPGTLP GTL+ 0.7 0.8 0.8 0.8 ns,
max
TGPHSTL HSTL 0.7 0.7 0.7 0.7 ns,
max
TGPSSTL2 SSTL2 0.6 0.52 0.51 0.50 ns,
max
TGPSSTL3 SSTL3 0.6 0.6 0.55 0.54 ns,
max
TGPCTT CTT 0.7 0.7 0.7 0.7 ns,
max
TGPAGP AGP 0.6 0.54 0.53 0.52 ns,
max
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Ta bl e 3 .
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
12 1-800-255-7778 Product Specification
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Description Symbol
Speed Grade
UnitsMin -6 -5 -4
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs TILO 0.29 0.6 0.7 0.8 ns, max
5-input function: F/G inputs to F5 output TIF5 0.32 0.7 0.8 0.9 ns, max
5-input function: F/G inputs to X output TIF5X 0.36 0.8 0.8 1.0 ns, max
6-input function: F/G inputs to Y output via F6 MUX TIF6Y 0.44 0.9 1.0 1.2 ns, max
6-input function: F5IN input to Y output TF5INY 0.17 0.32 0.36 0.42 ns, max
Incremental delay routing through transparent latch
to XQ/YQ outputs
TIFNCTL 0.31 0.7 0.7 0.8 ns, max
BY input to YB output TBYYB 0.27 0.53 0.6 0.7 ns, max
Sequential Delays
FF Clock CLK to XQ/YQ outputs TCKO 0.54 1.1 1.2 1.4 ns, max
Latch Clock CLK to XQ/YQ outputs TCKLO 0.6 1.2 1.4 1.6 ns, max
Setup and Hold Times before/after Clock CLK(1) Setup Time / Hold Time
4-input function: F/G Inputs TICK/TCKI 0.6 / 0 1.2 / 0 1.4 / 0 1.5 / 0 ns, min
5-input function: F/G inputs TIF5CK/TCKIF5 0.7 / 0 1.3 / 0 1.5 / 0 1.7 / 0 ns, min
6-input function: F5IN input TF5INCK/TCKF5IN 0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min
6-input function: F/G inputs via F6 MUX TIF6CK/TCKIF6 0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min
BX/BY inputs TDICK/TCKDI 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min
CE input TCECK/TCKCE 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
SR/BY inputs (synchronous) TRCKTCKR 0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
Clock CLK
Minimum Pulse Width, High TCH 0.8 1.5 1.7 2.0 ns, min
Minimum Pulse Width, Low TCL 0.8 1.5 1.7 2.0 ns, min
Set/Reset
Minimum Pulse Width, SR/BY inputs TRPW 1.3 2.5 2.8 3.3 ns, min
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
TRQ 0.54 1.1 1.3 1.4 ns, max
Delay from GSR to XQ/YQ outputs TIOGSRQ 4.9 9.7 10.9 12.5 ns, max
Toggle Frequency (MHz) (for export control) FTOG (MHz) 625 333 294 250 MHz
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
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R
DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 13
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Description Symbol
Speed Grade
UnitsMin -6 -5 -4
Combinatorial Delays
F operand inputs to X via XOR TOPX 0.37 0.8 0.9 1.0 ns, max
F operand input to XB output TOPXB 0.54 1.1 1.3 1.4 ns, max
F operand input to Y via XOR TOPY 0.8 1.5 1.7 2.0 ns, max
F operand input to YB output TOPYB 0.8 1.5 1.7 2.0 ns, max
F operand input to COUT output TOPCYF 0.6 1.2 1.3 1.5 ns, max
G operand inputs to Y via XOR TOPGY 0.46 1.0 1.1 1.2 ns, max
G operand input to YB output TOPGYB 0.8 1.6 1.8 2.1 ns, max
G operand input to COUT output TOPCYG 0.7 1.3 1.4 1.6 ns, max
BX initialization input to COUT TBXCY 0.41 0.9 1.0 1.1 ns, max
CIN input to X output via XOR TCINX 0.21 0.41 0.46 0.53 ns, max
CIN input to XB TCINXB 0.02 0.04 0.05 0.06 ns, max
CIN input to Y via XOR TCINY 0.23 0.46 0.52 0.6 ns, max
CIN input to YB TCINYB 0.23 0.45 0.51 0.6 ns, max
CIN input to COUT output TBYP 0.05 0.09 0.10 0.11 ns, max
Multiplier Operation
F1/2 operand inputs to XB output via AND TFANDXB 0.18 0.36 0.40 0.46 ns, max
F1/2 operand inputs to YB output via AND TFANDYB 0.40 0.8 0.9 1.1 ns, max
F1/2 operand inputs to COUT output via AND TFANDCY 0.22 0.43 0.48 0.6 ns, max
G1/2 operand inputs to YB output via AND TGANDYB 0.25 0.50 0.6 0.7 ns, max
G1/2 operand inputs to COUT output via AND TGANDCY 0.07 0.13 0.15 0.17 ns, max
Setup and Hold Times before/after Clock CLK(1) Setup Time / Hold Time
CIN input to FFX TCCKX/TCKCX 0.50 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min
CIN input to FFY TCCKY/TCKCY 0.53 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
14 1-800-255-7778 Product Specification
CLB SelectRAM Switching Characteristics
Description Symbol
Speed Grade
UnitsMin -6 -5 -4
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode TSHCKO16 1.2 2.3 2.6 3.0 ns, max
Clock CLK to X/Y outputs (WE active) 32 x 1 mode TSHCKO32 1.2 2.7 3.1 3.5 ns, max
Shift-Register Mode
Clock CLK to X/Y outputs TREG 1.2 3.7 4.1 4.7 ns, max
Setup and Hold Times before/after Clock CLK(1) Setup Time / Hold Time
F/G address inputs TAS/TAH 0.25 / 0 0.5 / 0 0.6 / 0 0.7 / 0 ns, min
BX/BY data inputs (DIN) TDS/TDH 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
CE input (WE) TWS/TWH 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
Shift-Register Mode
BX/BY data inputs (DIN) TSHDICK 0.34 0.7 0.8 0.9 ns, min
CE input (WS) TSHCECK 0.38 0.8 0.9 1.0 ns, min
Clock CLK
Minimum Pulse Width, High TWPH 1.2 2.4 2.7 3.1 ns, min
Minimum Pulse Width, Low TWPL 1.2 2.4 2.7 3.1 ns, min
Minimum clock period to meet address write cycle
time
TWC 2.4 4.8 5.4 6.2 ns, min
Shift-Register Mode
Minimum Pulse Width, High TSRPH 1.2 2.4 2.7 3.1 ns, min
Minimum Pulse Width, Low TSRPL 1.2 2.4 2.7 3.1 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 15
Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Description Symbol
Speed Grade
UnitsMin-6-5-4
Sequential Delays
Clock CLK to DOUT output TBCKO 1.7 3.4 3.8 4.3 ns, max
Setup and Hold Times before/after Clock CLK(1) Setup Time / Hold Time
ADDR inputs TBACK/TBCKA 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min
DIN inputs TBDCK/TBCKD 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min
EN input TBECK/TBCKE 1.3 / 0 2.6 / 0 3.0 / 0 3.4 / 0 ns, min
RST input TBRCK/TBCKR 1.3 / 0 2.5 / 0 2.7 / 0 3.2 / 0 ns, min
WEN input TBWCK/TBCKW 1.2 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min
Clock CLK
Minimum Pulse Width, High TBPWH 0.8 1.5 1.7 2.0 ns, min
Minimum Pulse Width, Low TBPWL 0.8 1.5 1.7 2.0 ns, min
CLKA -> CLKB setup time for different ports TBCCS 3.0 3.5 4.0 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Description Symbol
Speed Grade
UnitsMin -6 -5 -4
Combinatorial Delays
IN input to OUT output TIO 0000ns, max
TRI input to OUT output high-impedance TOFF 0.05 0.09 0.10 0.11 ns, max
TRI input to valid data on OUT output TON 0.05 0.09 0.10 0.11 ns, max
Description Symbol
Speed Grade
Units-6 -5 -4
TMS and TDI Setup times before TCK TTAPTCK 4.0 4.0 4.0 ns, min
TMS and TDI Hold times after TCK TTCKTAP 2.0 2.0 2.0 ns, min
Output delay from clock TCK to output TDO TTCKTDO 11.0 11.0 11.0 ns, max
Maximum TCK clock frequency FTCK 33 33 33 MHz, max
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
16 1-800-255-7778 Product Specification
Virtex Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Description Symbol Device
Speed Grade
UnitsMin -6 -5 -4
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.
For data output with different standards, adjust
delays with the values shown in Output Delay
Adjustments.
TICKOFDLL XCV50 1.0 3.1 3.3 3.6 ns, max
XCV100 1.0 3.1 3.3 3.6 ns, max
XCV150 1.0 3.1 3.3 3.6 ns, max
XCV200 1.0 3.1 3.3 3.6 ns, max
XCV300 1.0 3.1 3.3 3.6 ns, max
XCV400 1.0 3.1 3.3 3.6 ns, max
XCV600 1.0 3.1 3.3 3.6 ns, max
XCV800 1.0 3.1 3.3 3.6 ns, max
XCV1000 1.0 3.1 3.3 3.6 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.
Description Symbol Device
Speed Grade
UnitsMin -6 -5 -4
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.
For data output with different standards, adjust
delays with the values shown in Input and Output
Delay Adjustments.
For I/O standards requiring VREF
, such as GTL,
GTL+, SSTL, HSTL, CTT, and AGO, an additional
600 ps must be added.
TICKOF XCV50 1.5 4.6 5.1 5.7 ns, max
XCV100 1.5 4.6 5.1 5.7 ns, max
XCV150 1.5 4.7 5.2 5.8 ns, max
XCV200 1.5 4.7 5.2 5.8 ns, max
XCV300 1.5 4.7 5.2 5.9 ns, max
XCV400 1.5 4.8 5.3 6.0 ns, max
XCV600 1.6 4.9 5.4 6.0 ns, max
XCV800 1.6 4.9 5.5 6.2 ns, max
XCV1000 1.7 5.0 5.6 6.3 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 17
Minimum Clock-to-Out for Virtex Devices
I/O Standard
With DLL Without DLL
All Devices V50 V100 V150 V200 V300 V400 V600 V800 V1000 Units
*LVTTL_S2 5.2 6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1 6.1 ns
*LVTTL_S4 3.5 4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4 4.4 ns
*LVTTL_S6 2.8 3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7 3.7 ns
*LVTTL_S8 2.2 3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2 3.2 ns
*LVTTL_S12 2.0 2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0 3.0 ns
*LVTTL_S16 1.9 2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9 2.9 ns
*LVTTL_S24 1.8 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7 2.8 ns
*LVTTL_F2 2.9 3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9 3.9 ns
*LVTTL_F4 1.7 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 ns
*LVTTL_F6 1.2 2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1 2.2 ns
*LVTTL_F8 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns
*LVTTL_F12 1.0 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 ns
*LVTTL_F16 0.9 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 1.9 ns
*LVTTL_F24 0.9 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.9 ns
LVCMOS2 1.1 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 ns
PCI33_3 1.5 2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5 2.5 ns
PCI33_5 1.4 2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3 2.4 ns
PCI66_3 1.1 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 2.1 ns
GTL 1.6 2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6 2.6 ns
GTL+ 1.7 2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6 2.7 ns
HSTL I 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns
HSTL III 0.9 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 ns
HSTL IV 0.8 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 1.8 ns
SSTL2 I 0.9 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 ns
SSTL2 II 0.8 1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 ns
SSTL3 I 0.8 1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8 ns
SSTL3 II 0.7 1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.7 ns
CTT 1.0 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 2.0 ns
AGP 1.0 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 2.0 ns
*S = Slow Slew Rate, F = Fast Slew Rate
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive
load is used.
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
18 1-800-255-7778 Product Specification
Virtex Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Description Symbol Device
Speed Grade
UnitsMin -6 -5 -4
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
No Delay
Global Clock and IFF, with DLL
TPSDLL/TPHDLL XCV50 0.40 / 0.4 1.7 /0.4 1.8 /0.4 2.1 /0.4 ns,
min
XCV100 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV150 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV200 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV300 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV400 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV600 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV800 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
XCV1000 0.40 /0.4 1.7 /0.4 1.9 /0.4 2.1 /0.4 ns,
min
IFF = Input Flip-Flop or Latch
Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. DLL output jitter is already included in the timing calculation.
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Virtex 2.5 V Field Programmable Gate Arrays
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DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 19
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Description Symbol Device
Speed Grade
UnitsMin -6 -5 -4
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard.(2) For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
Full Delay
Global Clock and IFF, without
DLL
TPSFD/TPHFD XCV50 0.6 / 0 2.3 / 0 2.6 / 0 2.9 / 0 ns,
min
XCV100 0.6 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns,
min
XCV150 0.6 / 0 2.4 / 0 2.7 / 0 3.1 / 0 ns,
min
XCV200 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns,
min
XCV300 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns,
min
XCV400 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns,
min
XCV600 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns,
min
XCV800 0.7 / 0 2.7 / 0 3.1 / 0 3.5 / 0 ns,
min
XCV1000 0.7 / 0 2.8 / 0 3.1 / 0 3.6 / 0 ns,
min
IFF = Input Flip-Flop or Latch
Notes: Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
20 1-800-255-7778 Product Specification
DLL Timing Parameters
Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent
functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are
derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended
operating conditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
Description Symbol
Speed Grade
Units
-6 -5 -4
Min Max Min Max Min Max
Input Clock Frequency (CLKDLLHF) FCLKINHF 60 200 60 180 60 180 MHz
Input Clock Frequency (CLKDLL) FCLKINLF 25 100 25 90 25 90 MHz
Input Clock Pulse Width (CLKDLLHF) TDLLPWHF 2.0 - 2.4 - 2.4 - ns
Input Clock Pulse Width (CLKDLL) TDLLPWLF 2.5 - 3.0 3.0 - ns
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).
Description Symbol FCLKIN
CLKDLLHF CLKDLL
UnitsMin Max Min Max
Input Clock Period Tolerance TIPTOL - 1.0 - 1.0 ns
Input Clock Jitter Tolerance (Cycle to Cycle) TIJITCC -
±
150 -
±
300 ps
Time Required for DLL to Acquire Lock TLOCK > 60 MHz - 20 - 20
m
s
50 - 60 MHz - - - 25
m
s
40 - 50 MHz - - - 50
m
s
30 - 40 MHz - - - 90
m
s
25 - 30 MHz - - - 120
m
s
Output Jitter (cycle-to-cycle) for any DLL Clock Output(1) TOJITCC
±
60
±
60 ps
Phase Offset between CLKIN and CLKO(2) TPHIO
±
100
±
100 ps
Phase Offset between Clock Outputs on the DLL(3) TPHOO
±
140
±
140 ps
Maximum Phase Difference between CLKIN and
CLKO(4) TPHIOM
±
160
±
160 ps
Maximum Phase Difference between Clock Outputs on
the DLL(5) TPHOOM
±
200
±
200 ps
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v2.9) October 29, 2001 www.xilinx.com Module 3 of 4
Product Specification 1-800-255-7778 21
Figure 1: Frequency Tolerance and Clock Jitter
TCLKIN TCLKIN + T
IPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
_
ds003_20c_110399
Ideal Period
Actual Period
+ Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
Virtex 2.5 V Field Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS003-3 (v2.9) October 29, 2001
22 1-800-255-7778 Product Specification
Revision History
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module 2)
DS003-3, Virtex 2.5V FPGAs:
DC and Switching Characteristics (Module 3)
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module 4)
Date Version Revision
11/98 1.0 Initial Xilinx release.
01/99 1.2 Updated package drawings and specs.
02/99 1.3 Update of package drawings, updated specifications.
05/99 1.4 Addition of package drawings and specifications.
05/99 1.5 Replaced FG 676 & FG680 package drawings.
07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE.
01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status.
05/00 2.2 Modified Table 18.
09/00 2.3 Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under IOB Input Switching Characteristics.
Added values to table under CLB SelectRAM Switching Characteristics.
10/00 2.4 Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
Corrected BG256 Pin Function Diagram.
04/02/01 2.5 Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See the Virtex Data Sheet section.
04/19/01 2.6 Clarified TIOCKP and TIOCKON IOB Output Switching Characteristics descriptors.
07/19/01 2.7 Under Absolute Maximum Ratings, changed (TSOL) to 220
°
C .
07/26/01 2.8 Removed TSOL parameter and added footnote to Absolute Maximum Ratings table.
10/29/01 2.9 Updated the speed grade designations used in data sheets, and added Table 1, which
shows the current speed grade designation for each device.