74VHC112 Dual J-K Flip-Flops with Preset and Clear tm Features General Description High speed: fMAX = 200MHz (Typ.) at VCC = 5.0V Low power dissipation: ICC = 2A (Max.) at TA = 25C The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs Pin and function compatible with 74HC112 The VHC112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Number Package Description 74VHC112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74VHC112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 74VHC112 Dual J-K Flip-Flops with Preset and Clear May 2007 Truth Table Inputs Outputs PR CLR CP J K Q Q L H X X X H L H L X X X L H X L L X X H H H H h h Q0 Q0 H H l h L H H H h l H L Q0 Q0 H H l l H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Pin Description Pin Names Description J1, J2, K1, K2 Data Inputs CLK1, CLK2 Clock Pulse Inputs (Active Falling Edge) CLR1, CLR2 Direct Clear Inputs (Active LOW) PR1, PR2 Direct Preset Inputs (Active LOW) Q1, Q2, Q1, Q2 Outputs Logic Diagram (One Half Shown) (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 2 74VHC112 Dual J-K Flip-Flops with Preset and Clear Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage -0.5V to +7.0V VIN DC Input Voltage -0.5V to +7.0V VOUT DC Output Voltage -0.5V to VCC + 0.5V IIK Input Diode Current -20mA IOK Output Diode Current 20mA IOUT DC Output Current 25mA ICC DC VCC / GND Current TSTG TL 50mA Storage Temperature -65C to +150C Lead Temperature (Soldering, 10 seconds) 260C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr , tf Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C Input Rise and Fall Time, VCC = 3.3V 0.3V 0ns/V 100ns/V VCC = 5.0V 0.5V 0ns/V 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 3 74VHC112 Dual J-K Flip-Flops with Preset and Clear Absolute Maximum Ratings TA = -40C to +85C TA = 25C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0-5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. IOH = -50A 2.0 1.9 2.9 3.0 2.9 4.4 4.5 4.4 IOH = -4mA 2.58 2.48 4.5 IOH = -8mA 3.94 3.80 2.0 VIN = VIH or VIL IOL = 50A 4.5 3.0 4.5 IOL = 8mA V 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA V 0.3 x VCC 1.9 3.0 3.0 Units V 0.50 0.3 x VCC VIN = VIH or VIL Max. 0.7 x VCC 0.50 3.0-5.5 2.0 Max. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 IIN Input Leakage Current 0-5.5 VIN = 5.5V or GND 0.1 1.0 A ICC Quiescent Supply Current 5.5 VIN = VCC or GND 2.0 20.0 A (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 4 74VHC112 Dual J-K Flip-Flops with Preset and Clear DC Electrical Characteristics TA = -40C to +85C TA = 25C Symbol fMAX Parameter Maximum Clock Frequency VCC (V) Conditions Min. Typ. 3.3 0.3 CL = 15pF 110 150 100 CL = 50pF 90 120 80 CL = 15pF 150 200 135 CL = 50pF 120 185 110 5.0 0.5 tPLH, tPHL Propagation Delay Time (CP to Qn or Qn) 3.3 0.3 5.0 0.5 tPLH, tPHL Propagation Delay Time (PR or CLR to Qn or Qn) 3.3 0.3 5.0 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Max. Min. Max. Units MHz MHz CL = 15pF 8.5 11.0 1.0 13.4 CL = 50pF 10.0 15.0 1.0 16.5 CL = 15pF 5.1 7.3 1.0 8.8 CL = 50pF 6.3 10.5 1.0 12.0 CL = 15pF 6.7 10.2 1.0 11.7 CL = 50pF 9.7 13.5 1.0 15.0 CL = 15pF 4.6 6.7 1.0 8.0 CL = 50pF 6.4 9.5 1.0 11.0 4 10 VCC (2) = Open 10 18 ns ns ns ns pF pF Note: 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC / 4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 * n AC Operating Requirements TA = 25C Symbol tW tS tH tREC Parameter VCC (V)(3) Typ. TA = -40C to +85C Guaranteed Minimum Minimum Pulse Width (CP or CLR or PR) 3.3 5.0 5.0 5.0 5.0 5.0 Minimum Setup Time (Jn or Kn to CPn) 3.3 5.0 5.0 5.0 4.0 4.0 Minimum Hold Time (Jn or Kn to CPn) 3.3 1.0 1.0 5.0 1.0 1.0 Minimum Recovery Time (CLR or PR to CP) 3.3 6.0 6.0 5.0 5.0 5.0 Units ns ns ns ns Note: 3. VCC is 3.3 0.3V or 5.0 0.5V. (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 5 74VHC112 Dual J-K Flip-Flops with Preset and Clear AC Electrical Characteristics 74VHC112 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 6 74VHC112 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 7 5.000.10 4.55 5.90 4.45 7.35 0.65 4.40.1 1.45 5.00 0.11 12 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 8 74VHC112 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. (R) ACEx Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM 2 E CMOSTM (R) EcoSPARK EnSignaTM FACT Quiet SeriesTM (R) FACT (R) FAST FASTrTM FPSTM (R) FRFET GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC (R) OPTOPLANAR PACMANTM PDP-SPMTM POPTM (R) Power220 (R) Power247 PowerEdgeTM PowerSaverTM Power-SPMTM (R) PowerTrench Programmable Active DroopTM (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM (R) SPM STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM (R) The Power Franchise TinyBoostTM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM (R) UHC UniFETTM VCXTM WireTM TM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 (c)1995 Fairchild Semiconductor Corporation 74VHC112 Rev. 1.2 www.fairchildsemi.com 9 74VHC112 Dual J-K Flip-Flops with Preset and Clear TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.