Publication Number 21504 Revision EAmendment 7Issue Date August 3, 2009
Am29F800B
Am29F800 B Cover S heet
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
2 Am29F800B 21504_E7 August 3, 2009
Data Sheet
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DATA SHEET
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21504 Rev: EAmendment: 7
Issue Date: August 3, 2009
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F800 device
■High performance
— Access times as fast as 55 ns
■Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Top or bottom boot block configurations
available
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■Minimum 1,000,000 program/erase cycles per
sector guaranteed
■20-year data retention at 125°C
— Reliable operation for the life of the system
■Package option
— 48-pin TSOP
— 44-pin SO
— 48-ball FBGA
— Known Good Die (KGD)
(see publication number 21631)
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
2 Am29F800B 21504E7 August 3, 2009
DATA SHEET
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO, 48-pin
TSOP, and 48-ball FBGA packages. The device is also
available in Known Good Die (KGD) form. For more
information, refer to publication number 21631. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt VCC supply. A 12.0 V VPP is not
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
August 3, 2009 21504E7 Am29F800B 3
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .................... 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F800B Device Bus Operations ..................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Table 2. Am29F800BT Top Boot Block Sector Address Table .......11
Table 3. Am29F800BB Bottom Boot Block Sector Address Table ..12
Autoselect Mode ..................................................................... 12
Table 4. Am29F800B Autoselect Codes (High Voltage Method) ....13
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Hardware Data Protection ...................................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 15
Word/Byte Program Command Sequence ............................. 15
Figure 2. Program Operation .......................................................... 15
Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 16
Figure 3. Erase Operation............................................................... 17
Command Definitions ............................................................. 18
Table 5. Am29F800B Command Definitions ...................................18
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
DQ7: Data# Polling ................................................................. 19
Figure 4. Data# Polling Algorithm ................................................... 19
RY/BY#: Ready/Busy# ........................................................... 20
DQ6: Toggle Bit I .................................................................... 20
DQ2: Toggle Bit II ................................................................... 20
Reading Toggle Bits DQ6/DQ2 .............................................. 20
DQ5: Exceeded Timing Limits ................................................ 21
DQ3: Sector Erase Timer ....................................................... 21
Figure 5. Toggle Bit Algorithm........................................................ 21
Table 6. Write Operation Status ..................................................... 22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23
Figure 6. Maximum Negative Overshoot Waveform ...................... 23
Figure 7. Maximum Positive Overshoot Waveform........................ 23
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
TTL/NMOS Compatible .......................................................... 24
CMOS Compatible .................................................................. 25
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Test Setup....................................................................... 26
Table 7. Test Specifications ........................................................... 26
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Operations .................................................................... 27
Figure 9. Read Operations Timings ............................................... 27
Hardware Reset (RESET#) .................................................... 28
Figure 10. RESET# Timings .......................................................... 28
Word/Byte Configuration (BYTE#) ........................................ 29
Figure 11. BYTE# Timings for Read Operations............................ 29
Figure 12. BYTE# Timings for Write Operations............................ 29
Erase/Program Operations ..................................................... 30
Figure 13. Program Operation Timings.......................................... 31
Figure 14. Chip/Sector Erase Operation Timings .......................... 32
Figure 15. Data# Polling Timings (During Embedded Algorithms). 33
Figure 16. Toggle Bit Timings (During Embedded Algorithms) ...... 33
Figure 17. DQ2 vs. DQ6................................................................. 34
Temporary Sector Unprotect .................................................. 34
Figure 18. Temporary Sector Unprotect Timing Diagram .............. 34
Figure 19. Alternate CE# Controlled Write Operation Timings ...... 36
Erase and Programming Performance . . . . . . . 37
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 37
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
SO 044—44-Pin Small Outline Package ................................ 38
TS 048—48-Pin Standard Pinout Thin Small
Outline Package (TSOP) ........................................................ 39
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
package .................................................................................. 40
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41
4 Am29F800B 21504E7 August 3, 2009
DATA SHEET
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F800B
Speed Option VCC = 5.0 V ± 10% -55 -70 -90 -120
Max access time, ns (tACC)55 70 90 120
Max CE# access time, ns (tCE)55 70 90 120
Max OE# access time, ns (tOE)30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0–DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A18
August 3, 2009 21504E7 Am29F800B 5
DATA SHEET
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for
more information.
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
48-Pin TSOP—Standard Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
6 Am29F800B 21504E7 August 3, 2009
DATA SHEET
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for
more information.
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 V
SS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5NCNCRESET#WE#
DQ11 DQ3DQ10DQ2NCA18NCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# V
SS
CE#A0A1A2A4A3
FBGA
Top View, Balls Facing Down
August 3, 2009 21504E7 Am29F800B 7
DATA SHEET
PIN CONFIGURATION
A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = Device ground
NC = Pin not connected internally
LOGIC SYMBOL
19
16 or 8
DQ0–DQ15
(A-1)
A0–A18
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
8 Am29F800B 21504E7 August 3, 2009
DATA SHEET
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F800B T-70 E C
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
D = Commercial (0°C to +70°C) with Pb-Free Package
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C) with Pb-Free Package
E = Extended (–55°C to +125°C)
K = Extended (–55°C to +125°C) with Pb-Free Package
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
S = 44-Pin Small Outline Package (SO 044)
WB = 48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
This device is also available in Known Good Die (KGD) form. See publication number
21536 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program and Erase
Valid Combinations
AM29F800BT-55,
AM29F800BB-55
EC, EI, EE, ED, EF, EK
SC, SI, SE, SD, SF, SK
AM29F800BT-70,
AM29F800BB-70
AM29F800BT-90,
AM29F800BB-90
AM29F800BT-120,
AM29F800BB-120
Valid Combinations for FBGA Packages
Order Number Package Marking
AM29F800BT-55,
AM29F800BB-55
WBC,
WBI,
WBE,
WBD,
WBF,
WBK
F800BT55V,
F800BB55V
C, I, E,
D, F, K
AM29F800BT-70,
AM29F800BB-70
F800BT70V,
F800BB70V
AM29F800BT-90,
AM29F800BB-90
F800BT90V,
F800BB90V
AM29F800BT-120,
AM29F800BB-120
F800BT12V,
F800BB12V
August 3, 2009 21504E7 Am29F800B 9
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F800B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
Operation CE# OE# WE# RESET# A0–A18 DQ0–DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H AIN DOUT DOUT High-Z
Write L H L H AIN DIN DIN High-Z
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V XHigh-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note) X X X VID AIN DIN DIN X
10 Am29F800B 21504E7 August 3, 2009
DATA SHEET
tions” section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
August 3, 2009 21504E7 Am29F800B 11
DATA SHEET
Table 2. Am29F800BT Top Boot Block Sector Address Table
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” section for more
information.
Sector A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x16)
Address Range
(x8)
Address Range
SA0 0 0 0 0 X X X 64/32 00000h–07FFFh 00000h–0FFFFh
SA1 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh
SA2 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh
SA3 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh
SA4 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh
SA5 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh
SA6 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh
SA7 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh
SA8 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh
SA9 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh
SA10 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
SA11 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA12 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA13 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
SA14 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA15 1 1 1 1 0 X X 32/16 78000h–7BFFFh F0000h–F7FFFh
SA16 1111100 8/4 7C000h–7CFFFh F8000h–F9FFFh
SA17 1111101 8/4 7D000h–7DFFFh FA000h–FBFFFh
SA18 111111X 16/8 7E000h–7FFFFh FC000h–FFFFFh
12 Am29F800B 21504E7 August 3, 2009
DATA SHEET
Table 3. Am29F800BB Bottom Boot Block Sector Address Table
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” sectionfor more
information.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
Sector A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x16)
Address Range
(x8)
Address Range
SA0 000000X 16/8 00000h–01FFFh 00000h–03FFFh
SA1 0000010 8/4 02000h–02FFFh 04000h–05FFFh
SA2 0000011 8/4 03000h–03FFFh 06000h–07FFFh
SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh
SA4 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh
SA5 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh
SA6 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh
SA7 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh
SA8 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh
SA9 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh
SA10 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh
SA11 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh
SA12 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh
SA13 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
SA14 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA15 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA16 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
SA17 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA18 1 1 1 1 X X X 64/32 78000h–7FFFFh F0000h–FFFFFh
August 3, 2009 21504E7 Am29F800B 13
DATA SHEET
Table 4. Am29F800B Autoselect Codes (High Voltag e Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1. Temporary Sector Unprotect Operation
Description Mode CE# OE# WE#
A18
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID X L X L L X 01h
Device ID:
Am29F800B
(Top Boot Block)
Word L L H
X X VID X L X L H
22h D6h
Byte L L H X D6h
Device ID:
Am29F800B
(Bottom Boot Block)
Word L L H
X X VID X L X L H
22h 58h
Byte L L H X 58h
Sector Protection Verification L L H SA X VID X L X H L
X01h
(protected)
X00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
14 Am29F800B 21504E7 August 3, 2009
DATA SHEET
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
August 3, 2009 21504E7 Am29F800B 15
DATA SHEET
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is un-
protected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically provides internally gen-
erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the ad-
dress and data requirements for the byte program com-
mand sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
16 Am29F800B 21504E7 August 3, 2009
DATA SHEET
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
August 3, 2009 21504E7 Am29F800B 17
DATA SHEET
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
18 Am29F800B 21504E7 August 3, 2009
DATA SHEET
Command Definitions
Table 5. Am29F800B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
5. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” See
“Autoselect Command Sequence” for more information.
10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Cycle
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1RA RD
Reset (Note 7) 1XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block
Word 4555 AA 2AA 55 555 90 X01 22D6
Byte AAA 555 AAA X02 D6
Device ID,
Bottom Boot Block
Word 4555 AA 2AA 55 555 90 X01 2258
Byte AAA 555 AAA X02 58
Sector Protect Verify
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Byte AAA 555 AAA (SA)
X04
00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 10) 1XXX B0
Erase Resume (Note 11) 1XXX 30
August 3, 2009 21504E7 Am29F800B 19
DATA SHEET
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
20 Am29F800B 21504E7 August 3, 2009
DATA SHEET
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. The timing dia-
grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Ta bl e 6 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
August 3, 2009 21504E7 Am29F800B 21
DATA SHEET
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Ta bl e 6 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
22 Am29F800B 21504E7 August 3, 2009
DATA SHEET
Table 6. Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation
DQ7
(Note 1) DQ6
DQ5
(Note 2) DQ3
DQ2
(Note 1) RY/BY#
Standard
Mode
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
August 3, 2009 21504E7 Am29F800B 23
DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . .+4.5 V to +5.5 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 6. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 7. Maximum Positive
Overshoot Waveform
24 Am29F800B 21504E7 August 3, 2009
DATA SHEET
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifcations are tested with VCC = VCCmax
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperature (>+85°C)
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET Input Load Current VCC = VCC max;
A9 = OE# = RESET# = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC ±1.0 µA
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
f = 5 MHz, Byte Mode 19 40 mA
CE# = VIL, OE# = VIH,
f = 5 MHz, Word Mode 19 50 mA
ICC2
VCC Active Write Current
(Notes 2, 3 and 4) CE# = VIL, OE# = VIH 36 60 mA
ICC3 VCC Standby Current (Notes 2, 5) CE#, OE#, and RESET# = VIH, 0.4 1mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC
+ 0.5 V
VID
Voltage for Autoselect and Temporary
Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
VLKO Low VCC Lock-Out Voltage (Note 4) 3.2 4.2 V
August 3, 2009 21504E7 Am29F800B 25
DATA SHEET
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. ICC active while Embedded Erase or Embedded Program is in progress.
2. Maximum ICC specifcations are tested with VCC = VCCmax
3. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max
±1.0 µA
ILIT
A9, OE#, RESET Input Load
Current
VCC = VCC max,
A9 = OE# = RESET = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max
±1.0 µA
ICC1
VCC Active Read Current
(Note 2)
CE# = VIL, OE# = VIH,
f = 5 MHz
Byte Mode
20 40 mA
CE# = VIL, OE# = VIH,
f = 5 MHz
Word Mode
28 50 mA
ICC2
VCC Active Write Current
(Notes 1, 2, 3) CE# = VIL, OE# = VIH 30 50 mA
ICC3 VCC Standby Current (Note 2) CE# and RESET# = VCC±0.5 V,
OE# = VIH 0.3 5µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID
Voltage for Autoselect and
Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage
IOH = –2.5 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V
VLKO
Low VCC Lock-Out Voltage
(Note 3) 3.2 4.2 V
26 Am29F800B 21504E7 August 3, 2009
DATA SHEET
TEST CONDITIONS
Table 7. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Te s t
Figure 8. Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition -55
All
others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 100 pF
Input Rise and Fall Times 520 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8, 2.0 V
Output timing measurement
reference levels 1.5 0.8, 2.0 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
August 3, 2009 21504E7 Am29F800B 27
DATA SHEET
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 8 and Tabl e 7 for test specifications.
Parameter
Description
Speed Options
JEDEC Std Test Setup -55 -70 -90 -120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL
Max 55 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 20 20 30 ns
tGHQZ tDF
Output Enable to Output High Z
(Note 1) Max 20 20 20 30 ns
tOEH
Output Enable
Hold Time
(Note 1)
Read Min 0ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs First
(Note 1)
Min 0ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Figure 9. Read Operations Timings
28 Am29F800B 21504E7 August 3, 2009
DATA SHEET
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRB RY/BY# Recovery Time Min 0ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 10. RESET# Timings
August 3, 2009 21504E7 Am29F800B 29
DATA SHEET
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter Speed Options
JEDEC Std Description -55 -70 -90 -120 Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 20 20 20 30 ns
tFHQV BYTE# Switching High to Output Active Min 55 70 90 120 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
tELFH
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
BYTE#
Switching
from byte
to word
mode
Figure 11. BYTE# Timings for Read Operations
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 12. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
30 Am29F800B 21504E7 August 3, 2009
DATA SHEET
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter
Description
Speed Options
JEDEC Std -55 -70 -90 -120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns
tAVWL tAS Address Setup Time Min 0ns
tWLAX tAH Address Hold Time Min 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 25 30 45 50 ns
tWHDX tDH Data Hold Time Min 0ns
tOES Output Enable Setup Time Min 0ns
tGHWL tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0ns
tELWL tCS CE# Setup Time Min 0ns
tWHEH tCH CE# Hold Time Min 0ns
tWLWH tWP Write Pulse Width Min 30 35 45 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Programming Operation (Note 2)
Byte Typ 7
µs
Word Ty p 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 30 30 35 50 ns
August 3, 2009 21504E7 Am29F800B 31
DATA SHEET
AC CHARACTERISTICS
Figure 13. Program Operation Timings
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
32 Am29F800B 21504E7 August 3, 2009
DATA SHEET
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
RY/BY#
tRB
tBUSY
Note: SA = Sector Address. VA = Valid Address for reading status data.
Figure 14. Chip/Sector Erase Operation Timings
August 3, 2009 21504E7 Am29F800B 33
DATA SHEET
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
34 Am29F800B 21504E7 August 3, 2009
DATA SHEET
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect Min 4µs
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
Figure 17. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
0 or 5 V
Figure 18. Temporary Sector Unprotect Timing Diagram
August 3, 2009 21504E7 Am29F800B 35
DATA SHEET
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description -55 -70 -90 -120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns
tAVEL tAS Address Setup Time Min 0ns
tELAX tAH Address Hold Time Min 45 45 45 50 ns
tDVEH tDS Data Setup Time Min 25 30 45 50 ns
tEHDX tDH Data Hold Time Min 0ns
tOES Output Enable Setup Time Min 0ns
tGHEL tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low) Min 0ns
tWLEL tWS WE# Setup Time Min 0ns
tEHWH tWH WE# Hold Time Min 0ns
tELEH tCP CE# Pulse Width Min 30 35 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
tWHWH1 tWHWH1
Programming Operation
(Note 2)
Byte Typ 7
µs
Word Ty p 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1sec
36 Am29F800B 21504E7 August 3, 2009
DATA SHEET
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
Figure 19. Alternate CE# Controlled Write Operation Timings
August 3, 2009 21504E7 Am29F800B 37
DATA SHEET
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Tab l e 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 3) Unit Comments
Sector Erase Time 1.0 8 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time (Note 2) 19 s
Byte Programming Time 7300 µs
Excludes system level
overhead (Note 5)
Word Programming Time 12 500 µs
Chip Programming Time
(Note 2)
Byte Mode 7.2 21.6 s
Word Mode 6.3 18.6 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 67.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C10 Ye a r s
125°C20 Ye a r s
38 Am29F800B 21504E7 August 3, 2009
DATA SHEET
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
August 3, 2009 21504E7 Am29F800B 39
DATA SHEET
PHYSICAL DIMENSIONS (continued)
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
40 Am29F800B 21504E7 August 3, 2009
DATA SHEET
PHYSICAL DIMENSIONS (continued)
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm package
Dwg rev AF; 10/99
August 3, 2009 21504E7 Am29F800B 41
DATA SHEET
REVISION SUMMARY
Revision A (August 1997)
Initial release.
Revision B (October 1997)
Global
Added -55 speed option. Changed data sheet designa-
tion from Advance Information to Preliminary.
Sector Protection/Unprotection
Corrected text to indicate that these functions can only
be implemented using programming equipment.
Table 1, Device Bus Operations
Revised to indicate inputs for both CE# and RESET#
are required for standby mode.
Program Command Sequence
Changed to indicate Data# Polling is active for 2 µs
after a program command sequence if the sector spec-
ified is protected.
Sector Erase Command Sequence and DQ3: Sector
Erase Timer
Corrected sector erase timeout to 50 µs.
Erase Suspend Command
Changed to indicate that the device suspends the
erase operation a maximum of 20 µs after the rising
edge of WE#.
DC Characteristics
Changed to indicate VID min and max values are 11.5
to 12.5 V, with a VCC test condition of 5.0 V. Added
typical values to TTL table. Revised CMOS typical
standby current (ICC3).
Figure 14: Chip/Sector Erase Operation Timings;
Figure 19: Alternate CE# Controlled Write
Operation TImings
Corrected hexadecimal values in address and data
waveforms. In Figure 19, corrected data values for chip
and sector erase.
Erase and Programming Performance
Corrected word and chip programming times.
Revision C (January 1998)
Global
Formatted for consistency with other 5.0 volt-only
data sheets.
Revision C+1 (April 1998)
Distinctive Characteristics
Changed typical program/erase current to 30 mA to
match the CMOS DC Characteristics table.
Changed minimum endurance to 1 million write cycles
per sector guaranteed.
AC Characteristics
Erase/Program Operations: Corrected the notes refer-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Changed tDS and tCP specifications for 55
ns device. Changed tWHWH1 word mode specification
to 12 µs.
Alternate CE# Controlled Erase/Program Operations:
Corrected the notes reference for tWHWH1 and tWHWH2.
These parameters are 100% tested. Changed tDS and
tCP specifications for 55 ns device. Changed tWHWH1
word mode specification to 12 µs.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Erase and Programming Performance
In Notes 1 and 6, changed the endurance specification
to 1 million cycles.
Revision C+2 (April 1998)
Product Selector Guide
Deleted the -55 speed option for VCC = 5.0 V ± 5%.
Added the -55 speed option for VCC = 5.0 V ± 10%.
Ordering Information
Valid Combinations for Am29F800BT-55 and
Am29F800BB-55: Added the extended temperature
range for all package types.
Operating Ranges
VCC Supply Voltages: Deleted “VCC for ± 5% devices .
. . . +4.75 V to +5.25 V”. Changed “VCC for ±10%
devices . . . . +4.5 V to +5.5 V” to “VCC for all devices .
. . . +4.5 V to +5.5 V”.
Erase and Programming Performance
Note 2: Deleted “(4.75 V for -55)”.
42 Am29F800B 21504E7 August 3, 2009
DATA SHEET
REVISION SUMMARY (Continued)
Revision D (January 1999)
Distinctive Characteristics
Added the 20-year data retention subbullet.
Ordering Information
Optional Processing: Deleted “B = Burn-in”.
DC Characteristics—TTL/NMOS Compatible
ILIT: Added OE# and RESET to the Description column.
Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5
V” in the Test Conditions column.
ILO, ICC1, ICC2: Deleted “VCC = VCCmax” in
Te s t Conditions.
ICC3: Added Note 4, “ICC3 = 20 µA max at extended
temperatures (>+85°C)”.
DC Characteristics—CMOS Compatible
ILIT: Added OE# and RESET to the Description column.
Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5
V” in the Test Conditions column.
ICC1, ICC2, ICC3: Deleted “VCC = VCCmax”; added
Note 2 “Maximum ICC specifications are tested with
VCC = VCCmax”.
Revision D+1 (March 23, 1999)
Command Definitions table
Corrected SA definition in legend; range should be
A18–A12. In Note 4, A17 should be A18.
Revision D+2 (July 2, 1999)
Global
Added references to availability of device in Known
Good Die (KGD) form.
Revision E (November 16, 1999)
AC Characteristics—Figure 13. Program
Operations Timing and Figure 14. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision E+1 (August 4, 2000)
Global
Added FBGA package.
Revision E+2 (June 4, 2004)
Ordering Information
Added Pb-Free OPNs.
Revision E3 (December 22, 2005)
Global
Deleted reverse TSOP package option and 150 ns
speed option.
Revision E4 (May 19, 2006)
Added “Not recommended for new designs” note.
AC Characteristics
Changed tBUSY specification to maximium value.
Revision E5 (November 2, 2006)
Deleted “Not recommended for new designs” note.
Revision E6 (March 3, 2009)
Global
Added obsolescence information.
Revision E7 (August 3, 2009)
Global
Removed obsolescence information.
August 3, 2009 21504E7 Am29F800B 43
DATA SHEET
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
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development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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