EPSON GRAPHICS SPC8106F0C October 1998 SPC8106F0C VGA LCD CONTROLLER DESCRIPTION The SPC8106F0C is a versatile mixed voltage VGA graphics controller capable of driving liquid crystal displays, TFT displays and analog CRT monitors. The controller integrates all LCD interface, sequencing and color modulation logic into one small form factor 144 pin package. With the addition of an industry standard '477 compatible RAMDAC, the SPC8106F0C will also drive a VGA fixed frequency or multifrequency monitor. The target products for this device are price and power sensitive 80x86 microprocessor based portable personal computer or other specialized LCD systems where 320 x 200 to 640 x 480 x 256 color LCD panel displays are the major design criteria. FEATURES * Low-power CMOS technology * Hardware VGA compatible * 8- or 16-bit ISA support * Supports one 256K x 16 80ns DRAM (self refresh optional) * 64 x 64 x 2-bit pixel hardware cursor * Two-terminal crystal or external oscillator support * Hardware or software power-down * Video BIOS, software driver and utility support * 144-pin QFP package * 9- or 12-bit color TFT panel interface for 640 x 480 * Single panel or dual panel interface for sizes 320 x 200 to 640 x 480 * On-chip 256 x 12-bit look-up table * 16 gray shades or 4096 colors by FRM * 64 gray shades by FRM and dithering * Two programmable gray-scale weightings: NTSC and Green-Only * Vertical centering and expansion for LCDs * Full CRT support with '477 compatible RAMDAC * Pin Compatible with the SPC8108F0C * Mixed voltage 3.3V/5V operation SYSTEM BLOCK DIAGRAM CLOCKS MONOCHROME 3.3V or 5V ISA BUS 3.3V or 5V LCD PANEL SPC8106 3.3 V or 5V RAMDAC ANALOG 3.3V or 5V CRT DRAM X12-DS-001-09 1 GRAPHICS SPC8106F0C INTERFACE OPTIONS 25.175 MHz 7 pF SUSPEND# P[7:0] PCLK DACRD# DACWR# OL[0] OL[1] OL23 RS2 D477 BLANK# MEMCS16# IOCS16# ALE BHE# SUSPEND# PDCLK IREF P[7:0] CLOCK /RD /WR R,G,B Bt477 RAMDAC OL[3:0] RS2 477/471 BLANK# A[9:0] D[0:15] RAS# LCAS# UCAS# WE# /OE CRT MONITOR HSYNC# VSYNC# MS[2:0] SA[1:0] 32KHz 50% duty SPC8106F0C YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 RS[1:0] BALE -SHBE IREFEN# MA[9:0] MD[15:0] RAS# LCAS# UCAS# WE# -MEMCS16 -IOCS16 YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 LCD DISPLAY D[7:0] IOEN# IOR# IOW# MEMR# MEMW# READY IRQ RESET A[16:0], LA[23:17] D[15:0] 2 M D[7:0] MEMEN AEN -IOR -IOW -SMEMR -SMEMW IOCHRDY IRQ2 7 pF CLKI2 -REFRESH CLKI1 ISA BUS CLKO1 2 M 16 Bit RESET DRV SA[16:0], LA[23:17] D[15:0] 7 pF CLKO2 7 pF 28.322 MHz italics = components required for CRT support 256K x 16 DRAM Note: Example implementation, actual may vary. 2 X12-DS-001-09 GRAPHICS SPC8106F0C SUPPORTED RESOLUTIONS LCD Display Modes Mode No. 0 0+ 0++ 1 1+ 1++ 2 2+ 2++ 3 3+ 3++ 4 5 6 7 7+ 0D 0E 0F 10 11 12 13 100 101 108 Mode Type Text Text Text Text Text Text Text Text Text Text Text Text Graphics Graphics Graphics Text Text Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Text X12-DS-001-09 Font Characters Resolution 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 N/A N/A N/A 8 x 14 8 x 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A 8x8 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 N/A N/A N/A 80 x 25 80 x 25 N/A N/A N/A N/A N/A N/A N/A N/A N/A 80 x 60 320 x 200 320 x 350 320 x 400 320 x 200 320 x 350 320 x 400 640 x 200 640 x 350 640 x 400 640 x 200 640 x 350 640 x 400 320 x 200 320 x 200 640 x 200 640 x 350 640 x 400 320 x 200 640 x 200 640 x 350 640 x 350 640 x 480 640 x 480 320 x 200 640 x 400 640 x 480 640 x 480 Displayed Gray Pixels Shades 640 x 400 16 640 x 350 16 640 x 400 16 640 x 400 16 640 x 350 16 640 x 400 16 640 x 400 16 640 x 350 16 640 x 400 16 640 x 400 16 640 x 350 16 640 x 400 16 640 x 400 4 640 x 400 4 640 x 400 2 640 x 350 2 640 x 400 2 640 x 400 16 640 x 400 16 640 x 350 2 640 x 350 16 640 x 480 2 640 x 480 16 640 x 400 64 640 x 400 64 640 x 480 64 640 x 480 16 Colors 16 16 16 16 16 16 16 16 16 16 16 16 4 4 2 2 2 16 16 2 16 2 16 256 256 256 16 Memory Segment B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B000 B000 A000 A000 A000 A000 A000 A000 A000 A000 A000 B800 3 GRAPHICS SPC8106F0C CRT Display Modes Mode No. 0 0+ 0++ 1 1+ 1++ 2 2+ 2++ 3 3+ 3++ 4 5 6 7 7+ 0D 0E 0F 10 11 12 13 100 101 108 Mode Type Font Text Text Text Text Text Text Text Text Text Text Text Text Graphics Graphics Graphics Text Text Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Text 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 N/A N/A N/A 8 x 14 9 x 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A 8x8 Characters Resolution 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 N/A N/A N/A 80 x 25 80 x 25 N/A N/A N/A N/A N/A N/A N/A N/A N/A 80 x 60 320 x 200 320 x 350 360 x 400 320 x 200 320 x 350 360 x 400 640 x 200 640 x 350 720 x 400 640 x 200 640 x 350 720 x 400 320 x 200 320 x 200 640 x 200 640 x 350 720 x 400 320 x 200 640 x 200 640 x 350 640 x 350 640 x 480 640 x 480 320 x 200 640 x 400 640 x 480 640 x 480 Displayed Pixels 640 x 400 640 x 350 720 x 400 640 x 400 640 x 350 720 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 400 640 x 400 640 x 350 720 x 400 640 x 400 640 x 400 640 x 350 640 x 350 640 x 480 640 x 480 640 x 400 640 x 400 640 x 480 640 x 480 Colors 16 16 16 16 16 16 16 16 16 16 16 16 4 4 2 2 2 16 16 2 16 2 16 256 256 256 16 Memory Segment B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B000 B000 A000 A000 A000 A000 A000 A000 A000 A000 A000 B800 SUPPORTED LCD INTERFACES 8-Bit Interface Dual Panel Horizontal 640 4 Vertical 400 480 4-Bit Interface Single Panel Single Panel Horizontal Vertical Horizontal Vertical 640 1 to 480 320 480 640 200 240 320 400 480 X12-DS-001-09 X12-DS-001-09 DRAM CONTROL MA[9:0] MD[15:0] PDCLK CLKO1 CLKI1 CLKO2 CLKI2 D[15:0] 16-BIT BUS CONTROL A[23:0] POWER SAVE CLOCK GENERATOR MEMORY DECODER PORT DECODER DISPLAY MEMORY INTERFACE ADDRESS GENERATOR MAP 3 MAP 0 GRAPHICS CONTROLLER CRT CONTROLLER SEQUENCER AUXILIARY PORTS ATTRIBUTE CONTROLLER VGA PORTS LOOK-UP TABLE CRT INTERFACE LCD PANEL INTERFACE HARDWARE CURSOR P[7:0] PCLK HSYNC # VSYNC # BLANK # DACRD # DACWR # OL23 OL0 OL1 D477 RS2 UD[3:0] LD[3:0] XSCL XSCL2 LP YD WF LCDPWR # GRAPHICS SPC8106F0C BLOCK DIAGRAM 5 GRAPHICS SPC8106F0C FUNCTIONAL BLOCK DESCRIPTION The Sequencer The Sequencer generates internal signals to synchronize the operation of the chip as well as the signals to control the timing of the display DRAM. The Sequencer also arbitrates between CPU and video display accesses to the DRAM. It contains registers that allow the selection of the character font set, control the structure of the video memory and allow write masking of the individual plane of memory. CRT Controller The CRT Controller generates the horizontal and vertical synchronization signals for the CRT, single panel or dual panel LCD display and character and/or pixel addresses for display data from DRAM. CRT Interface The CRT Interface aligns CRT signals to the Pixel Clock and generates the I/O Control signals for CPU access to the RAMDAC. Address Generator The Address Generator takes the display and refresh addresses from the CRT Controller and converts them into RAS and CAS addresses for the display DRAM, and multiplexes these display accesses with CPU memory accesses. Attributes Controller The Attributes Controller takes in pixel and attribute information from the Graphics Controller and display DRAM and formats the data into pixel information which then passes through the lookup table. It also controls display character attributes such as blink, underline and horizontal pixel panning. Graphics Controller The Graphics Controller supplies display memory data to the Attributes Controller during display time and provides data translation between the CPU bus and the display memory during CPU read or write access cycles. Display Memory Interface The Display Memory Interface is a bridge by which the chip communicates with the DRAM. It contains buffers that are used to store recently fetched DRAM data. Port Decoder The Port Decoder decodes CPU-bus I/O cycles to provide enable and write strobes for the on-chip I/O registers. Auxiliary Ports The Auxiliary Ports are I/O registers used to control functions of the chip beyond the basic VGA register set. Registers are included for controlling the LCD interface circuits as well as the power save modes. VGA Ports The VGA Ports contain the Miscellaneous Output Status register and the Video Subsystem Enable register used in VGA mode. Clock Generation The Clock Generation contains oscillator support for external crystals. Power Save Power Save contains the logic to implement six software controlled and one hardware controlled power down modes. Lookup Table The Lookup Table consists of a memory array of 256 locations of 12 bits each and hardware to convert VGA palette writes to gray-scale values. LCD Interface The LCD Interface converts the display video data from the Lookup Table into LCD display data. It also generates control signals necessary to drive single or dual-panel LCD panels. For monochrome LCD panels, the LCD Interface generates a maximum 64 gray shades through frame rate modulation and dithering techniques. For color LCD panels, the LCD Interface generates 256 simultaneous colors from a possible 4096 colors through frame rate modulation. Hardware Cursor The Hardware Cursor generates a 4 gray shade or color cursor/sprite that can be overlaid on the LCD or CRT display. The cursor is 64 x 64 pixels or optionally expanded to 128 x 128 through pixel replication. Memory Decoder The Memory Decoder monitors the CPU-bus activity and decodes cycles for the display DRAM. It supplies memory access control signals to the Sequencer. 6 X12-DS-001-09 GRAPHICS SPC8106F0C DC SPECIFICATIONS Absolute Maximum Ratings Symbol VDD VIN VOUT TOPR TSTG TSOL Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Soldering Temperature/Time Rating VSS-0.3 to +7.0 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 0 to +70 -65 to +150 260 for 10sec max at lead Units V V V C C C Recommended Operating Conditions Symbol HVDD LVDD VIN TOPR Parameter Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition VSS = 0V VSS = 0V VSS IOPR Average Current Consumption Vcc Core = 3.3V VCC I/O = 5.0V Min Typ Max 4.5 5.0 5.5 3.0 3.3 3.6 VSS -VDD 0 25 70 typical ICore = 52.31 typical IIO = 13.85 Units V V V C mA Input Specifications Symbol VH Parameter Low Level Input Voltage (CMOS inputs) High Level Input Voltage (CMOS inputs) Low Level Input Voltage (TTL inputs) High Level Input Voltage (TTL inputs) Positive-going Threshold (CMOS Schmitt inputs) Negative-going Threshold (CMOS Schmitt inputs) Hysteresis Voltage (CMOS Schmitt inputs) Positive-going Threshold (TTL Schmitt inputs) Negative-going Threshold (TTL Schmitt inputs) Hysteresis Voltage (TTL Schmitt inputs) IIZ Input Leakage Current CIN RPU2 RPU3 RPD Input Pin Capacitance Pull Up Resistance Pull Up Resistance Pull Down Resistance VIL VIH VIL VIH VT+ VTVH VT+ VT- X12-DS-001-09 Condition Min Typ VDD = MIN VDD = MAX Units 1.0 V 3.5 V VDD = MIN VDD = MAX Max 0.8 2.0 V V VDD = 5.0 4.0 V VDD = 5.0 0.8 V VDD = 5.0 0.3 V VDD = 5.0 3.0 V VDD = 5.0 0.6 V VDD = 5.0 0.1 V VDD = MAX VIH = VDD VIL = VSS -1 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V 50 100 100 8 100 200 200 1 A 200 400 400 pF k k k 7 GRAPHICS SPC8106F0C Output Specifications Symbol Parameter IOL2 Low Level Output Current IOH2 High Level Output Current IOL3 Low Level Output Current IOH3 High Level Output Current IOL4 Low Level Output Current IOH4 High Level Output Current IOZ Output Leakage Current COUT Output Pin Capacitance Bidirectional Pin Capacitance CBID 8 Condition VOL=VSS+0.4V TS2 VOH=VDD-0.4V TS2 VOL=VSS+0.4V TS3 VOH=VDD-0.4V TS3 VOL=VSS+0.4V TS4 VOH=VDD-0.4V TS4 VOH=VDD or VOL=VSS Min Typ Max Units 6.0 mA -2.0 mA 12.0 mA -4.0 mA 24.0 mA -8.0 mA -1 1 A 8 pF 10 pF X12-DS-001-09 GRAPHICS SPC8106F0C A14 A15 A16 IOVSS IOVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RESET READY PDCLK IOVSS 76 75 74 73 84 83 82 81 80 79 78 77 93 92 91 90 89 88 87 86 85 101 100 99 98 97 96 95 94 IOVSS MS0 MD4 MD11 MD5 MD10 MD6 MD9 MD7 MD8 LCAS# SPC8106F0C WE# UCAS# RAS# MA8 MA0 MA7 MA1 MA6 MA2 MA5 MA3 IOVDD IOVSS MA4 IREFEN# RS2 DACWR# BLANK# DACRD# VSYNC# HSYNC# D477 OL0 OL1 COREVDD 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 IOVDD LA17 LA18 LA19 LA20 LA21 LA22 LA23 XSCL2 YD VSS XSCL LP 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 COREVDD A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 COREVDD WF LD0 LD1 LD2 LD3 MA9 LCDPWR# UD0 UD1 UD2 UD3 P0 P1 P2 P3 P4 P5 P6 P7 PCLK OL23 VSS 120 121 122 123 124 125 MEMCS16# MEMW# MEMEN MEMR# IOW# IOR# IOEN# COREVDD CLKO1 CLKI1 VSS VSS CLKO2 CLKI2 COREVDD SUSPEND# MS2 MS1 MD0 MD15 MD1 MD14 MD2 MD13 MD3 MD12 IOVDD 109 110 111 112 113 114 115 116 117 118 119 A2 A1 A0 IRQ ALE BHE# IOCS16# VSS A3 108 107 106 105 104 103 102 SPC8106 PIN OUT X12-DS-001-09 9 GRAPHICS SPC8106F0C PIN DESCRIPTION Key A I O = Analog = Input = Output I/O = Bidirectional P = Power CPU Interface Pin Name A[0:16], LA[17:23] Type Pin # I Description 104..107, 110..122, 2..4, 5..8 CPU bus address inputs. In Suspend Mode, the Address inputs are internally masked off. If the value on MD[5] at RESET = 1, then the ALE input pin is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, where pins A[0:16], LA[17:23] should be connected to the ISA bus signals SA[0:16], LA[17:23] respectively. ALE I 102 ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled. If the value on MD[5] at RESET = 1, then the ALE input is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. In this mode, the processor ADS# output should be connected to this pin. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, and only the LA[19:17] inputs are internally latched. D[0:15] I/O 125..140 16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles, and are in a hi-Z state at all other times. In Suspend Mode, these inputs are internally masked off. MEMEN I 97 ISA Bus Memory Enable. This signal should be connected to the REFRESH# signal on the ISA bus. When this signal is low (e.g. during a system memory refresh cycle), memory address decoding is disabled. IOR# I 94 ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is disabled. IOW# I 95 ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is disabled. MEMR# I 96 ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is disabled. MEMW# I 98 ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input is disabled. IOEN# I 93 ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal. When this signal is high, I/O address decoding is disabled. In Suspend Mode, the IOEN# input is disabled. READY O 142 ISA Bus READY signal. This output is driven low to force the CPU to insert wait states during memory cycles. READY is released to high-Z after a transfer is complete. RESET I 141 The active high Reset signal from the CPU clears all internal registers and forces all signals to their inactive state. 103 ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A control bit in the Auxiliary Registers allows this output to be optionally disabled (tristated). This pin also is used for the output of the NAND tree in pin test mode. 99 ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive this output low when a valid memory address (AXXXXh, BXXXXH) appears on the bus. IRQ O MEMCS16# O 10 X12-DS-001-09 GRAPHICS SPC8106F0C Pin Name Type Pin # Description IOCS16# O 100 ISA Bus I/O Chip Select 16. Address inputs A[15:0] and IOEN# are decoded to drive this output low when a valid SPC8106F0C I/O register address appears on the bus. Note that I/O addresses 3C6h-3C9h do not result in IOCS16# being driven low (i.e. RAMDAC and internal LUT register reads and writes are 8 bit cycles). BHE# I 101 ISA Bus Byte High Enable. In Suspend Mode the BHE# input is disabled. Video Memory Interface Pin Name Type Pin # Description O 57, 55, 53, 51, 48, 52, 54, 56, 58, 20 Multiplexed row/column address bits for video display memory. MD[0:15] I/O 81, 79, 77, 75, 70, 68, 66, 64, 63, 65, 67, 69, 74, 76, 78, 80 Data bits for video display memory. The output drivers of these pins are placed into a high-impedance state when RESET is high, or when the Sequencer is in a reset state. On the falling edge of RESET, the values on MD[3:0] and MD[12:9] are latched into a read-only Auxiliary Register and are available to be read as configuration inputs. Also, the value on MD[8:4] and MD[15:13] are used to configure various hardware options. See "Summary of Configuration Options" on page 15 for details. RAS# O 59 DRAM Row Address Strobe for single 256Kx16 DRAM. LCAS# (LWE#) O 62 Multiple Function: DRAM Column Address Strobe for low byte (LCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 16. UCAS# (CAS#) O 60 Multiple Function: DRAM Column Address Strobe for high byte (UCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 16. WE# (UWE#) O 61 Multiple Function: DRAM Write Enable Strobe (WE#). For alternate function see "Multiple Function Pin Descriptions" on page 16. Pin Name Type Pin # Description CLKI1 I 90 This pin, along with CLKO1 is the 25.175 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. CLKO1 O 91 This pin, along with CLKI1 is the 25.175 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. CLKI2 I 86 This pin, along with CLKO2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. CLKO2 O 87 This pin, along with CLKI2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. MA[0:9] Clock Inputs X12-DS-001-09 11 GRAPHICS SPC8106F0C LCD Panel Interface Pin Name Type Pin # Description YD O 10 Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row drivers (Y drivers) to indicate the start of the vertical frame. LP O 13 Latch Pulse output. The falling edge of this signal is used to latch a row of display data in the LCD module's column driver shift registers and to turn on the row driver (Y driver) for that line. XSCL O 12 Shift Clock for LCD data. Display data is clocked out of the chip on the rising edge of this signal, to be shifted into the LCD panel module column drivers (X drivers) on each falling edge. XSCL2 O 9 This second shift clock is used together with XSCL in 8-bit single color panel mode to shift in alternate sets of display data. XSCL2 is also used alone as the shift clock in 8-bit dual color panel mode and 4-bit single color panel mode. UD[0:3] O 22..25 Upper panel display data for dual panel - dual drive mode. For 8-bit single panelsingle drive mode, these bits are the most significant 4-bits of the 8-bit output data to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4 bits of data output to the panel. For 16-bit LCD modes, these outputs are the multiplexed upper panel data if MD[7]=1 at RESET, or the lower nibble of the upper panel data if MD[7]=0 at RESET. UD[4:7] O 26..29 When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode upper panel data. LD[0:3] O 16..19 Lower panel display data for dual panel-dual drive mode. For 8-bit single panelsingle drive mode, these bits are the least significant 4 bits of the 8-bit output data to the panel (data[3:0]). For 4-bit single panel mode, these outputs are driven low. For 16-bit LCD modes, these outputs are the multiplexed lower panel data if MD[7]=1 at RESET, or the lower nibble of the lower panel data if MD[7]=0 at RESET. LD[4:7] O 30..33 When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode lower panel data. LCDPWR# O 21 LCD power control. In normal operation this signal is driven low to enable an external LCD power supply. This signal is driven high when the chip is put into any power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the Sequencer is in a reset state. It can be used externally to turn off the panel supply voltage and backlight. After a RESET, this signal is held high until the CRTC is programmed and running. WF O 15 LCD Backplane Bias signal. This output toggles once every n LP periods, as programmed in Auxiliary Register [0D]. 12 X12-DS-001-09 GRAPHICS SPC8106F0C External CRT/RAMDAC Interface Pin Name Type Pin # Description P[0:7] O 26..33 When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits are connected to the pixel select inputs of the external RAMDAC. PCLK O 34 Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK. BLANK# O 44 Blank output. This output is clocked out on the falling edge of PCLK and is driven low during display blanking periods. HSYNC# O 41 Horizontal Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the horizontal retrace period. The polarity of this signal is determined by a control bit in register 3C2h. VSYNC# O 42 Vertical Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the vertical retrace period. The polarity of this signal is determined by a control bit in register 3C2h. DACRD# O 43 RAMDAC Read Strobe. This signal goes low when a valid read access to the VGA RAMDAC is decoded by the chip. DACWR# O 45 RAMDAC Write Strobe. This signal goes low when a valid write access to the VGA RAMDAC is decoded by the chip. 46 Register Select 2 output. This output should be connected to the RS2 input of the RAMDAC (Bt477 or equivalent). The logic level on this output may be set by setting Auxiliary Register [0B] bit 3. This signal is required to allow CPU access the control and overlay registers of the external RAMDAC. RS2 O Multiple Function: Overlay Select outputs 1:0 OL[0:1] OL23 D477 IREFEN# I/O O O O X12-DS-001-09 39, 38 When MD[13]=0 at RESET, these pins are outputs used to provide sprite/HW cursor function on the CRT display. In this case, these outputs should be connected to the OL[0:1] inputs of the RAMDAC (Bt477 or equivalent). They are used by the sprite circuitry to access the overlay registers in the RAMDAC. For alternate function see "Multiple Function Pin Descriptions" on page 16. 35 Overlay Select output 2/3. This output should be connected to both the OL2 and OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the sprite circuitry to access the overlay registers in the RAMDAC. For alternate function see "Multiple Function Pin Descriptions" on page 16. 40 477 Control Signal. This output should be connected to the 477/471 input of the RAMDAC (Bt477 or equivalent). This signal is used to access the control register of the RAMDAC and to allow it to be powered down. The logic level on this output can be controlled by setting Auxiliary Register [0B] bit 4, and is also controlled by the power save logic. 47 IREF Enable output. This signal is used to control the external current reference source required by the RAMDAC, allowing powering down the analog circuitry when not required. When this signal is driven low, the external current reference should be enabled. When this signal is high, the external current reference should be shut off. 13 GRAPHICS SPC8106F0C Pin Name MS[2:0] Type Pin # Description I/O Monitor Sense inputs. These signals should be connected to the monitor sense lines from the CRT monitor cable. The status of these bits is readable in Auxiliary Register [08] bits 2:0, and is used by BIOS software to determine the presence 83, 82, 71 and type of monitor connected. Optionally, the SENSE output of the RAMDAC may be connected to one of these inputs to allow the BIOS to read the SENSE signal and detect the monitor. MS[2:1] can be forced low by the DCC2 monitor support bits in Auxiliary Register [10] bits 1:0. Power Save Mode Control Pin Name Type SUSPEND# I PDCLK I Pin # Description 84 A low level on this pin puts the chip into a hardware power down mode. The SUSPEND# signal overrides any software initiated power down modes, and disables the ISA-Bus interface inputs except RESET. Address and Data inputs are also masked when this signal is low. When in Suspend Mode the UD(3:0), LD(3:0), XSCL, XSCL2, LP, YD and WF signals are driven into a high impedance or low state (configurable) and the LCDPWR# signal is driven high. 143 Power Down Clock. This input may be used to provide a low frequency clock for generating refresh in Power Save Modes 4 and Suspend, as an optional alternative to using the pixel clock or MEMEN input as the refresh clock source. This clock input should be driven by either by a 32 kHz 50% duty cycle clock source, or a 64 kHz clock source with a high period as short as possible (but > minimum RAS low pulse width) to minimize DRAM current consumption during refresh. The PDCLK input is used to directly generate the RAS and CAS pulses during Power Save Mode 4 and Suspend. Power Supply Pin Name Type Pin # Description COREVDD P 14, 37, 85, 92, 109 IOVDD P 1, 50, 73, 124 VDD supply for interface pins. VSS P 11, 36, 88, 89, 108 VSS supply for core logic. IOVSS P 49, 72, 123, 144 VSS supply for interface pins. 14 VDD supply for core logic. X12-DS-001-09 GRAPHICS SPC8106F0C Pin Mapping for Various Display Modes Display Mode SPC8106 Pin Name VSYNC# HSYNC# YD LP WF XCSL XCSL2 UD[3] UD[2] UD[1] UD[0] LD[3] LD[2] LD[1] LD[0] OL0 OL1 OL23 CRT VSYNC# HSYNC# None None None None None None None None None None None None None OL0 OL1 OL23 LCD None None YD LP WF XCSL XCSL2 UD[3] UD[2] UD[1] UD[0] LD[3] LD[2] LD[1] LD[0] None None None RGBI 12-bit RGB None None VSYNC# HSYNC# None (forced 0) PCLK None (forced 0) None (forced 0) None (forced 0) None (forced 0) None (forced 0) D[3] D[2] D[1] D[0] None None None None None VSYNC# HSYNC# None (forced 0) PCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] 9-bit None None VSYNC# HSYNC# DATAEN PANCLK R[2] B[2] B[1] B[0] R[1] G[2] G[1] G[0] R[0] None None None TFT 12-bit 12-bit AUX[00]b5=1 AUX[00]b5=1 AUX[0B]b1=0 AUX[0B]b1=1 None None VSYNC# HSYNC# DATAEN PANCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] VSYNC# HSYNC# None None DATAEN PANCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] Mixed Voltage Configurations Core VDD I/O VDD 3.3 V 5.0 V 3.3 V OK OK 5.0 V NO OK Summary of Configuration Options Pin Name value on this pin at falling edge of RESET is used to configure: MD[3:0] values latched into read-only Aux Reg[0C] bits 3:0 for software use MD[4] 16-bit I/O interface (1) / 8-bit I/O interface (0) MD[5] A[19:2] latched internally by ALE (1) / standard ISA bus ALE - A[16:0] not latched (0) (1/0) MD[6] 2 CAS, 1 WE type DRAM (1) / 1 CAS, 2 WE type DRAM (0) MD[7] support 16-bit panel with external logic (1) / support 16-bit panel directly (0) MD[8] 5 V core operating voltage (1) / 3.3 V core operating voltage (0) MD[12:9] values latched into read-only bits 7:4 of Aux Reg[0C] for software use MD[13] pins 38, 39 used for ext. RC for 32 kHz PDCLK (1) / pins 38, 39 used for OL[1:0] (0) MD[14] Internal PDCLK doubling disable (1) / enable (0) MD[15] 3C3h used as video enable port (1) / 46E8h and 102h used as video enable port (0) These inputs have internal pull-up resistors. Based on the value of the internal pull-ups, the external pull-down resistors if necessary, should be approximately 15K ohm. This value will provide the correct voltage levels on power-up without loading the DRAM Data lines (V DD = 5.0V). X12-DS-001-09 15 GRAPHICS SPC8106F0C Multiple Function Pin Descriptions Pin Name LCAS#, LWE# UCAS#, CAS# WE#, UWE# Function MD Line Status Functional Description LCAS# MD6 = 1 DRAM Column Address Strobe (Low Byte). LWE# MD6 = 0 DRAM Write Strobe (Low Byte). UCAS# MD6 = 1 DRAM Column Address Strobe (High Byte). CAS# MD6 = 0 DRAM Column Address Strobe. WE# MD[6] = 1 DRAM Write Strobe. UWE# MD[6] = 0 DRAM Write Strobe (High Byte). OL0 MD[13] = 0 AUX[00] b6=0 Overlay Bit 0. Used for CRT HW Cursor/Sprite support. MD[13] = 1 MD[14] = 1 32 kHz Clock Output. Used with external RC when using external PDCLK support. B0 MD[13] = 0 AUX[00] b6=1 Data bit B0 for 12-bit TFT support. OL1 MD[13] = 0 AUX[00] b6=0 Overlay Bit 1. Used for CRT HW Cursor/Sprite support. MD[13] = 1 MD[14] = 1 32 kHz Clock Input. Used with external RC when using external PDCLK support. G0 MD[13] = 0 AUX[00] b6=1 Data bit G0 for 12-bit TFT support. OL23 MD[13] = 0 AUX[00] b6=0 Overlay Bit 2. Used for CRT HW Cursor/Sprite support. R0 MD[13] = 0 AUX[00] b6=1 Data bit R0 for 12-bit TFT support. P[0:3} MD[7] = 1 Lower nibble of the CRT pixel data outputs. UD[4:7} MD[7] = 0 Upper nibble of the 16-bit LCD mode upper panel data. P[4:7] MD[7] = 1 Upper nibble of the CRT pixel data outputs. LD[4:7] MD[7] = 0 Upper nibble of the 16-bit LCD mode lower panel data. OL0, P320, B0 P320 OL1, P32I, G0 P32I OL23, R0 P[0:3] P[4:7] 16 X12-DS-001-09 GRAPHICS SPC8106F0C Illustrated below are the display data output which are output from the UD0 to UD3, LD0/UD4 to LD3/UD7 and the display on the panel: UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top 8-bit Single Panel LD3 LD2 LD1 LD0 Dual Panel - Bottom UD3 UD2 UD1 UD0 4-bit Single Panel LCD PANEL PIXELS 640 D O TS 1 - 1 1 - 2 1-639 1-640 2-1 2 -2 2-639 2-640 240 LINE S UP PER LC D P A N EL 240-1 240-2 2 4 0 - 639 2 4 0 - 64 0 241-1 241-2 2 4 1 - 639 241 - 640 4 8 0 - 639 480 - 640 (TO P V IE W ) 240 LINES LO W E R LC D P A N E L 480-1 X12-DS-001-09 480-2 17 GRAPHICS SPC8106F0C MONOCHROME PASSIVE STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 242 PULSES YD LP WF U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 240 LINE 2 LP WF XSCL: 80 CLOCK PERIODS XSCL UD3 1-1 1- 5 1 -317 UD2 1 -2 1-6 1 -318 UD1 1-3 1 -7 1 -319 UD0 1 -4 1 -8 1-320 Exam ple tim ing for a 320 x 240 panel 18 X12-DS-001-09 GRAPHICS SPC8106F0C MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[3:0] LD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL: 80 CLOCK PERIODS XSCL UD3 1-1 1-9 1-633 UD2 1-2 1-10 1-634 UD1 1-3 1-11 1-635 UD0 1-4 1-12 1-636 LD3 1-5 1-13 1-637 LD2 1-6 1-14 1-638 LD1 1-7 1-15 1-639 LD0 1-8 1-16 1-640 X12-DS-001-09 19 GRAPHICS SPC8106F0C MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[3:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[3:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL: 160 CLOCK PERIODS XSCL 20 UD3 1-1 1-5 1-637 UD2 1-2 1-6 1-638 UD1 1-3 1-7 1-639 UD0 1-4 1-8 1-640 LD3 241-1 241-5 241-637 LD2 241-2 241-6 241-638 LD1 241-3 241-7 241-639 LD0 241-4 241-8 241-640 X12-DS-001-09 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 242 PULSES YD LP WF U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 240 LINE 2 LP WF XSCL2: 240 CLOCK PERIODS XSCL 2 UD3 R1 G2 B3 UD2 G1 B2 R4 R320 B319 UD1 B1 R3 G4 G320 UD0 R2 G3 B4 B320 Exam ple tim ing for a 320 x 240 panel X12-DS-001-09 21 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[3:0] LD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL2: 120 CLOCK PERIODS XSCL2 XSCL: 120 CLOCK PERIODS XSCL 22 UD3 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-B635 1-R636 UD2 1-B1 1-R2 1-R7 1-G7 1-G12 1-B12 1-G636 1-B636 UD1 1-G2 1-B2 1-B7 1-R8 1-R13 1-G13 1-R637 1-G637 UD0 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1-B637 1-R638 LD3 1-B3 1-R4 1-R9 1-G9 1-G14 1-B14 1-G638 1-B638 LD2 1-G4 1-B4 1-B9 1-R10 1-R15 1-G15 1-R639 1-G639 LD1 1-R5 1-G5 1-G10 1-B10 1-B15 1-R16 1-B639 1-R640 LD0 1-B5 1-R6 1-R11 1-G11 1-G16 1-B16 1-G640 1-B640 X12-DS-001-09 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 8-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[3:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[3:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL2: 480 CLOCK PERIODS XSCL2 UD3 1-R1 1-G2 1-B3 1-R637 1-G638 1-B639 UD2 1-G1 1-B2 1-R4 1-G637 1-B638 1-R640 UD1 1-B1 1-R3 1-G4 1-B637 1-R639 1-G640 UD0 1-R2 1-G3 1-B4 1-R638 1-G639 1-B640 LD3 241-R1 241-G2 241-B3 241-R637 241-G638 241-B639 LD2 241-G1 241-B2 241-R4 241-G637 241-B638 241-R640 LD1 241-B1 241-R3 241-G4 241-B637 241-R639 241-G640 LD0 241-R2 241-G3 241-B4 241-R638 241-G639 241-B640 X12-DS-001-09 23 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 16-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[7:0] LD[7:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL: 120 CLOCK PERIODS XSCL 24 UD7 1-R1 1-G6 1-B11 1-R625 1-G630 1-B635 UD6 1-B1 1-R7 1-G12 1-B625 1-R631 1-G636 UD5 1-G2 1-B7 1-R13 1-G626 1-B631 1-R637 UD3 1-R3 1-G8 1-B13 1-R627 1-G632 1-B637 UD3 1-B3 1-R9 1-G14 1-B627 1-R633 1-G638 UD2 1-G4 1-B9 1-R15 1-G628 1-B633 1-R639 UD1 1-R5 1-G10 1-B15 1-R629 1-G634 1-B639 UD0 1-B5 1-R11 1-G16 1-B629 1-R635 1-G640 LD7 1-G1 1-B6 1-R12 1-G625 1-B630 1-R636 LD6 1-R2 1-G7 1-B12 1-R626 1-G631 1-B636 LD5 1-B2 1-R8 1-G13 1-B626 1-R632 1-G637 LD4 1-G3 1-B8 1-R14 1-G627 1-B632 1-R638 LD3 1-R4 1-G9 1-B14 1-R628 1-G633 1-B638 LD2 1-B4 1-R10 1-G15 1-B628 1-R634 1-G639 LD1 1-G5 1-B10 1-R16 1-G629 1-B634 1-R640 LD0 1-R6 1-G11 1-B16 1-R630 1-G635 1-B640 X12-DS-001-09 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 16-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[7:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[7:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL: 240 CLOCK PERIODS XSCL UD7 1-R1 1-B3 1-G6 1-R633 1-B635 1-G638 UD6 1-G1 1-R4 1-B6 1-G633 1-R636 1-B638 UD5 1-B1 1-G4 1-R7 1-B633 1-G636 1-R639 UD4 1-R2 1-B4 1-G7 1-R634 1-B636 1-G639 UD3 1-G2 1-R5 1-B7 1-G634 1-R637 1-B639 UD2 1-B2 1-G5 1-R8 1-B634 1-G637 1-R640 UD1 1-R3 1-B5 1-G8 1-R635 1-B637 1-G640 UD0 1-G3 1-R6 1-B8 1-G635 1-R638 1-B640 LD7 241-R1 241-B3 241-G6 241-R633 241-B635 241-G638 LD6 241-G1 241-R4 241-B6 241-G633 241-R636 241-B638 LD5 241-B1 241-G4 241-R7 241-B633 241-G636 241-R639 LD4 241-R2 241-B4 241-G7 241-R634 241-B636 241-G639 LD3 241-G2 241-R5 241-B7 241-G634 241-R637 241-B639 LD2 241-B2 241-G5 241-R8 241-B634 241-G637 241-R640 LD1 241-R3 241-B5 241-G8 241-R635 241-B637 241-G640 LD0 241-G3 241-R6 241-B8 241-G635 241-R638 241-B640 X12-DS-001-09 25 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 16-BIT SINGLE PANEL WITH EXTERNAL CIRCUIT LP : 482 PULSES YD LP WF P ix el D a ta LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 26 WF XSCL: 120 CLO CKS XSC L UD3 1 -R 1 1-B3 1 -B 6 3 5 1 -G 6 3 8 UD2 1-B1 1-G4 1 -G 6 3 6 1 - R 6 3 9 UD1 1-G2 1 -R 5 1-R 637 UD0 1 -R 3 1-B5 1-B637 1-G640 LD3 1-G1 1-R4 1-R636 1 -B 6 3 8 LD2 1-R2 1-B4 1-B636 1 -G 6 3 9 LD1 1 -B 2 1-G5 1 -G 6 3 7 1 -R6 4 0 LD0 1-G3 1 -R 6 1 -R6 3 8 1-B640 1 -B 6 3 9 1-R1 1-B635 U D6 1 -B 1 1-G636 U D5 1-G2 1-R637 EXTERNAL CIRCUIT U D4 1 -R 3 1 -B 6 3 7 (required when MD[7]=1 at reset) UD3 1-B3 1 -G 63 8 UD2 1-G4 1-R 639 UD1 1-R5 1 -B 6 3 9 UD0 1-B5 1-G640 1-G637 LD 4 1 -G 3 1-R638 LD 3 1 -R 4 1-B638 LD 2 1-B4 1-G639 LD 1 1-G5 1-R640 LD 0 1-R6 1-B640 CK 1 -B 2 XSCL LD 5 Q LD 6 D 1 -R 6 3 6 1 -B 6 3 6 UD[3:0] LD[3:0] 1-G1 1 -R 2 FROM SPC8106 LD 7 LD[7:4] U D7 UD[3:0] LD[3:0] TO 16-BIT UD[7:4] PANEL 16-bit PANEL INPUTS SPC8106 OUTPUTS LP X12-DS-001-09 GRAPHICS SPC8106F0C COLOR STN LCD PANEL INTERFACE 16-BIT DUAL PANEL WITH EXTERNAL CIRCUIT LP : 242 PULSES YD LP WF P ix el D a ta LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 WF XSCL: 240 CLO CKS XSC L UD3 1 -R 1 1-G2 1 -B 3 1 -G 6 3 8 1 -B 6 3 9 UD2 1-G1 1-B2 1-R4 1-B 638 1-R 640 UD1 1 -B 1 1 -R 3 1 -G 4 1 -R6 3 9 UD0 1 -R 2 1-G3 1 -B 4 1 -G 6 3 9 1 -B 6 4 0 241-R1 241-G2 241-B3 241G638 241B639 LD2 241-G1 241-B2 241-R4 241B 638 241R640 LD1 2 41 -B 1 2 4 1 -R 3 2 41 -B 4 241R639 241G640 LD0 2 4 1 -R 2 2 4 1-G3 2 41 -B 4 241G639 241B640 1 -R 1 1-G638 1-G1 1-B638 U D5 1-B1 1-R639 U D4 1-R2 1-G639 UD3 1-G2 1 -B 6 3 9 UD2 1 -B 2 1-R 640 UD1 1-R3 1 -G 6 4 0 UD0 1-G3 1 -B 6 4 0 LD 7 241-R1 2 4 1 -G 6 3 8 LD 6 241-G1 2 4 1 -B 6 3 8 EXTERNAL CIRCUIT (required when MD[7]=1 at reset) Q U D6 241-B1 2 4 1 -R 6 3 9 LD 4 241-R2 2 4 1 -G 6 3 9 LD 3 2 4 1-G2 241B 639 LD 2 2 41 -B 2 241R 640 LD 1 241-R3 241G640 LD 0 2 4 1-G3 241B 640 X12-DS-001-09 FROM SPC8106 XSCL UD[3:0] LD[3:0] D LD 5 CK U D7 LD[7:4] LD3 16-BIT PANEL INPUTS 1-G640 UD[3:0] LD[3:0] TO 16-BIT UD[7:4] PANEL SPC8106 OUTPUTS LP 27 GRAPHICS SPC8106F0C COLOR TFT PANEL INTERFACE Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=1 HRTC 350 PULSES 61 HRTC PULSES 350 Line Mode VSYNC#* HSYNC#* LINE 1 R [3:0], G [3:0], B[3:0]* 34 HRTC PULSES 400 Line Mode LINE 350 HRTC 400 PULSES VSYNC#* HSYNC#* LINE 1 R [3:0], G [3:0 ], B [3:0]* 480 Line Mode LINE 400 HRTC 480 PULSES 34 HRTC PULSES VSYNC#* HSYNC#* LINE 1 R [3:0], G [3:0 ], B [3:0]* LINE 480 H S Y N C#* (400, 480) H S Y NC#* (35 0) CLOCK: 640 CLOCKS PANCLK* DATAEN* R [3:0] * 1 -1 1-2 1 -64 0 G [3:0] * 1-1 1-2 1-640 B [3 :0] * 1-1 1-2 1-640 9-bit panels use data bits [2:0] * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names 28 X12-DS-001-09 GRAPHICS SPC8106F0C COLOR TFT PANEL INTERFACE Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=0 UP TO 1023 HRTC PULSES 2 ~ 6 5 HRTC PULSES VSYNC#*2 HSYNC#*2 LINE 1 *2 R[3:0 ], G [3:0 ], B [3:0 ] LINE 480 H S Y N C#*2 CLOCK: 640 CLOCKS 112 OR 160 CLOCKS PANCLK*2 *1 DATAEN*2 R[3:0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 G [3:0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 B [3:0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 9-bit panels use data bits [2:0] *1 - This number is controlled by Auxiliary Register [06] bit 2 *2 - Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names X12-DS-001-09 29 GRAPHICS SPC8106F0C RGB MODE PANEL INTERFACE 12-BIT RGB MODE PANEL HSYNC: 240 PULSES HSYNC: 2 PULSES VSYNC#* HSYNC#* R[3:0], G[3:0], B[3:0]* LINE 1/241 L IN E 2 / 2 4 2 L I N E 3 /2 4 3 L IN E 4 /2 4 4 L IN E 2 3 9 / 4 7 9 PCLK : 1280 CLOCKS L IN E 2 4 0 / 4 8 0 LINE 1/24 1 L IN E 2 / 2 4 2 PCLK : 224 CLOCKS HSYNC#* PCLK* R[3:0]* 1 -1 241-1 1-2 241-2 G[3:0]* 1-1 B[3:0]* 1 -1 241-1 1- 2 241 -2 241-1 1-2 241-2 2 41-640 2-1 242 -1 1-640 2 41-640 2-1 242 -1 2-2 1-640 2 41-640 2-1 242 -1 2-2 1-640 2-2 * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names RGBI MODE DUAL PANEL INTERFACE RGBI MODE DUAL PANEL HSYNC: 240 PULSES HSYNC: 2 PULSES VSYNC#* HSYNC#* I, R, G, B* LINE 1/24 1 L IN E 2 / 2 4 2 LINE 3/24 3 LINE 4/24 4 L IN E 2 3 9 / 4 7 9 PCLK : 1280 CLOCKS LIN E 240/48 0 L I NE 1 / 24 1 LINE 2/242 PCLK : 224 CLOCKS HSYNC#* PCLK* I, R,G, B* 1-1 241-1 1-2 241-2 1 -640 241-640 2-1 242-1 2-2 * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names 30 X12-DS-001-09 GRAPHICS SPC8106F0C PACKAGE DIMENSIONS QFP17 - 144 pin Unit: mm 22.0 0.4 20.0 0.1 73 108 72 20.0 0.1 22.0 0.4 109 Index 37 3.0 Max 0.15 0.05 144 1 0.5 0.1 0.2 0.1 36 0.1 0~10 0.5 0.2 1.0 Actual Size X12-DS-001-09 31 GRAPHICS SPC8106F0C COMPREHENSIVE SUPPORT TOOLS Seiko Epson provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation * Technical manuals * Evaluation/Demonstration board manual Evaluation/Demonstration Board * Assembled and fully tested Graphics Evaluation/Demonstration board * Schematic of Evaluation/Demonstration board * Parts List * Installation Guide * CPU Independent Software Utilities * Evaluation Software * Windows CE Display Driver Application Engineering Support Seiko Epson offers the following services through their Sales and Marketing Network: * Sales Technical Support * Customer Training * Design Assistance CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: * SPC8106C Technical Manual * SDU8106C Evaluation Boards * Windows CE Display Driver * CPU Independent Software Utilities FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS(R) CE CONTACT: Epson Research & Development, Inc. Suite #320 - 11120 Horseshoe Way Richmond, B.C., Canada V7A 5H7 Tel: (604) 275-5151 Fax: (604) 275-2167 Email: wince@erd.epson.com http://www.erd.epson.com Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 Copyright (c)1997, 1998 Seiko Epson Corp. All rights reserved. VDC Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windows CE Logo are registered trademarks of Microsoft Corporation. 32 X12-DS-001-09