SPC8106F0C - EPSON Research and Development, Inc.

GRAPHICS

SPC8106F0C

EPSON

X12-DS-001-09 1

October 1998

SPC8106F0C VGA LCD CONTROLLER

■DESCRIPTION

The SPC8106F0C is a versatile mixed voltage VGA graphics controller capable of driving liquid crystal displays,

TFT displays and ana log CRT monitor s. The con tr oll er i nte grates al l LCD inte rface, sequenci ng and color mo dul a-

tion logic into one small form factor 144 pin package. With the addition of an industry standard ’477 compatible

RAMDAC, the SPC8106F0C will also drive a VGA fixed frequency or multifrequency monitor.

The target products for this device are price and power sensitive 80x86 microprocessor based por table personal

computer or ot her s pec i ali zed LCD sy s tem s wh er e 3 20 x 200 to 640 x 480 x 256 color L CD pa nel di sp lays are th e

major design criteria.

■FEATURES

•Low-power CMOS technology

•Hardware VGA compatible

•8- or 16-bit ISA support

•Supports one 256K x 16 80ns DRAM (self refresh

optional)

•64 x 64 x 2-bit pixel hardware cursor

•Two-terminal crystal or external oscillator support

•Hardware or software power-down

•Video BIOS, software driver and utility support

•144-pin QFP package

•9- or 12-bit color TFT panel interface for 640 x 480

•Single panel or dual panel interface

for sizes 320 x 200 to 640 x 480

•On-chip 256 x 12-bit look-up table

•16 gray shades or 4096 colo rs by FRM

•64 gray shades by FRM and dithering

•Two programmable gray-scale weightings:

NTSC and Green-Only

•Vertical centering and expansion for LCDs

•Full CRT support with ’477 compatible RAMDAC

•Pin Compatible with the SPC8108F0C

•Mixed voltage 3.3V/5V operation

■SYSTEM BLOCK DIAGRAM

MONOCHROME

ISA SPC8106

DRAM

CLOCKS

BUS

LCD PANEL

ANALOG

CRT

RAMDAC

3.3V or 5V

3.3 V

3.3V or 5V

3.3V or 5 V

or 5V

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SPC8106F0C

X12-DS-001-09

■INTERFACE OPTIONS

Note: Example implementation, actual may v ary.

PCLK

VSYNC#

P[7:0]

CLOCK

/RD

/WR

BLANK#

OL[3:0]

Bt477

RAMDAC

CRT

MONITOR

R,G,B

477/471

IREFEN#

IREF

RS2

SA[1:0] RS[1:0]

D[7:0] D[7:0]

MS[2:0]

P[7:0]

BLANK#

HSYNC#

OL23

DACRD#

D477

RS2

DACWR#

PDCLK

32KHz

50% duty

SUSPEND#

MEMEN

READY

RESET

A[16:0],

LA[23:17]

D[15:0]

IOEN#

IOR#

IOW#

MEMR#

MEMW#

IRQ

-REFRESH

IOCHRDY

RESET DRV

SA[16:0],

LA[23:17]

D[15:0]

AEN

-IOR

-IOW

-SMEMR

-SMEMW

16 Bit

ISA BUS

IRQ2

-MEMCS16

-IOCS16 ALE

BHE#

BALE

-SHBE

SUSPEND#

XSCL

LCDPWR#

XSCL

UD[3:0]

LD[3:0]

LCDPWR#

UD[3:0]

LD[3:0]

LCD DISPLAY

2 MΩ

7 pF7 pF

25.175 MHz

CLKO1

CLKI1

2 MΩ

7 pF7 pF

28.322 MHz

CLKO2

CLKI2

MD[15:0]

WE#

UCAS#

LCAS#

RAS#

MA[9:0]

D[0:15]

WE#

UCAS#

RAS#

/OE

256K x 16 DRAM

LCAS#

A[9:0]

SPC8106F0C

MEMCS16#

IOCS16# OL[0]

OL[1]

XSCL2

italics

= components req uir ed

XSCL2

for CRT support

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SPC8106F0C

X12-DS-001-09 3

■SUPPORTED RESOLUTIONS

LCD Display Modes

Mode

No. Mode

Type Font Characters Resolution Displayed

Pixels Gray

Shades Colors Memory

Segment

0 Text 8 x 8 40 x 25 320 x 200 640 x 400 16 16 B800

0+ Text 8 x 14 40 x 25 320 x 350 640 x 350 16 16 B800

0++ Text 8 x 16 40 x 25 320 x 400 640 x 400 16 16 B800

1 Text 8 x 8 40 x 25 320 x 200 640 x 400 16 16 B800

1+ Text 8 x 14 40 x 25 320 x 350 640 x 350 16 16 B800

1++ Text 8 x 16 40 x 25 320 x 400 640 x 400 16 16 B800

2 Text 8 x 8 80 x 25 640 x 200 640 x 400 16 16 B800

2+ Text 8 x 14 80 x 25 640 x 350 640 x 350 16 16 B800

2++ Text 8 x 16 80 x 25 640 x 400 640 x 400 16 16 B800

3 Text 8 x 8 80 x 25 640 x 200 640 x 400 16 16 B800

3+ Text 8 x 14 80 x 25 640 x 350 640 x 350 16 16 B800

3++ Text 8 x 16 80 x 25 640 x 400 640 x 400 16 16 B800

4 Graphics N/A N/A 320 x 200 640 x 400 4 4 B800

5 Graphics N/A N/A 320 x 200 640 x 400 4 4 B800

6 Graphics N/A N/A 640 x 200 640 x 400 2 2 B800

7 Text 8 x 14 80 x 25 640 x 350 640 x 350 2 2 B000

7+ Text 8 x 16 80 x 25 640 x 400 640 x 400 2 2 B000

0D Graphics N/A N/A 320 x 200 640 x 400 16 16 A000

0E Graphics N/A N/A 640 x 200 640 x 400 16 16 A000

0F Graphics N/A N/A 640 x 350 640 x 350 2 2 A000

10 Graphics N/A N/A 640 x 350 640 x 350 16 16 A000

11 Graphics N/A N/A 640 x 480 640 x 480 2 2 A000

12 Graphics N/A N/A 640 x 480 640 x 480 16 16 A000

13 Graphics N/A N/A 320 x 200 640 x 400 64 256 A000

100 Graphics N/A N/A 640 x 400 640 x 400 64 256 A000

101 Graphics N/A N/A 640 x 480 640 x 480 64 256 A000

108 Text 8 x 8 80 x 60 640 x 480 640 x 480 16 16 B800

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SPC8106F0C

X12-DS-001-09

CR T Displ ay Modes

■SUPPORTED LCD INTERFACES

Mode

No. Mode Type Font Characters Resolution Displayed

Pixels Colors Memory

Segment

0 Text 8 x 8 40 x 25 320 x 200 640 x 400 16 B800

0+ Text 8 x 14 40 x 25 320 x 350 640 x 350 16 B800

0++ Text 9 x 16 40 x 25 360 x 400 720 x 400 16 B800

1 Text 8 x 8 40 x 25 320 x 200 640 x 400 16 B800

1+ Text 8 x 14 40 x 25 320 x 350 640 x 350 16 B800

1++ Text 9 x 16 40 x 25 360 x 400 720 x 400 16 B800

2 Text 8 x 8 80 x 25 640 x 200 640 x 400 16 B800

2+ Text 8 x 14 80 x 25 640 x 350 640 x 350 16 B800

2++ Text 9 x 16 80 x 25 720 x 400 640 x 400 16 B800

3 Text 8 x 8 80 x 25 640 x 200 640 x 400 16 B800

3+ Text 8 x 14 80 x 25 640 x 350 640 x 350 16 B800

3++ Text 9 x 16 80 x 25 720 x 400 640 x 400 16 B800

4 Graphics N/A N/A 320 x 200 640 x 400 4 B800

5 Graphics N/A N/A 320 x 200 640 x 400 4 B800

6 Graphics N/A N/A 640 x 200 640 x 400 2 B800

7 Text 8 x 14 80 x 25 640 x 350 640 x 350 2 B000

7+ Text 9 x 16 80 x 25 720 x 400 720 x 400 2 B000

0D Graphics N/A N/A 320 x 200 640 x 400 16 A000

0E Graphics N/A N/A 640 x 200 640 x 400 16 A000

0F Graphics N/A N/A 640 x 350 640 x 350 2 A000

10 Graphics N/A N/A 640 x 350 640 x 350 16 A000

11 Graphics N/A N/A 640 x 480 640 x 480 2 A000

12 Graphics N/A N/A 640 x 480 640 x 480 16 A000

13 Graphics N/A N/A 320 x 200 640 x 400 256 A000

100 Graphics N/A N/A 640 x 400 640 x 400 256 A000

101 Graphics N/A N/A 640 x 480 640 x 480 256 A000

108 Text 8 x 8 80 x 60 640 x 480 640 x 480 16 B800

8-Bit Interface 4-Bit Interface

Dual Panel Single Panel Single Panel

Horizontal Vertical Horizontal Vertical Horizontal Vertical

640 400

480 640 1

480

320

480

640

200

240

320

400

480

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SPC8106F0C

X12-DS-001-09 5

■BLOCK DIAGRAM

A[23:0]

16-BIT BUS

CONTROL

D[15:0]

CLKO1

CLKI1

CLKO2

CLKI2

PDCLK

MD[15:0]

MA[9:0]

DRAM

CONTROL

PORT

DECODER

MEMORY

DECODER

CLOCK

GENERATOR

POWER

SAVE

ADDRESS

GENERATOR

DISPLAY

MEMORY

INTERFACE

AUXILIARY

PORTS

SEQUENCER

CRT

CONTROLLER

GRAPHICS

CONTROLLER

VGA

PORTS

MAP 0

MAP 3

ATTRIBUTE

CONTROLLER LOOK-UP

TABLE

CRT

INTERFACE

LCD

PANEL

INTERFACE

HARDWARE

CURSOR

UD[3:0]

LD[3:0]

XSCL

LCDPWR #

P[7:0]

PCLK

HSYNC #

VSYNC #

BLANK #

DACRD #

DACWR #

OL23

OL0

OL1

D477

RS2

XSCL2

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SPC8106F0C

X12-DS-001-09 6

■FUNCTIONAL BLOCK DESCRIPTION

The Sequencer

The Sequencer generates internal signals to syn-

chronize the operation of the ch ip as well as the si g-

nals to control the timing of the display DRAM. The

Sequencer also arbitrates between CPU and video

display accesses to the DRAM. It contains registers

that allow the selection of the character font set, con-

trol the structure of the video memory and allow write

masking of the individual plane of memory.

CR T Controller

The CRT Controller generates the horizontal and ver-

tical synchronization signals for the CRT, single panel

or dual panel L CD display and c haracter and/or pi xel

addresses for display data from DRAM.

CR T Interface

The CRT Interface aligns CRT signals to the Pixel

Clock and gen erates the I /O Contro l signa ls for CPU

access to the RAMDAC.

Address Generator

The Address Generator takes the display and refresh

addresses from the CRT Controller and converts

them into RAS and CAS addresses for the display

DRAM, and multiplexes these display accesses with

CPU memory accesses.

Attributes Controller

The Attributes Controller takes in pixel and attribute

information from the Graphics Controller and display

DRAM and formats the data into pixel information

which then passes through the lookup table. It also

controls display character attributes such as blink,

underline and horizontal pixel panning.

Graphics Controller

The Graphics Controller supplies display memory

data to the Attributes Controller during display time

and provides data translation between the CPU bus

and the display memory during CPU read or write

access cycles.

Display Memory Interface

The Display Memory Interface is a bridge by which

the chip communicates with the DRAM. It contains

buffers tha t are use d to store r ecently fetched DRAM

data.

Memory Decoder

The Memor y Decode r monitors the CP U-bus a ctivity

and decodes cycles for the displa y DRAM. It supplies

memory access control signals to the Sequencer.

Port Decoder

The Port Decoder decodes CPU-bus I/O cycles to

provide enable and write strobes for the on-chip I/O

registers.

Auxiliary P orts

The Auxiliary Ports are I/O registers used to control

functions of the chip beyond the basic VGA register

set. Registers are included for controlling the LCD

interface circuits as well as the power save modes.

VGA Ports

The VGA Ports contain the Miscellaneous Output

Status register and the Video Subsystem Enable reg-

ister used in VGA mode.

Clock Generation

The Clock Generation contains oscillator support for

external crystals.

Power Save

Power Save con tains the log ic to impl ement six soft-

ware controlled and one hardware controlled power

down modes.

Lookup Table

The Lookup Table co nsists of a mem or y array of 256

locations of 12 bits each and hardware to convert

VGA palette writes to gray-scale values.

LCD Interface

The LCD Interface converts the display video data

from the L ookup Table into LCD display data. It also

generates control signals necessary to drive single or

dual-panel LCD panels. For monochrome LCD pan-

els, the LCD Interf ace generates a maximum 64 gray

shades through frame rate modulation and dithering

techniqu es. Fo r color LCD panels, th e LCD Inter fac e

generates 256 simultaneous colors from a possible

4096 colors through frame rate modulation.

Hardware Cursor

The Hardware Cursor generates a 4 gray shade or

color cursor/sprite that can be overlaid on the LCD or

CRT display. The cursor is 64 x 64 pixels or optionally

expanded to 128 x 128 through pixel replication.

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SPC8106F0C

X12-DS-001-09 7

■DC SPECIFICATIONS

Absolute Maximum Ratings

Recommended Operating Conditions

Input Specifications

Symbol Parameter Rating Units

VDD Supply Voltage VSS-0.3 to +7.0 V

VIN Input Voltage VSS-0.3 to VDD+0.3 V

VOUT Output Vol tag e VSS-0.3 to VDD+0.3 V

TOPR Operating Temperature 0 to +70 °C

TSTG Storage Temperature -65 to +150 °C

TSOL Soldering Temperature/Time 260 for 10sec max at lead °C

Symbol Parameter Condition Min Typ Max Units

HVDD Supply Voltage VSS = 0V 4.5 5.0 5.5 V

LVDD Supply Voltage VSS = 0V 3.0 3.3 3.6 V

VIN Input Voltage VSS VSS -- VDD V

TOPR Operating Temperature 02570°C

OPR Average Current Consumption Vcc Cor e = 3.3V

VCC I/O = 5.0V typical ICore = 52.31

typical IIO = 13.85 mA

Symbol Parameter Condition Min Typ Max Units

VIL Low Level Input Voltage

(CMOS inputs) VDD = MIN 1.0 V

VIH High Level Input Voltage

(CMOS inputs) VDD = MAX 3.5 V

VIL Low Level Input Voltage

(TTL inputs) VDD = MIN 0.8 V

VIH High Level Input Voltage

(TTL inputs) VDD = MAX 2.0 V

VT+ Positive-going Threshold

(CMOS Schmitt inputs) VDD = 5.0 4.0 V

VT- Negative-going Threshold

(CMOS Schmitt inputs) VDD = 5.0 0.8 V

VHHysteresis Voltage

(CMOS Schmitt inputs) VDD = 5.0 0.3 V

VT+ Positive-going Threshold

(TTL Schmitt inputs) VDD = 5.0 3.0 V

VT- Negative-going Threshold

(TTL Schmitt inputs) VDD = 5.0 0.6 V

VHHysteresis Voltage

(TTL Schmitt inputs) VDD = 5.0 0.1 V

IIZ Input Leakage Current VDD = MAX

VIH = VDD

VIL = VSS

-1 1 µA

CIN Input Pin Capacitance 8pF

PU2 Pull Up Resistance VDD = 5.0 V 50 100 200 kΩ

RPU3 Pull Up Resistance VDD = 5.0 V 100 200 400 kΩ

RPD Pull Down Resistance VDD = 5.0 V 100 200 400 kΩ

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SPC8106F0C

X12-DS-001-09

Output Specifi cations

Symbol Parameter Condition Min Typ Max Units

IOL2 Low Level Output

Current VOL=VSS+0.4V

TS2 6.0 mA

IOH2 High Level Output

Current VOH=VDD-0.4V

TS2 -2.0 mA

IOL3 Low Level Output

Current VOL=VSS+0.4V

TS3 12.0 mA

IOH3 High Level Output

Current VOH=VDD-0.4V

TS3 -4.0 mA

IOL4 Low Level Output

Current VOL=VSS+0.4V

TS4 24.0 mA

IOH4 High Level Output

Current VOH=VDD-0.4V

TS4 -8.0 mA

IOZ Output Leakage Current VOH=VDD

or VOL=VSS -1 1 µA

COUT Output Pin Capacitance 8 pF

CBID Bidirectional Pin

Capacitance 10 pF

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SPC8106F0C

X12-DS-001-09 9

■SPC8106 PIN OUT

COREVDD

A10

A11

A12

A13

A14

A15

A16

IOVSS

IOVDD

D10

D11

D12

D13

D14

D15

RESET

READY

PDCLK

IOVSS

MA5

OL1

OL0

D477

HSYNC#

MD9

MA7

IOVSS

MS0

MD5

MD11

MD10

MD6

MD7

MD8

LCAS#

WE#

UCAS#

RAS#

MA8

MA0

MA1

MA6

MA3

IOVDD

IOVSS

MA4

IREFEN#

RS2

DACWR#

BLANK#

DACRD#

VSYNC#

COREVDD

MD4

MA2

LA17

LA18

LA19

LA20

IOVDD

LA21

LA22

LA23

XSCL2

VSS

XSCL

COREVDD

LD0

LD1

MA9

LCDPWR#

UD0

UD1

LD2

LD3

UD2

UD3

PCLK

OL23

VSS

108

107

106

105

104

103

102

101

100

VSS

IRQ

ALE

BHE#

MEMCS16#

MEMW#

MEMEN

MEMR#

IOW#

IOR#

IOEN#

COREVDD

CLKO1

CLKI1

VSS

CLKO2

CLKI2

COREVDD

SUSPEND#

MS2

MS1

MD0

MD15

MD1

MD14

MD2

MD13

MD3

MD12

IOVDD

IOCS16#

SPC8106F0C

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

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SPC8106F0C

X12-DS-001-09

■PIN DESCRIPTION

Key

CPU Interface

A = Analog I/O = Bidirectional

I = Input P = Power

O = Output

Pin Name Type Pin # Description

A[0:16],

LA[17:23] I104..107,

110..122,

2..4, 5..8

CPU bus address inputs. In Suspend Mode, the Address inputs are internally

masked off. If the value on MD[5] at RESET = 1, then the ALE input pin is used to

internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by

the processor address bus. If the value on MD[5] at RESET = 0, then standard ISA

address timing is assumed, where pins A[0:16], LA[17:23] should be connected to

the ISA bus signals SA[0:16], LA[17:23] respectively.

ALE I 102

ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled. If the

value on MD[5] at RESET = 1, then the ALE input is used to internally latch

LA[19:17] and A[16:2], allowing these address bits to be driven by the processor

address bus. In this mode, the processor ADS# output should be connected to this

pin. If the value on MD[5] at RESET = 0, then standard ISA address timing is

assum ed, and onl y the LA[19:17] inputs are inter na lly latche d.

D[0:15] I/O 125..140 16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles,

and are in a hi-Z state at all other times. In Suspend Mode, these inputs are

internally masked off.

MEMEN I 97 ISA Bus Memory Enable. This signal should be connected to the REFRESH# signal

on the ISA bus. When this signal is low (e.g. during a system memory refresh

cycle), memory address decoding is disabled.

IOR# I 94 ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is disabled.

IOW# I 95 ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is disabled.

MEMR# I 96 ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is

disabled.

MEMW# I 98 ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input is

disabled.

IOEN# I 93 ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal.

When this signal is high, I/O address decoding is disabled. In Suspend Mode, the

IOEN# input is disabled.

READY O 142 ISA Bus READY signal. This output is driven low to force the CPU to insert wait

states during memory cycles. READY is released to high-Z after a transfer is

complete.

RESET I 141 The active high Reset signal from the CPU clears all internal registers and forces all

signals to their inactive state.

IRQ O 103

ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause

this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered

interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A

control bit in the Auxiliary Registers allows this output to be optionally disabled (tri-

stated). This pin also is used for the output of the NAND tree in pin test mode.

MEMCS16# O 99 ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive

this output low when a valid memory address (AXXXXh, BXXXXH) appears on the

bus.

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SPC8106F0C

X12-DS-001-09 11

Video Memory Interface

Clock Inputs

IOCS16# O 100

ISA Bus I/O Chip Select 16. Address inputs A[15:0] and IOEN# are decoded to

drive this output low when a valid SPC8106F0C I/O register address appears on the

bus. Note that I/O addresses 3C6h-3C9h do not result in IOCS16# being driven low

(i.e. RAMDAC and internal LUT register reads and writes are 8 bit cycles).

BHE# I 101 ISA Bus Byte High Enable. In Suspend Mode the BHE# input is disabled.

Pin Name Type Pin # Description

MA[0:9] O

57, 55,

53, 51,

48, 52,

54, 56,

58, 20

Multiplexed row/column address bits for video display memory.

MD[0:15] I/O

81, 79,

77, 75,

70, 68,

66, 64,

63, 65,

67, 69,

74, 76,

78, 80

Data bits for video display memory. The output drivers of these pins are placed into

a high-impedance state when RESET is high, or when the Sequencer is in a reset

state. On the falling edge of RESET, the values on MD[3:0] and MD[12:9] are

latched into a read-only Auxiliary Register and are available to be read as

configuration inputs. Also, the value on MD[8:4] and MD[15:13] are used to

configure various hardware options. See “Summary of Configuration Options” on

page 15 for details.

RAS# O 59 DRAM Row Address Strobe for single 256Kx16 DRAM.

LCAS#

(LWE#) O 62 Multiple Func tio n:

DRAM Column Address Strobe for low byte (LCAS#). For alternate function see

“Multiple Function Pin Descriptions” on page 16.

UCAS#

(CAS#) O60 Multiple Func tio n:

DRAM Column Address Strobe for high byte (UCAS#). For alternate function see

“Multiple Function Pin Descriptions” on page 16.

WE#

(UWE#) O61 Multiple Func tio n:

DRAM Write Enable Strobe (WE#). For alternate function see “Multiple Function

Pin Descriptions” on page 16.

Pin Name Type Pin # Description

CLKI1 I 90 This pin, along with CLKO1 is the 25.175 MHz 2-terminal crystal interface when

using a 2-terminal crystal as the clock input. If an external oscillator is used as a

clock source, then this pin is the clock input.

CLKO1 O 91 This pin, along with CLKI1 is the 25.175 MHz 2-terminal crystal interface when

using a 2-terminal crystal as the clock input. If an external oscillator is used as a

clock source, then this pin should be left unconnected.

CLKI2 I 86 This pin, along with CLKO2 is the 28.322 MHz 2-terminal crystal interface when

using a 2-terminal crystal as the clock input. If an external oscillator is used as a

clock source, then this pin is the clock input.

CLKO2 O 87 This pin, along with CLKI2 is the 28.322 MHz 2-terminal crystal interface when

using a 2-terminal crystal as the clock input. If an external oscillator is used as a

clock source, then this pin should be left unconnected.

Pin Name Type Pin # Description

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SPC8106F0C

X12-DS-001-09

LCD P anel Interface

Pin Name Type Pin # Description

YD O 10 Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD

module on the falling edge of LP, is used by the panel row drivers (Y drivers) to

indicate the start of the vertical frame.

LP O 13 Latch Pulse output. The falling edge of this signal is used to latch a row of display

data in the LCD module’s column driver shift registers and to turn on the row driver

(Y driver) for that line.

XSCL O 12 Shift Clock for LCD data. Display data is clocked out of the chip on the rising edge

of this signal, to be shifted into the LCD panel module column drivers (X drivers)

on each falling edge.

XSCL2 O 9 This second shift clock is used together with XSCL in 8-bit single color panel mode

to shift in alternate sets of display data. XSCL2 is also used alone as the shift clock

in 8-bit dual color panel mode and 4-bit single color panel mode.

UD[0:3] O 22..25

Upper panel display data for dual panel - dual drive mode. For 8-bit single panel-

single drive mode, these bits are the most significant 4-bits of the 8-bit output data

to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4 bits of

data output to the panel. For 16-bit LCD modes, these outputs are the multiplexed

upper panel data if MD[7]=1 at RESET, or the lower nibble of the upper panel data

if MD[7]=0 at RESET.

UD[4:7] O 26..29 When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode

upper panel data.

LD[0:3] O 16..19

Lower panel display data for dual panel-dual drive mode. For 8-bit single panel-

single drive mode, these bits are the least significant 4 bits of the 8-bit output data

to the panel (data[3:0]). For 4-bit single panel mode, these outputs are driven low.

For 16-bit LCD modes, these outputs are the multiplexed lower panel data if

MD[7]=1 at RESET, or the lower nibble of the lower panel data if MD[7]=0 at

RESET.

LD[4:7] O 30..33 When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode

lower panel data.

LCDPWR# O 21

LCD power control. In normal operation this signal is driven low to enable an

external LCD power supply. This signal is driven high when the chip is put into any

power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the

Sequencer is in a reset state. It can be used externally to turn off the panel supply

voltage and backlight. After a RESET, this signal is held high until the CRTC is

programmed and running.

WF O 15 LCD Backplane Bias signal. This output toggles once every n LP periods, as

programmed in Auxiliary Register [0D].

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External CRT/RAMDAC Interface

Pin Name Type Pin # Description

P[0:7] O 26..33 When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits are

connected to the pixel select inputs of the external RAMDAC.

PCLK O 34 Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK.

BLANK# O 44 Blank output. This output is clocked out on the falling edge of PCLK and is driven

low during display blanking periods.

HSYNC# O 41 Horizontal Sync. This output is clocked out on the falling edge of PCLK and is

driven to indicate the horizontal retrace period. The polarity of this signal is

determined by a control bit in register 3C2h.

VSYNC# O 42 Vertical Sync. This output is clocked out on the falling edge of PCLK and is driven

to indicate the vertical retrace period. The polarity of this signal is determined by a

control bit in register 3C2h.

DACRD# O 43 RAMDAC Read Strobe. This signal goes low when a valid read access to the VGA

RAMDAC is decoded by the chip.

DACWR# O 45 RAMDAC Write Strobe. This signal goes low when a valid write access to the VGA

RAMDAC is decoded by the chip.

RS2 O 46

RAMDAC (Bt477 or equivalent). The logic level on this output may be set by

setting Auxiliary Register [0B] bit 3. This signal is required to allow CPU access the

control and overlay registers of the external RAMDAC.

OL[0:1] I/O 39, 38

Multiple Function:

Overlay Select ou tputs 1:0

When MD[13]=0 at RESET, these pins are outputs used to provide sprite/HW

cursor function on the CRT display. In this case, these outputs should be

connected to the OL[0:1] inputs of the RAMDAC (Bt477 or equivalent). They are

used by the sprite circuitry to access the overlay registers in the RAMDAC. For

alternate function see “Multiple Function Pin Descriptions” on page 16.

OL23 O 35

Overlay Select output 2/3. This output should be connected to both the OL2 and

OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the sprite

circuitry to access the overlay registers in the RAMDAC. For alternate function see

“Multiple Function Pin Descriptions” on page 16.

D477 O 40

477 Control Signal. This output should be connected to the 477/471 input of the

RAMDAC (Bt477 or equivalent). This signal is used to access the control register

of the RAMDAC and to allow it to be powered down. The logic level on this output

can be controlled by setting Auxiliary Register [0B] bit 4, and is also controlled by

the power save logic .

IREFEN# O 47

IREF Enable output. This signal is used to control the external current reference

source required by the RAMDAC, allowing powering down the analog circuitry

when not required. When this signal is driven low, the external current reference

should be enabled. When this signal is high, the external current reference should

be shut off.

GRAPHICS

SPC8106F0C

X12-DS-001-09

Power Save Mode Control

Power Supply

MS[2:0] I/O 83, 82, 71

Monitor Sense inputs. These signals should be connected to the monitor sense

lines from the CRT monitor cable. The status of these bits is readable in Auxiliary

and type of monitor connected. Optionally, the SENSE output of the RAMDAC

may be connected to one of these inputs to allow the BIOS to read the SENSE

signal and detect the monitor. MS[2:1] can be forced low by the DCC2 monitor

support bits in Auxiliary Register [10] bits 1:0.

Pin Name Type Pin # Description

SUSPEND# I 84

A low level on this pin puts the ch ip into a hardware power down mode. The

SUSPEND# signal overrides any software initiated power down modes, and

disables the ISA-Bus interface inputs except RESET. Address and Data inputs are

also masked when this signal is low. When in Suspend Mode the UD(3:0), LD(3:0),

XSCL, XSCL2, LP, YD and WF signals are driven into a high impedance or low

state (configurable) and the LCDPWR# signal is driven high.

PDCLK I 143

Power Down Clock. This input may be used to provide a low frequency clock for

generating refresh in Power Save Modes 4 and Suspend, as an optional

alternative to using the pixel clock or MEMEN input as the refresh clock source.

This clock input should be driven by either by a 32 kHz 50% duty cycle clock

source, or a 64 kHz clock source with a high period as short as possible (but >

minimum RAS low pulse width) to minimize DRAM current consumption during

refresh. The PDCLK input is used to directly generate the RAS and CAS pulses

during Power Sav e Mod e 4 and Suspend.

Pin Name Type Pin # Description

COREVDD P 14, 37,

85, 92,

109 VDD supply for core logic.

IOVDD P 1, 50, 73,

124 VDD supply for interface pins.

VSS P 11, 36,

88, 89,

108 VSS supply for core logic.

IOVSS P 49, 72,

123, 144 VSS supply for interface pins.

Pin Name Type Pin # Description

GRAPHICS

SPC8106F0C

X12-DS-001-09 15

Pin Mapping for Various Display Modes

Mixed Voltage Configurations

Summary of Configuration Options

These inputs have internal pull-up resistors. Based on the value of the internal pull-ups, the external pull-down

resistors if necessary, should be approximately 15K ohm. This value will provide the correct voltage levels on

power-up without loading the DRAM Data lines (VDD = 5.0V).

SPC8106

Pin Name

Display Mode

RGBI 12-bit RGB

TFT

CRT LCD 9-bit 12-bit

AUX[00]b5=1

AUX[0B]b1=0

12-bit

AUX[00]b5=1

AUX[0B]b1=1

VSYNC# VSYNC# None None None None None VSYNC#

HSYNC# HSYNC# None None None None None HSYNC#

YD None YD VSYNC# VSYNC# VSYNC# VSYNC# None

LP None LP HSYNC# HSYNC# HSYNC# HSYNC# None

WF None WF None (forced 0) None (forced 0) DATAEN DATAEN DATAEN

XCSL None XCSL PCLK PCLK PANCLK PANCLK PANCLK

XCSL2 None XCSL2 None (forced 0) R[3] R[2] R[3] R[3]

UD[3] None UD[3] None (forced 0) B[3] B[2] B[3] B[3]

UD[2] None UD[2] None (forced 0) B[2] B[1] B[2] B[2]

UD[1] None UD[1] None (forced 0) B[1] B[0] B[1] B[1]

UD[0] None UD[0] None (forced 0) R[2] R[1] R[2] R[2]

LD[3] None LD[3] D[3] G[3] G[2] G[3] G[3]

LD[2] None LD[2] D[2] G[2] G[1] G[2] G[2]

LD[1] None LD[1] D[1] G[1] G[0] G[1] G[1]

LD[0] None LD[0] D[0] R[1] R[0] R[1] R[1]

OL0 OL0 None None B[0] None B[0] B[0]

OL1 OL1 None None G[0] None G[0] G[0]

OL23 OL23 None None R[0] None R[0] R[0]

Core VDD I/O VDD

3.3 V 5.0 V

3.3 V OK OK

5.0 V NO OK

Pin Name value on this pin at falling edge of RESET is used to configure: (1/0)

MD[3:0] values latched into read-only Aux Reg[0C] bits 3:0 for software use

MD[4] 16-bit I/O interface (1) / 8-bit I/O interface (0)

MD[5] A[19:2] latched internally by ALE (1) / standard ISA bus ALE - A[16:0] not latched (0)

MD[6] 2 CAS, 1 WE type DRAM (1) / 1 CAS, 2 WE type DRAM (0)

MD[7] support 16-bit panel with external logic (1) / support 16-bit panel directly (0)

MD[8] 5 V core operating voltage (1) / 3.3 V core operating voltage (0)

MD[12:9] values latched into read-only bits 7:4 of Aux Reg[0C] for software use

MD[13] pins 38, 39 used for ext. RC for 32 kHz PDCLK (1) / pins 38, 39 used for OL[1:0] (0)

MD[14] Internal PDCLK doubling disable (1) / enable (0)

MD[15] 3C3h used as video enable port (1) / 46E8h and 102h used as video enable port (0)

GRAPHICS

SPC8106F0C

X12-DS-001-09

Multiple Function Pin Descriptions

Pin Name Function MD Line Status Functional Description

LCAS #, LWE # LCAS# MD6 = 1 DRAM Column Address Strobe

(Low Byte).

LWE# MD6 = 0 DRAM Write Strobe (Low Byte).

UCAS#, CAS# UCAS# MD6 = 1 DRAM Column Address Strobe

(High Byte).

CAS# MD6 = 0 DRAM Column Address Strobe.

WE#, U WE# WE# MD[6] = 1 DRAM Write Strobe.

UWE# MD[6] = 0 DRAM Write Strobe

(High Byte).

OL0, P320, B0

OL0 MD[13] = 0

AUX[00] b6=0 Overlay Bit 0. Used for CRT HW

Cursor/Sp r ite su ppo rt.

P320 MD[13] = 1

MD[14] = 1

32 kHz Clock Output. Used with

external RC when using external

PDCLK support.

B0 MD[13] = 0

AUX[00] b6=1 Data bit B0 for 12-bit TFT support.

OL1, P3 2I, G0

OL1 MD[13] = 0

AUX[00] b6=0 Overlay Bit 1. Used for CRT HW

Cursor/Sp r ite su ppo rt.

P32I MD[13] = 1

MD[14] = 1

32 kHz Clock Input. Used with

external RC when using external

PDCLK support.

G0 MD[13] = 0

AUX[00] b6=1 Data bit G0 for 12-bit TFT support.

OL23, R0 OL23 MD[13] = 0

AUX[00] b6=0 Overlay Bit 2. Used for CRT HW

Cursor/Sp r ite su ppo rt.

R0 MD[13] = 0

AUX[00] b6=1 Data bit R0 for 12-bit TFT support.

P[0:3] P[0:3} MD[7] = 1 Lower nibble of the CRT pixel data

outputs.

UD[4:7} MD[7] = 0 Upper nibble of the 16-bit LCD

mode upper panel data.

P[4:7] P[4:7] MD[7] = 1 Upper nibble of the CRT pixel data

outputs.

LD[4:7] MD[7] = 0 Upper nibble of the 16-bit LCD

mode lower panel data.

GRAPHICS

SPC8106F0C

X12-DS-001-09 17

Illustrated below are the display data output which are output from the UD0 to UD3, LD0/UD4 to

LD3/UD7 and the display on the panel:

■LCD PANEL PIXELS

8-bit Single Panel

UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0

4-bit Single Panel

UD3 UD2 UD1 UD0

LD3LD2LD1LD0

Dual Panel - Top

Dual Panel - Bottom

1-1 1-2

2-22-1

240-1 240-2

241-1 241-2

240-639

1-639 241-640

240 - 640

1-639

2-639 2-640

1-640

480-1 480-2 480-639 480-640

UPPER LCD PANEL

(TOP VIEW)

LOWER LCD PANEL

640 DOTS

240 LINES

GRAPHICS

SPC8106F0C

X12-DS-001-09

■MONOCHROME PASSIVE STN LCD PANEL INTERFACE

4-BIT SINGLE PANEL

LP : 242 PULSES

XSCL

UD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 240

LINE 1 LINE 2

UD2 1-2 1-61-318

UD1 1-3 1-71-319

UD0 1-4 1-81-320

UD3 1-1 1-51-317

XSCL: 80 CLOCK PERIODS

Example timing for a 320 x 240 panel

GRAPHICS

SPC8106F0C

X12-DS-001-09 19

■MONOCHROME PASSIVE STN LCD PANEL INTERFACE

8-BIT SINGLE PANEL

UD[3:0]

XSCL

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

LP: 482 PULSES

XSCL: 80 CLOCK PERIODS

1-1

LINE 1 LINE 480LINE 2 LINE 3 LINE 4 LIN E 479 LINE 1 LINE 2

1-2

1-3

1-4

1-5

1-6

1-7

1-8

1-9

1-10

1-11

1-12

1-13

1-14

1-15

1-16

1-633

1-634

1-635

1-636

1-637

1-638

1-639

1-640

LD[3:0]

GRAPHICS

SPC8106F0C

X12-DS-001-09

■MONOCHROME PASSIVE STN LCD PANEL INTERFACE

8-BIT DUAL PANEL

UD[3:0]

XSCL

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

LP: 242 PULSES

XSCL: 160 CLOCK PERIODS

1-1

LINE 241 LINE 480LINE 242 LINE 243 LINE 244 LINE 479 LINE 241 LINE 242

1-2

1-3

1-4

241-1

241-2

241-3

241-4

1-5

1-6

1-7

1-8

241-5

241-6

241-7

241-8

1-637

1-638

1-639

1-640

241-637

241-638

241-639

241-640

LD[3:0]

LINE 1 LINE 240LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 2

GRAPHICS

SPC8106F0C

X12-DS-001-09 21

■COLOR STN LCD PANEL INTERFACE

4-BIT SINGLE PANEL

LP : 242 PULSES

XSCL2

UD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 240

LINE 1 LINE 2

UD2 G1 B2 R320

UD1 B1 R3 G320

UD0 R2 G3 B320

UD3 R1 G2 B319

XSCL2: 240 CLOCK PERIODS

Example timing for a 320 x 240 panel

GRAPHICS

SPC8106F0C

X12-DS-001-09

■COLOR STN LCD PANEL INTERFACE

8-BIT SINGLE PANEL

UD[3:0]

XSCL2

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

LP: 482 PULSES

XSCL: 120 CLOCK PERIODS

LINE 1 LINE 480LINE 2 LINE 3 LINE 4 LIN E 479 LINE 1 LINE 2

1-G1

1-R2

1-B2

1-G3

1-R4

1-B4

1-G5

1-R6

1-R636

1-B636

1-G637

1-R638

1-B638

1-G639

1-R640

1-B640

LD[3:0]

1-G6

1-R7

1-B7

1-G8

1-R9

1-B9

1-G10

1-R11

1-R12

1-B12

1-G13

1-R14

1-B14

1-G15

1-R16

1-B16

1-B6

1-G7

1-R8

1-B8

1-G9

1-R10

1-B10

1-G11

1-B11

1-G12

1-R13

1-B13

1-G14

1-R15

1-B15

1-G16

1-B635

1-G636

1-R637

1-B637

1-G638

1-R639

1-B639

1-G640

1-R1

1-B1

1-G2

1-R3

1-B3

1-G4

1-R5

1-B5

XSCL2: 120 CLOCK PERIODS

XSCL

GRAPHICS

SPC8106F0C

X12-DS-001-09 23

■COLOR STN LCD PANEL INTERFACE

8-BIT DUAL PANEL

UD[3:0]

XSCL2

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

LP: 242 PULSES

XSCL2: 480 CLOCK PERIODS

241-R1

LINE 241 LINE 480LINE 242 LINE 243 LINE 244 LINE 479 LINE 241 LINE 242

241-G1

241-B1

241-R2

241-B3

241-R4

241-G4

241-B4

LD[3:0]

LINE 1 LINE 240LINE 2 LINE 3 L I NE 4 LINE 239 LINE 1 LINE 2

241-G2

241-B2

241-R3

241-G3

1-R637

1-G637

1-B637

1-R638

1-B639

1-R640

1-G640

1-B640

1-G638

1-B638

1-R639

1-G639

1-R1

1-G1

1-B1

1-R2

1-B3

1-R4

1-G4

1-B4

1-G2

1-B2

1-R3

1-G3

241-R637

241-G637

241-B637

241-R638

241-B639

241-R640

241-G640

241-B640

241-G638

241-B638

241-R639

241-G639

GRAPHICS

SPC8106F0C

X12-DS-001-09

■COLOR STN LCD PANEL INTERFACE

16-BIT SINGLE PANEL

UD[7:0]

XSCL

UD7

UD6

UD5

UD3

UD2

UD1

UD0

LP: 482 PULSES

XSCL: 120 CLOCK PERIODS

1-R1

LINE 1 LINE 480LINE 2 LINE 3 LINE 4 LIN E 479 LINE 1 LINE 2

1-B1

1-G2

1-R3

1-B3

1-G4

1-R5

1-B5

1-G6

1-R7

1-B7

1-G8

1-R9

1-B9

1-G10

1-R11

LD[7:0]

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

1-G1

1-R2

1-B2

1-G3

1-R4

1-B4

1-G5

1-R6

1-B6

1-G7

1-R8

1-B8

1-G9

1-R10

1-B10

1-G11

1-B11

1-G12

1-R13

1-B13

1-G14

1-R15

1-B15

1-G16

1-R12

1-B12

1-G13

1-R14

1-B14

1-G15

1-R16

1-B16

1-R625

1-B625

1-G626

1-R627

1-B627

1-G628

1-R629

1-B629

1-G630

1-R631

1-B631

1-G632

1-R633

1-B633

1-G634

1-R635

1-G625

1-R626

1-B626

1-G627

1-R628

1-B628

1-G629

1-R630

1-B630

1-G631

1-R632

1-B632

1-G633

1-R634

1-B634

1-G635

1-B635

1-G636

1-R637

1-B637

1-G638

1-R639

1-B639

1-G640

1-R636

1-B636

1-G637

1-R638

1-B638

1-G639

1-R640

1-B640

GRAPHICS

SPC8106F0C

X12-DS-001-09 25

■COLOR STN LCD PANEL INTERFACE

16-BIT DUAL PANEL

UD[7:0]

XSCL

UD7

UD6

UD5

UD4

UD3

UD2

UD1

UD0

LP: 242 PULSES

XSCL: 240 CLOCK PERIODS

241-R1

LINE 241 LINE 480LINE 242 LINE 243 LINE 244 LINE 479 LINE 241 LINE 242

241-G1

241-B1

241-R2

241-G6

241-B6

241-R7

241-G7

LD[7:0]

LINE 1 LINE 240LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 2

241-B3

241-R4

241-G4

241-B4

1-R633

1-G633

1-B633

1-R634

1-G638

1-B638

1-R639

1-G639

1-B635

1-R636

1-G636

1-B636

1-R1

1-G1

1-B1

1-R2

1-G6

1-B6

1-R7

1-G7

1-B3

1-R4

1-G4

1-B4

241-R633

241-G633

241-B633

241-R634

241-G638

241-B638

241-R639

241-G639

241-B635

241-R636

241-G636

241-B636

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

241-G2

241-B2

241-R3

241-G3

241-B7

241-R8

241-G8

241-B8

241-R5

241-G5

241-B5

241-R6

1-G634

1-B634

1-R635

1-G635

1-B639

1-R640

1-G640

1-B640

1-R637

1-G637

1-B637

1-R638

1-G2

1-B2

1-R3

1-G3

1-B7

1-R8

1-G8

1-B8

1-R5

1-G5

1-B5

1-R6

241-G634

241-B634

241-R635

241-G635

241-B639

241-R640

241-G640

241-B640

241-R637

241-G637

241-B637

241-R638

GRAPHICS

SPC8106F0C

X12-DS-001-09

■COLOR STN LCD PANEL INTERFACE

16-BIT SINGLE PANEL WITH EXTERNAL CIRCUIT

LP : 482 PULSES

XSCL

Pixel Data LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480

LINE 1 LINE 2

UD2

UD1

UD0

UD3

XSCL: 120 CLOCKS

1-R1 1-B3

1-B1 1-G4

1-G2 1-R5

1-R3 1-B5

UD6

UD5

UD4

UD7

LD3

LD2

LD1

LD0

1-G1 1-R4

1-R2 1-B4

1-B2 1-G5

1-G3 1-R6

SPC8106 OUTPUTS

LD6

LD5

LD4

LD7

1-B3

1-G4

1-R5

1-B5

UD3

UD2

UD1

UD0

1-R4

1-B4

1-G5

1-R6

LD3

LD2

LD1

LD0

16-bit PANEL INPUTS

1-R1

1-B1

1-G2

1-R3

1-B635

1-G636

1-R637

1-B637

1-B638

1-G639

1-R640

1-B640

1-G638

1-R639

1-B639

1-G640

1-G1

1-R2

1-B2

1-G3

1-R636

1-B636

1-G637

1-R638

1-G638

1-R639

1-B639

1-G640

1-B638

1-G639

1-R640

1-B640

1-R636

1-B636

1-G637

1-R638

1-B635

1-G636

1-R637

1-B637

UD[3:0]

LD[3:0]

XSCL

UD[3:0]

LD[3:0]

UD[7:4]

LD[7:4]

TO 16-BIT

PANEL

FROM

SPC8106

EXTERNAL CIRCUIT

(required when MD[7]=1

at re set)

GRAPHICS

SPC8106F0C

X12-DS-001-09 27

■COLOR STN LCD PANEL INTERFACE

16-BIT DUAL PANEL WITH EXTERNAL CIRCUIT

LP : 242 PULSES

XSCL

Pixel Data LINE 1/241

UD2

UD1

UD0

UD3

XSCL: 240 CLOCKS

1-R1 1-B3

1-G1 1-B2

1-B1 1-R3

1-R2 1-G3

UD6

UD5

UD4

UD7

LD3

LD2

LD1

LD0

241-R1

SPC8106 OUTPUTS

LD6

LD5

LD4

LD7

1-G2

1-B2

1-R3

1-G3

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

16-BIT PANEL INPUTS

1-R1

1-G1

1-B1

1-R2

1-G638

1-B638

1-R639

1-G639

241-

B639

1-B639

1-R640

1-G640

1-B640

241-R1 241-G638

1-B639

1-R640

1-G640

1-B640

241-

B639

1-G2

1-R4

1-G4

1-B4

1-G638

1-B638

1-R639

1-G639

241-G2 241-B3

241-G1 241-B2 241-R4

241-B1 241-R3 241-B4

241-R2 241-G3 241-B4

241-

G638

241-

R640

241-

B638

241-

G640

241-

R639

241-

B640

241-

G639

241-G1

241-B1

241-R2

241-G2

241-B2

241-R3

241-G3

241-B638

241-R639

241-G639

241-

R640

241-

G640

241-

B640

LINE 2/242 LI NE 3/243 LINE 4/244 L I N E 239 / 479 LINE 240/480 LINE 1/241 LINE 2/242

UD[3:0]

LD[3:0]

XSCL

UD[3:0]

LD[3:0]

UD[7:4]

LD[7:4]

TO 16-BIT

PANEL

FROM

SPC8106

EXTERNAL CIRCUIT

(required when MD[7]=1

at re set)

GRAPHICS

SPC8106F0C

X12-DS-001-09

■COLOR TFT PANEL INTERFACE

Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=1

R[3:0], G[3:0], B[3:0]* LINE 1 LINE 350

VSYNC#*

HSYNC#*

350 Line Mode

LINE 1 LINE40

INE 1 LINE48

-1

1-1

1-640

HSYNC#* (400, 480)

HSYNC#* (350)

PANCLK*

DATAEN*

R[3:0] *

HRTC 350 PULSES

HRTC 400 PULSES

HRTC 480 PULSES

CLOCK: 640 CLOCKS

G[3:0] *

B[3:0] *

1-2

1-1

61 HRTC PULSES

34 HRTC

PULSES

34 HRTC PULSES

R[3:0], G[3:0], B[3:0]*

VSYNC#*

HSYNC#*

VSYNC#*

HSYNC#*

400 Line Mode

480 Line Mode

9-bit panels use data bits [2:0]

* Refer to “Pin Mapping for Various Display Modes” on page 15 for actual pin names

GRAPHICS

SPC8106F0C

X12-DS-001-09 29

■COLOR TFT PANEL INTERFACE

Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=0

LINE 1 LINE48

1-1

1-640

HSYNC#*2

PANCLK*2

DATAEN*2

R[3:0]*2

UP TO 1023 HRTC PULSES

CLOCK: 640 CLOCKS

G[3:0]*2

B[3:0]*2

1-2

1-1

2~65 HRTC PULSES

R[3:0], G[3:0], B[3:0]*2

VSYNC#*2

HSYNC#*2

112 OR 160

CLOCKS

2-1

2-2

2-1

9-bit panels use data bits [2:0]

1-3

1-4

1-3

*1 - This number is controlled by Auxiliary Register [06] bit 2

*2 - Refer to “Pin Mapping for Various Display Modes” on page 15 for actual pin names

GRAPHICS

SPC8106F0C

X12-DS-001-09

■RGB MODE PANEL INTERFACE

■RGBI MODE DUAL P ANEL INTERFACE

12-BIT RGB MODE PANEL HSYNC: 240 PULSES

HSYNC#*

PCLK*

R[3:0], G[3:0], B[3:0]* LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480

VSYNC#*

LINE 1/241 LINE 2/242

HSYNC#*

R[3:0]* 1-1 241-1 241-640

PCLK : 1280 CLOCKS

2 PULSES

PCLK : 224 CLOCKS

1-2241-21-640

-1 241-1 241-640

1-2241-21-640

1-1 241-1 241-640

1-2241-21-640

2-1 242-1 2-2

2-1

242-1

2-2

G[3:0]*

B[3:0]*

HSYNC:

* Refer to “Pin Mapping for Various Display Modes” on page 15 for actual pin names

RGBI MODE DUAL PANEL

2-1

HSYNC: 240 PULSES

HSYNC#*

PCLK*

I, R, G, B* LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480

VSYNC#*

LINE 1/241 LINE 2/242

HSYNC#*

I, R,G, B* 1-1 241-1 241-640

PCLK : 1280 CLOCKS

2 PULSES

PCLK : 224 CLOCKS

1-2 241-2 1-640242-1 2-2

HSYNC:

* Refer to “Pin Mapping for Various Display Modes” on page 15 for actual pin names

GRAPHICS

SPC8106F0C

X12-DS-001-09 31

■PACKAGE DIMENSIONS

Actual Size

QFP17 - 144 pin Unit: mm

136

±0.1

0.5 0.2±0.1

0~10°

1.0

108 73

109

144

20.0±0.1

Index

3.0 Max

0.1

22.0±0.4

0.5±0.2

20.0 ±0.1

22.0±0.4

0.15 ±0.05

GRAPHICS

SPC8106F0C

X12-DS-001-09

■COMPREHENSIVE SUPPORT TOOLS

Seiko Epson provides the designer and manufacturer a complete set of resources and tools for the development of

LCD Graphics Systems.

Documentation

•Technical manua ls

•Evaluation/Demonstration b oard manual

Evaluation/Demonstration Board

•Assembled and fully tested Graphics Evaluation/Demonstration board

•Schematic of Evaluation/Demonstration board

•Parts List

•Installation Guide

•CPU Independent Software Utilities

•Eval uation Software

•Windows CE Display Driver

■Application Engine ering Support

Seiko Epson offers the following services through their Sales and Marketing Network:

•Sales Technical Support

•Customer Training

•Design Assistance

FOR SYSTEM INTEGRATION SERVICES

FOR WINDOWS® CE CONTACT:

Epson Research & Development, Inc.

Suite #320 - 11120 Horseshoe Way

Richmond, B.C., Canada V7A 5H7

Tel: (604) 275-5151

Fax: (604) 275-2167

Email: wince@erd.epson.com

http://www.erd.epson.com

CONTACT YOUR SALES REPRESENTATIVE FOR THESE

COMPREHENSIVE DESIGN TOOLS:

• S PC8106C Technical Manual

• S DU8106C Evaluation Boards

• Windows CE Display Driver

• CPU Independent Software Utilit ies

Japan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Fax: 042-587-5564

http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 2827-4346

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan, R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Singapore

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Europe

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

North America

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.eea.epson.com

Information in thi s docum ent is subject to change witho ut notice. You may downloa d and use this docume nt, but o nly for your own use in evalu ating S eiko E pson/

EPSON produ cts. Y ou ma y no t m odify the docu ment. E pson Resea rch and Develo pment, Inc. disclaims any r epr esenta ti on that the con t ents of this document are

accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.

EPSON is a registered tradema rk of Seiko Epson Corporation. Microso ft, Windows, and the Windows CE Logo are registered tra demarks of M icrosoft C orporati on.