Nonreflective, 9 kHz to 44 GHz Silicon SP4T Switch ADRF5043 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM GND RF1 GND GND 24 23 22 21 20 GND 18 RF2 17 GND 4 16 GND GND 5 15 GND VSS 6 14 RF3 LS 7 13 GND 3 RFC 50 50 50 50 8 9 10 11 12 GND GND GND 2 RF4 V1 GND 1 DRIVER 19 EN 23794-001 V2 ADRF5043 VDD Ultrawideband frequency range: 9 kHz to 44 GHz Nonreflective 50 design Low insertion loss 1.5 dB up to 18 GHz 2.4 dB up to 40 GHz 2.5 dB up to 44 GHz High isolation 44 dB up to 18 GHz 39 dB up to 40 GHz 36 dB up to 44 GHz High input linearity P0.1dB: 26 dBm typical IP3: 48 dBm typical High power handling 24 dBm through path 24 dBm terminated path All off state control Logic select control No low frequency spurs Settling time (0.1 dB final RF output): 6 s 24-terminal, 3 mm x 3 mm LGA package Pin compatible with ADRF5042, fast switching version Figure 1. APPLICATIONS Industrial scanners Test instrumentation Cellular infrastructure--millimeterwave (mmWave) 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5043 is a nonreflective, SP4T switch manufactured in the silicon on insulator (SOI) process. The ADRF5043 has enable and logic select controls to feature all off state and port mirroring, respectively. The ADRF5043 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.5 dB and an isolation of higher than 36 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths. The ADRF5043 is pin compatible with the ADRF5042 fast switching version, which operates from 100 MHz to 44 GHz. The ADRF5043 requires a dual-supply voltage of +3.3 V and -3.3 V. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls. Rev. 0 The ADRF5043 comes in a 24-terminal, 3 mm x 3 mm, RoHS compliant, land grid array (LGA) package and can operate from -40C to +105C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5043 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Interface Schematics .....................................................................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7 Revision History ............................................................................... 2 Input Power Compression and Third-Order Intercept ............9 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 10 Absolute Maximum Ratings............................................................ 5 Application Information ................................................................ 11 Thermal Resistance ...................................................................... 5 Evaluation Board ........................................................................ 11 Electrostatic Discharge (ESD) Ratings ...................................... 5 Outline Dimensions ....................................................................... 12 Power Derating Curves ................................................................ 5 Ordering Guide .......................................................................... 12 ESD Caution .................................................................................. 5 REVISION HISTORY 7/2020--Revision 0: Initial Version Rev. 0 | Page 2 of 12 Data Sheet ADRF5043 SPECIFICATIONS Positive supply voltage (VDD) = 3.3 V, negative supply voltage (VSS) = -3.3 V, V1 pin voltage (V1) = 0 V or 3.3 V, V2 pin voltage (V2) = 0 V or 3.3 V, LS = 0 V or 3.3 V, EN = 0 V or 3.3 V, and TCASE = 25C on a 50 system, unless otherwise noted. RFx refers to RF1 to RF4. VCTL is the digital control inputs voltage. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RFx (On) Symbol f ISOLATION Between RFC and RFx (Off ) RETURN LOSS RFC and RFx (On) RFx (Off ) SWITCHING Rise and Fall Time On and Off Time Settling Time 0.1 dB 0.05 dB INPUT LINEARITY1 0.1 dB Power Compression 1 dB Power Compression Third-Order Intercept Second-Order Intercept VIDEO FEEDTHROUGH2 SUPPLY CURRENT Positive Supply Current Negative Supply Current DIGITAL CONTROL INPUTS Voltage Low High tRISE, tFALL tON, tOFF P0.1dB P1dB IP3 IP2 Test Conditions/Comments Min 0.009 Typ Max 44,000 Unit MHz 9 kHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 1.5 1.8 2.1 2.4 2.5 dB dB dB dB dB 9 kHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 44 43 40 39 36 dB dB dB dB dB 9 kHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 9 kHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 15 15 14 13 13 23 20 17 15 14 dB dB dB dB dB dB dB dB dB dB 10% to 90% of RF output 50% VCTL to 90% of RF output 1.1 2.8 s s 50% VCTL to 0.1 dB of final RF output 50% VCTL to 0.05 dB of final RF output 6 7.8 s s f = 1 MHz to 40 GHz f = 1 MHz to 40 GHz Two-tone input power = 15 dBm each tone, f = 1 MHz to 40 GHz, f = 1 MHz Two-tone input power = 15 dBm each tone, f = 10 GHz, f = 1 MHz 26 27 48 dBm dBm dBm 120 dBm 3 mV p-p 370 -100 A A VDD, VSS pins IDD ISS V1, V2, EN, LS pins VINL VINH 0 1.2 Rev. 0 | Page 3 of 12 0.8 3.3 V V ADRF5043 Parameter Current Low High RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Inputs Voltage RFx Input Power3 Through Path Data Sheet Symbol Min IINL IINH VDD VSS VCTL PIN Terminated Path Hot Switching Case Temperature Test Conditions/Comments Typ Max 3 6 A A 3.15 -3.45 0 3.45 -3.15 VDD V V V -40 24 24 24 24 24 24 +105 dBm dBm dBm dBm dBm dBm C f = 1 MHz to 44 GHz, TCASE = 85C4 Average Peak Average Peak Average Peak TCASE Unit For input linearity performance over frequency, see Figure 18 to Figure 21. Video feedthrough is the spurious dc transient measured at the RF ports in a 50 test setup, without an RF signal present while switching the control voltage. 3 For power derating over frequency, see Figure 2. 4 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 1 2 Rev. 0 | Page 4 of 12 Data Sheet ADRF5043 ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. ELECTROSTATIC DISCHARGE (ESD) RATINGS Table 2. The following ESD information is provided for handling of ESD sensitive devices in an ESD protected area only. -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD + 0.3 V or 3.3 mA, whichever occurs first 26 dBm 26dBm Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. ESD Ratings for ADRF5043 Table 4. ADRF5043, 24-Terminal LGA ESD Model HBM RFx Pins Supply and Digital Control Pins 2 0 25 dBm 25dBm -2 25 dBm 25dBm 135C -65C to +150C 260C -4 -6 -8 -10 -12 -14 -16 Overvoltages at digital control inputs are clamped by internal diodes. Current must be limited to the maximum rating given. 2 For power derating over frequency, see Figure 2. 3 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. -18 10k ESD CAUTION Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JC is the junction to case bottom (channel to package bottom) thermal resistance. Table 3. Thermal Resistance Unit 468 200 C/W C/W 1M 10M 100M 1G 10G 100G Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C THERMAL RESISTANCE JC1 100k FREQUENCY (Hz) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 1 1000 2000 POWER DERATING CURVES 1 Package Type CC-24-12 Through Path Terminated Path Withstand Threshold (V) 23794-002 RFx Input Power (f2 = 1 MHz to 44 GHz, TCASE = 85C3) Through Path Average Peak Terminated Path Average Peak Hot Switching Average Peak Temperature Junction, TJ Storage Range Reflow Rating POWER DERATING (dB) Parameter Supply Voltage Positive Negative Digital Control Inputs1 JC was determined by simulation under the following conditions: the heat transfer is due solely to thermal conduction from the channel through the ground pad to the PCB, and the ground pad is held constant at the operating temperature of 85C. Rev. 0 | Page 5 of 12 ADRF5043 Data Sheet GND RF1 GND GND 24 23 22 21 20 EN 1 19 GND V1 2 18 RF2 GND 3 17 GND RFC 4 16 GND GND 5 15 GND VSS 6 14 RF3 LS 7 13 GND ADRF5043 8 9 10 11 12 VDD GND RF4 GND GND TOP VIEW (Not to Scale) NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF AND DC GROUND. 23794-004 V2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. 1 2 3, 5, 9, 11 to 13, 15 to 17, 19 to 21, 23 4 Mnemonic EN V1 GND Description Enable Input. See Table 6 for the truth table. See Figure 5 for the interface schematic. Control Input 1. See Table 6 for the truth table. See Figure 5 for the interface schematic. Ground. The GND pins must be connected to the RF and dc ground of the PCB. RFC 6 7 8 10 VSS LS VDD RF4 14 RF3 18 RF2 22 RF1 24 V2 EPAD RF Common Port. RFC is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. Negative Supply Voltage. Logic Select Input. See Table 6 for the truth table. See Figure 5 for the interface schematic. Positive Supply Voltage. RF Throw Port 4. RF4 is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. RF Throw Port 3. RF3 is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. RF Throw Port 2. RF2 is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic. RF Throw Port 1. RF1 is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. Control Input 2. See Table 6 for the truth table. See Figure 5 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF and dc ground. V1, V2, EN, LS 23794-006 RFC, RF1, RF2, RF3, RF4 23794-005 INTERFACE SCHEMATICS Figure 5. V1, V2, EN, and LS Pin Interface Schematic Figure 4. RFC and RF1 to RF4 Pin Interface Schematic Rev. 0 | Page 6 of 12 Data Sheet ADRF5043 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = -3.3 V, VCTL = 0 V or 3.3 V, and TCASE = 25C on a 50 system, unless otherwise noted. Measured on the evaluation board. -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 RF1 RF2 RF3 RF4 -5.0 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) -2.0 -2.5 -3.0 -3.5 -4.0 0 15 20 25 30 35 40 RETURN LOSS FOR RFx OFF (dB) -20 -25 -30 -35 -40 -10 -15 -20 -25 -30 -35 -40 RF1 RF2 RF3 RF4 -45 -45 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) -50 0 0 -10 ISOLATION FOR RFC TO RFx OFF (dB) 0 -20 -30 -40 -50 -60 -70 -80 -100 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 15 20 25 30 35 40 45 50 Figure 8. Isolation for RFC to RFx Off vs. Frequency, RFC to RF1 Path On -20 -30 -40 -50 -60 -70 -80 RF1 RF3 RF4 -90 -100 23794-009 RF2 RF3 RF4 5 10 Figure 10. Return Loss for RFx Off vs. Frequency -10 -90 5 FREQUENCY (GHz) Figure 7. Return Loss for RFC and RFx On vs. Frequency 0 50 -5 -15 0 45 0 -50 ISOLATION FOR RFC to RFx OFF (dB) 10 FREQUENCY (GHz) 23794-008 RETURN LOSS FOR RFC TO RFx ON (dB) -10 5 Figure 9. Insertion Loss for RFC to RF1 On vs. Frequency over Various Temperatures RF1 RF2 RF3 RF4 RFC -5 = +105C = +85C = +25C = -40C -5.0 Figure 6. Insertion Loss for RFC to RFx On vs. Frequency 0 TCASE TCASE TCASE TCASE -4.5 23794-011 -4.5 -1.5 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 23794-012 -4.0 -0.5 -1.0 23794-010 INSERTION LOSS FOR RFC TO RF1 ON (dB) 0 23794-007 INSERTION LOSS FOR RFC TO RFx ON (dB) 0 Figure 11. Isolation for RFC to RFx Off vs. Frequency, RFC to RF2 Path On Rev. 0 | Page 7 of 12 Data Sheet 0 -10 -10 -20 -30 -40 -50 -60 -70 -80 RF1 RF2 RF4 -90 -100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) Figure 12. Isolation for RFC to RFx Off vs. Frequency, RFC to RF3 Path On -30 -40 -50 -60 -70 -80 -90 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) Figure 15. Isolation for RFC to RFx Off vs. Frequency, RFC to RF4 Path On 0 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) Figure 13. Channel to Channel Isolation vs. Frequency, RFC to RF1 Path On RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 -20 RF2 RF3 RF4 RF3 RF4 RF4 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (GHz) 23794-017 -10 RF2 RF3 RF4 RF3 RF4 RF4 CHANNEL TO CHANNEL ISOLATION (dB) RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO 23794-014 Figure 16. Channel to Channel Isolation vs. Frequency, RFC to RF2 Path On 0 0 -20 RF2 RF3 RF4 RF3 RF4 RF4 CHANNEL TO CHANNEL ISOLATION (dB) RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 -30 -40 -50 -60 -70 -80 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF3 Path On -20 RF2 RF3 RF4 RF3 RF4 RF4 -30 -40 -50 -60 -70 -80 -90 -100 23794-015 -90 -100 RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 0 5 10 15 20 25 30 FREQUENCY (GHz) 35 40 45 50 23794-018 CHANNEL TO CHANNEL ISOLATION (dB) -20 -100 0 CHANNEL TO CHANNEL ISOLATION (dB) RF1 RF2 RF3 23794-016 ISOLATION FOR RFC TO RFx OFF (dB) 0 23794-013 ISOLATION FOR RFC TO RFx OFF (dB) ADRF5043 Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF4 Path On Rev. 0 | Page 8 of 12 Data Sheet ADRF5043 INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 30 28 28 26 26 24 24 22 20 18 16 14 12 TCASE TCASE TCASE TCASE = +105C = +85C = +25C = -40C 5 10 15 18 16 TCASE TCASE TCASE TCASE 12 20 25 30 35 40 FREQUENCY (GHz) 10 10k 100k 1M 10M = +105C = +85C = +25C = -40C 100M 1G FREQUENCY (Hz) Figure 18. Input P0.1dB vs. Frequency over Various Temperatures Figure 20. Input P0.1dB vs. Frequency, Low Frequency Detail over Various Temperatures 60 55 55 50 50 INPUT IP3 (dBm) 60 45 40 35 30 45 40 35 30 = +105C = +85C = +25C = -40C 5 10 20 0 15 TCASE TCASE TCASE TCASE 25 20 25 30 35 40 FREQUENCY (GHz) Figure 19. Input IP3 vs. Frequency over Various Temperatures 20 10k 100k 1M 10M = +105C = +85C = +25C = -40C 100M FREQUENCY (Hz) Figure 21. Input IP3 vs. Frequency, Low Frequency Detail over Various Temperatures Rev. 0 | Page 9 of 12 1G 23794-022 25 TCASE TCASE TCASE TCASE 23794-020 INPUT IP3 (dBm) 20 14 10 0 22 23794-021 INPUT P0.1dB (dBm) 30 23794-019 INPUT P0.1dB (dBm) VDD = +3.3 V, VSS = -3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25C on a 50 system, unless otherwise noted. Measured on the evaluation board. ADRF5043 Data Sheet THEORY OF OPERATION The ADRF5043 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The RF ports are internally matched to 50 . Therefore, external matching networks are not required. The ADRF5043 integrates a driver to perform logic functions internally and to provide the user with the advantage of a simplified CMOS-/LVTTL-compatible control interface. The driver features four digital control input pins (EN, LS, V1, and V2) that control the state of the RFx paths (see Table 6). The insertion loss path conducts the RF signal between the selected RF throw port and the RF common port. The switch design is bidirectional with equal power handling capabilities. The RF input signal can be applied to the RFC port or the selected RF throw port. The isolation paths provide high loss between the insertion loss path and the unselected RF throw ports that are terminated to internal 50 resistors. The ideal power-up sequence is as follows: 1. 2. Connect GND to ground. Power up VDD and VSS. Powering up VSS after VDD avoids current transients on VDD during ramp up. Apply a control voltage to the digital control inputs (EN, LS, V1, and V2). Applying a control voltage to the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures. Use a series 1 k resistor to limit the current flowing into the control pin in such cases. If the control pins are not driven to a valid logic state (that is, controller output is in high impedance state) after VDD is powered up, it is recommended to use a pull-up or pull-down resistor. Apply an RF input signal. 3. The logic select input (LS) allows the user to define the control input logic sequence for the RF path selections. The logic level applied to the V1 and V2 pins determines which RFx port is in the insertion loss state while the other three paths are in the isolation state. When the EN pin is logic high, all four RFx paths are in isolation state regardless of the logic state of LS, V1, V2. RFx ports are terminated to internal 50 resistors, and RFC becomes reflective. 4. The ideal power-down sequence is the reverse order of the power-up sequence. Table 6. Control Voltage Truth Table EN Low Low Low Low Low Low Low Low High Digital Control Inputs LS V1 Low Low Low High Low Low Low High High Low High High High Low High High Low or high Low or high V2 Low Low High High Low Low High High Low or high RFC to RF1 Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) RFx Paths RFC to RF2 RFC to RF3 Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Rev. 0 | Page 10 of 12 RFC to RF4 Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) Isolation (off ) Data Sheet ADRF5043 APPLICATION INFORMATION EVALUATION BOARD All RF traces are routed on the top copper layer, whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 8 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The total board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. All measurements in this data sheet are measured on the ADRF5043-EVALZ evaluation board. Figure 24 shows the simplified application circuit for ADRF5043-EVALZ evaluation board. See the ADRF5043-EVALZ user guide for more information on using the evaluation board. The design of the ADRF5043-EVALZ board serves as a layout recommendation. The Gerber files of the ADRF5043-EVALZ evaluation board are available at www.analog.com/EVALADRF5043. The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with a trace width of 14 mil and a ground clearance of 7 mil to have a characteristic impedance of 50 . The RF transmission lines are tapered at the RFC or RFx pin transition, as shown in Figure 23. For optimal RF and thermal grounding, arrange as many plated through vias as possible around the transmission lines and under the exposed pad of the package. The ADRF5043-EVALZ is a 4-layer evaluation board. The outer copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil) and are separated by dielectric materials. Figure 22 shows the cross sectional view of the evaluation board stackup. W = 14mil 1.5oz Cu (2.2mil) G = 7mil 1.5oz Cu (2.2mil) 1.5oz Cu (2.2mil) T = 2.2mil H = 8mil RO4003 0.5oz Cu (0.7mil) 1.5oz Cu (2.2mil) 23794-025 23794-024 Figure 22. Evaluation Board Cross Sectional View Figure 23. RF Trasmission Lines RF1 50 V2 CMOS/LVTTL CMOS/LVTTL 24 23 22 21 20 EN 1 V1 2 18 3 17 CMOS/LVTTL 50 RFC -3.3V VSS 100pF ADRF5043 4 LS 19 15 6 14 7 13 9 10 11 RF2 16 5 8 50 12 50 RF3 100pF 3.3V VDD 50 RF4 Figure 24. Application Circuit Rev. 0 | Page 11 of 12 23794-023 TOTAL THICKNESS -62mil 0.5oz Cu (0.7mil) ADRF5043 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 PIN 1 INDICATOR AREA 1.60 REF 0.40 BSC 19 1 20 PIN 1 INDICATOR (C0.225 x 0.45) 24 18 2.40 REF 1.50 BSC SQ EXPOSED PAD 6 13 0.125 REF 0.125 REF PKG-006844 0.808 0.738 0.668 SIDE VIEW 0.530 REF 0.248 0.208 0.168 SEATING PLANE 7 0.250 0.200 0.150 BOTTOM VIEW 0.325 0.275 0.225 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-11-2020-A TOP VIEW 12 Figure 25. 24-Terminal Land Grid Array [LGA] 3 mm x 3 mm Body and 0.738 mm Package Height (CC-24-12) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5043BCCZN ADRF5043BCCZN-R7 ADRF5043-EVALZ 1 Temperature Range -40C to +105C -40C to +105C Package Description 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D23794-7/20(0) Rev. 0 | Page 12 of 12 Package Option CC-24-12 CC-24-12 Marking Code 043 043