Nonreflective, 9 kHz to 44 GHz
Silicon SP4T Switch
Data Sheet
ADRF5043
Rev. 0 Document Feedback
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Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 9 kHz to 44 GHz
Nonreflective 50 Ω design
Low insertion loss
1.5 dB up to 18 GHz
2.4 dB up to 40 GHz
2.5 dB up to 44 GHz
High isolation
44 dB up to 18 GHz
39 dB up to 40 GHz
36 dB up to 44 GHz
High input linearity
P0.1dB: 26 dBm typical
IP3: 48 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
All off state control
Logic select control
No low frequency spurs
Settling time (0.1 dB final RF output): 6 µs
24-terminal, 3 mm × 3 mm LGA package
Pin compatible with ADRF5042, fast switching version
APPLICATIONS
Industrial scanners
Test instrumentation
Cellular infrastructure—millimeterwave (mmWave) 5G
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
FUNCTIONAL BLOCK DIAGRAM
GND
GND
RF1
GND
V2
RF4
VDD
GND
GND
GND
GND
EN
V1
RFC
LS
GND
VSS
GND
GND
RF2
GND
GND
RF3
GND
DRIVER
50Ω 50Ω
50Ω
50Ω
ADRF5043
1
2
3
4
5
6
78 9 10 11 12 13
14
15
16
17
18
19
2021222324
23794-001
Figure 1.
GENERAL DESCRIPTION
The ADRF5043 is a nonreflective, SP4T switch manufactured in
the silicon on insulator (SOI) process.
The ADRF5043 operates from 9 kHz to 44 GHz with an
insertion loss of lower than 2.5 dB and an isolation of higher
than 36 dB. The device has a RF input power handling
capability of 24 dBm for both through and terminated paths.
The ADRF5043 requires a dual-supply voltage of +3.3 V and
−3.3 V. The device employs CMOS- and low voltage transistor
to transistor logic (LVTTL)-compatible controls.
The ADRF5043 has enable and logic select controls to feature
all off state and port mirroring, respectively.
The ADRF5043 is pin compatible with the ADRF5042 fast
switching version, which operates from 100 MHz to 44 GHz.
The ADRF5043 comes in a 24-terminal, 3 mm × 3 mm, RoHS
compliant, land grid array (LGA) package and can operate from
−40°C to +105°C.
ADRF5043 Data Sheet
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Electrostatic Discharge (ESD) Ratings ...................................... 5
Power Derating Curves ................................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ..............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input Power Compression and Third-Order Intercept ............9
Theory of Operation ...................................................................... 10
Application Information ................................................................ 11
Evaluation Board ........................................................................ 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
7/2020—Revision 0: Initial Version
Data Sheet ADRF5043
Rev. 0 | Page 3 of 12
SPECIFICATIONS
Positive supply voltage (VDD) = 3.3 V, negative supply voltage (VSS) = −3.3 V, V1 pin voltage (V1) = 0 V or 3.3 V, V2 pin voltage (V2) = 0 V
or 3.3 V, LS = 0 V or 3.3 V, EN = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. RFx refers to RF1 to RF4. VCTL
is the digital control inputs voltage.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 0.009 44,000 MHz
INSERTION LOSS
Between RFC and RFx (On) 9 kHz to 18 GHz 1.5 dB
18 GHz to 26 GHz 1.8 dB
26 GHz to 35 GHz 2.1 dB
35 GHz to 40 GHz 2.4 dB
40 GHz to 44 GHz 2.5 dB
ISOLATION
Between RFC and RFx (Off) 9 kHz to 18 GHz 44 dB
18 GHz to 26 GHz 43 dB
26 GHz to 35 GHz 40 dB
35 GHz to 40 GHz 39 dB
40 GHz to 44 GHz 36 dB
RETURN LOSS
RFC and RFx (On) 9 kHz to 18 GHz 15 dB
18 GHz to 26 GHz 15 dB
26 GHz to 35 GHz 14 dB
35 GHz to 40 GHz 13 dB
40 GHz to 44 GHz 13 dB
RFx (Off) 9 kHz to 18 GHz 23 dB
18 GHz to 26 GHz 20 dB
26 GHz to 35 GHz 17 dB
35 GHz to 40 GHz 15 dB
40 GHz to 44 GHz 14 dB
SWITCHING
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 1.1 µs
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 2.8 µs
Settling Time
0.1 dB 50% VCTL to 0.1 dB of final RF output 6 µs
0.05 dB 50% VCTL to 0.05 dB of final RF output 7.8 µs
INPUT LINEARITY1
0.1 dB Power Compression P0.1dB f = 1 MHz to 40 GHz 26 dBm
1 dB Power Compression P1dB f = 1 MHz to 40 GHz 27 dBm
Third-Order Intercept IP3 Two-tone input power = 15 dBm each tone,
f = 1 MHz to 40 GHz, Δf = 1 MHz
48 dBm
Second-Order Intercept IP2 Two-tone input power = 15 dBm each tone,
f = 10 GHz, Δf = 1 MHz
120 dBm
VIDEO FEEDTHROUGH2 3 mV p-p
SUPPLY CURRENT VDD, VSS pins
Positive Supply Current IDD 370 µA
Negative Supply Current ISS −100 µA
DIGITAL CONTROL INPUTS V1, V2, EN, LS pins
Voltage
Low VINL 0 0.8 V
High VINH 1.2 3.3 V
ADRF5043 Data Sheet
Rev. 0 | Page 4 of 12
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Current
Low IINL 3 µA
High IINH 6 µA
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Inputs Voltage VCTL 0 VDD V
RFx Input Power3 PIN f = 1 MHz to 44 GHz, TCASE = 85°C4
Through Path Average 24 dBm
Peak 24 dBm
Terminated Path Average 24 dBm
Peak 24 dBm
Hot Switching Average 24 dBm
Peak 24 dBm
Case Temperature TCASE −40 +105 °C
1 For input linearity performance over frequency, see Figure 18 to Figure 21.
2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage.
3 For power derating over frequency, see Figure 2.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Data Sheet ADRF5043
Rev. 0 | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Supply Voltage
Positive −0.3 V to +3.6 V
Negative −3.6 V to +0.3 V
Digital Control Inputs1 −0.3 V to VDD + 0.3 V or 3.3 mA,
whichever occurs first
RFx Input Power (f2 = 1 MHz to
44 GHz, TCASE = 85°C3)
Through Path
Average 26 dBm
Peak 26dBm
Terminated Path
Average 25 dBm
Peak 25dBm
Hot Switching
Average 25 dBm
Peak 25dBm
Temperature
Junction, TJ 135°C
Storage Range −65°C to +150°C
Reflow 260°C
1 Overvoltages at digital control inputs are clamped by internal diodes.
Current must be limited to the maximum rating given.
2 For power derating over frequency, see Figure 2.
3 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC1 Unit
CC-24-12
Through Path 468 °C/W
Terminated Path 200 °C/W
1 θJC was determined by simulation under the following conditions: the heat
transfer is due solely to thermal conduction from the channel through the
ground pad to the PCB, and the ground pad is held constant at the
operating temperature of 85°C.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD
sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADRF5043
Table 4. ADRF5043, 24-Terminal LGA
ESD Model Withstand Threshold (V)
HBM
RFx Pins 1000
Supply and Digital Control Pins 2000
POWER DERATING CURVES
2
–18
–16
–14
10k 100G
POWER DE RATING (d B)
FRE Q UE NCY ( Hz )
–12
–10
–8
–6
–4
–2
0
100k 1M 10M 100M 1G 10G
23794-002
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
ESD CAUTION
ADRF5043 Data Sheet
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GND
RF1
GND
V2
VDD
GND
RF4
GND
GND
V1
EN
GND
RFC
VSS
GND GND
GND
GND
RF2
RF3
GND
1
2
3
4
5
6
LS 78 9 10 11 12 13
14
15
16
17
18
GND
19
202122
2324
TOP VIEW
(Not to Scal e)
ADRF5043
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF AND DC GROUND.
23794-004
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Enable Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.
2 V1 Control Input 1. See Table 6 for the truth table. See Figure 5 for the interface schematic.
3, 5, 9, 11 to 13, 15 to
17, 19 to 21, 23
GND Ground. The GND pins must be connected to the RF and dc ground of the PCB.
4 RFC RF Common Port. RFC is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
6 VSS Negative Supply Voltage.
7 LS Logic Select Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.
8 VDD Positive Supply Voltage.
10 RF4 RF Throw Port 4. RF4 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
14 RF3 RF Throw Port 3. RF3 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
18 RF2 RF Throw Port 2. RF2 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
22 RF1 RF Throw Port 1. RF1 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required
when the RF line potential is equal to 0 V dc.
24 V2 Control Input 2. See Table 6 for the truth table. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
23794-005
Figure 4. RFC and RF1 to RF4 Pin Interface Schematic
Figure 5. V1, V2, EN, and LS Pin Interface Schematic
Data Sheet ADRF5043
Rev. 0 | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3. 3 V, V SS = −3.3 V, VCTL = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation board.
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0 5 10 15 20 25 30 35 45 5040
INSERTION LOSS FOR RFC TO RFx ON (dB)
FRE Q UE NCY ( GHz)
RF1
RF2
RF3
RF4
23794-007
Figure 6. Insertion Loss for RFC to RFx On vs. Frequency
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 45 5040
RET URN LOS S FOR RFC TO RFx ON (d B)
FRE Q UE NCY ( GHz)
RF1
RF2
RF3
RF4
RFC
23794-008
Figure 7. Return Loss for RFC and RFx On vs. Frequency
0
–100
ISOLATION FOR RFC to RFx OFF (dB)
050
FRE Q UE NCY ( GHz)
510 15 20 25 30 35 40 45
RF2
RF3
RF4
–90
–80
–70
–60
–50
–40
–30
–20
–10
23794-009
Figure 8. Isolation for RFC to RFx Off vs. Frequency, RFC to RF1 Path On
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0 5 10 15 20 25 30 35 45 5040
INSERTION LOSS FOR RFC TO RF1 ON (dB)
FRE Q UE NCY ( GHz)
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40°C
23794-010
Figure 9. Insertion Loss for RFC to RF1 On vs. Frequency
over Various Temperatures
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 45 5040
RETURN LOSS FOR RFx OFF (dB)
FRE Q UE NCY ( GHz)
RF1
RF2
RF3
RF4
23794-011
Figure 10. Return Loss for RFx Off vs. Frequency
0
–100
ISOLATION FOR RFC TO RFx OFF (dB)
050
FREQUENCY ( GHz)
510 15 20 25 30 35 40 45
RF1
RF3
RF4
–90
–80
–70
–60
–50
–40
–30
–20
–10
23794-012
Figure 11. Isolation for RFC to RFx Off vs. Frequency, RFC to RF2 Path On
ADRF5043 Data Sheet
Rev. 0 | Page 8 of 12
0
–100
ISOLATION FOR RFC TO RFx OFF (dB)
050
FRE Q UE NCY ( GHz)
510 15 20 25 30 35 40 45
RF1
RF2
RF4
–90
–80
–70
–60
–50
–40
–30
–20
–10
23794-013
Figure 12. Isolation for RFC to RFx Off vs. Frequency, RFC to RF3 Path On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0510 15 20 25 30 35 50
4540
CHANNEL TO CHANNE L IS OLATION (d B)
FRE Q UE NCY ( GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
23794-014
Figure 13. Channel to Channel Isolation vs. Frequency, RFC to RF1 Path On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 5045
40
CHANNEL TO CHANNE L IS OLATION (d B)
FRE Q UE NCY ( GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
23794-015
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF3 Path On
0
–100
ISOLATION FOR RFC TO RFx OFF (dB)
050
FRE Q UE NCY ( GHz)
510 15 20 25 30 35 40 45
RF1
RF2
RF3
–90
–80
–70
–60
–50
–40
–30
–20
–10
23794-016
Figure 15. Isolation for RFC to RFx Off vs. Frequency, RFC to RF4 Path On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 504540
CHANNEL TO CHANNE L IS OLATION (d B)
FRE Q UE NCY ( GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
23794-017
Figure 16. Channel to Channel Isolation vs. Frequency, RFC to RF2 Path On
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 504540
CHANNEL TO CHANNE L IS OLATION (d B)
FRE Q UE NCY ( GHz)
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
23794-018
Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF4 Path On
Data Sheet ADRF5043
Rev. 0 | Page 9 of 12
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = +3.3 V, VSS = −3.3 V, VCTL = 0 V or +3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation board.
30
28
26
24
22
20
18
16
14
12
10 040
INPUT P0.1dB ( dBm)
FRE Q UE NCY ( GHz)
510 15 20 25 30 35
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40°C
23794-019
Figure 18. Input P0.1dB vs. Frequency over Various Temperatures
60
20 040
INPUT I P 3 ( dBm)
FRE Q UE NCY ( GHz)
25
30
35
40
45
50
55
510 15 20 25 30 35
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40°C
23794-020
Figure 19. Input IP3 vs. Frequency over Various Temperatures
30
28
26
24
22
20
18
16
14
12
10
INPUT P0.1dB ( dBm)
FRE Q UE NCY ( Hz )
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40°C
10k 1G
100k 1M 10M 100M
23794-021
Figure 20. Input P0.1dB vs. Frequency, Low Frequency Detail
over Various Temperatures
60
20
INPUT I P 3 ( dBm)
25
30
35
40
45
50
55
10k 1G
FRE Q UE NCY ( Hz )
100k 1M 10M 100M
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40°C
23794-022
Figure 21. Input IP3 vs. Frequency, Low Frequency Detail
over Various Temperatures
ADRF5043 Data Sheet
Rev. 0 | Page 10 of 12
THEORY OF OPERATION
The ADRF5043 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V. The RF ports are internally matched to
50 Ω. Therefore, external matching networks are not required.
The ADRF5043 integrates a driver to perform logic functions
internally and to provide the user with the advantage of a simplified
CMOS-/LVTTL-compatible control interface. The driver features
four digital control input pins (EN, LS, V1, and V2) that control
the state of the RFx paths (see Table 6).
The logic select input (LS) allows the user to define the control
input logic sequence for the RF path selections. The logic level
applied to the V1 and V2 pins determines which RFx port is in
the insertion loss state while the other three paths are in the
isolation state.
When the EN pin is logic high, all four RFx paths are in
isolation state regardless of the logic state of LS, V1, V2. RFx
ports are terminated to internal 50 Ω resistors, and RFC
becomes reflective.
The insertion loss path conducts the RF signal between the
selected RF throw port and the RF common port. The switch
design is bidirectional with equal power handling capabilities.
The RF input signal can be applied to the RFC port or the
selected RF throw port. The isolation paths provide high loss
between the insertion loss path and the unselected RF throw
ports that are terminated to internal 50 Ω resistors.
The ideal power-up sequence is as follows:
1. Connect GND to ground.
2. Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp up.
3. Apply a control voltage to the digital control inputs (EN,
LS, V1, and V2). Applying a control voltage to the digital
control inputs before the VDD supply can inadvertently
forward bias and damage the internal ESD protection
structures. Use a series 1 kΩ resistor to limit the current
flowing into the control pin in such cases. If the control
pins are not driven to a valid logic state (that is, controller
output is in high impedance state) after VDD is powered
up, it is recommended to use a pull-up or pull-down
resistor.
4. Apply an RF input signal.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 6. Control Voltage Truth Table
Digital Control Inputs RFx Paths
EN LS V1 V2 RFC to RF1 RFC to RF2 RFC to RF3 RFC to RF4
Low Low Low Low Insertion loss (on) Isolation (off) Isolation (off ) Isolation (off)
Low Low High Low Isolation (off) Insertion loss (on) Isolation (off) Isolation (off )
Low Low Low High Isolation (off) Isolation (off) Insertion loss (on) Isolation (off)
Low Low High High Isolation (off ) Isolation (off) Isolation (off) Insertion loss (on)
Low High Low Low Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Low High High Low Isolation (off ) Isolation (off) Insertion loss (on) Isolation (off)
Low High Low High Isolation (off ) Insertion loss (on) Isolation (off) Isolation (off)
Low High High High Insertion loss (on) Isolation (off) Isolation (off) Isolation (off )
High Low or high Low or high Low or high Isolation (off) Isolation (off) Isolation (off ) Isolation (off)
Data Sheet ADRF5043
Rev. 0 | Page 11 of 12
APPLICATION INFORMATION
EVALUATION BOARD
All measurements in this data sheet are measured on the
ADRF5043-EVALZ evaluation board. Figure 24 shows the
simplified application circuit for ADRF5043-EVALZ evaluation
board. See the ADRF5043-EVALZ user guide for more
information on using the evaluation board.
The design of the ADRF5043-EVALZ board serves as a layout
recommendation. The Gerber files of the ADRF5043-EVALZ
evaluation board are available at www.analog.com/EVAL-
ADRF5043.
The ADRF5043-EVALZ is a 4-layer evaluation board. The outer
copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil)
and are separated by dielectric materials. Figure 22 shows the
cross sectional view of the evaluation board stackup.
0.5oz Cu ( 0.7mil)
RO4003
0.5oz Cu ( 0.7mil)
1.5oz Cu ( 2.2mil) 1. 5oz Cu (2. 2mil)
W = 14mil G = 7mil
T = 2.2mi l
H = 8mil
1.5oz Cu ( 2.2mil)
1.5oz Cu ( 2.2mil)
TOTAL THICKNESS
–62mil
23794-024
Figure 22. Evaluation Board Cross Sectional View
All RF traces are routed on the top copper layer, whereas the
inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 8 mil Rogers RO4003, offering optimal high frequency
performance. The middle and bottom dielectric materials
provide mechanical strength. The total board thickness is
62 mil, which allows 2.4 mm RF launchers to be connected at
the board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. The RF transmission lines are tapered at the RFC or RFx
pin transition, as shown in Figure 23. For optimal RF and
thermal grounding, arrange as many plated through vias as
possible around the transmission lines and under the exposed
pad of the package.
23794-025
Figure 23. RF Trasmission Lines
V1
EN CMOS/LVTTL
CMOS/LVTTL
CMOS/LVTTL
–3.3V
3.3V
100pF
100pF
RFC
RF4
RF1
VSS
VDD
V2
RF2
RF3
1
2
3
4
5
6
LS
78 9 10 11 12 13
14
15
16
17
18
19
2021222324
ADRF5043
50Ω
50Ω
50Ω
50Ω
50Ω
23794-023
Figure 24. Application Circuit
ADRF5043 Data Sheet
Rev. 0 | Page 12 of 12
OUTLINE DIMENSIONS
06-11-2020-A
PKG-006844
3.10
3.00 SQ
2.90
TOP VIEW BOTTOM VIEW
SIDE VIEW
1
6
712
13
18
19
20 24
0.40
BSC
0.248
0.208
0.168
0.808
0.738
0.668
0.250
0.200
0.150
0.325
0.275
0.225
0.530 REF
0.125 REF
0.125 REF
SEATING
PLANE
PIN 1
INDICATOR
AREA
1.50 BSC
SQ
1.60
REF
2.40
REF
PIN 1
INDICATOR
(C0.225 ×0.45°)
FO R PROPER CO NNE CTIO N OF
THE EXPOSED PAD, REFER TO
THE PI N CONFIG URATIO N AND
FUNCTI ON DESCRIPTIO NS
SECTI ON O F THIS DATA SHE ET.
EXPOSED
PAD
Figure 25. 24-Terminal Land Grid Array [LGA]
3 mm × 3 mm Body and 0.738 mm Package Height
(CC-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADRF5043BCCZN −40°C to +105°C 24-Terminal Land Grid Array [LGA] CC-24-12 043
ADRF5043BCCZN-R7 −40°C to +105°C 24-Terminal Land Grid Array [LGA] CC-24-12 043
ADRF5043-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
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