PCI EXPRESS™ JITTER ATTENUATOR ICS874003-05
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 1
ICS874003BG-05 REV. A APRIL 15, 2009
General Description
The ICS874003-05 is a high performance
Differential-to-LVDS Jitter Attenuator designed for
use in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the
PLL synthesizer and from the system board. The ICS874003-05
has a bandwidth of 6.2MHz with <1dB peaking, easily meeting
PCI Express Gen2 PLL requirements.
The ICS874003-05 uses IDT’s 3rd Generation FemtoClock™ PLL
technology to achieve the lowest possible phase noise. The device
is packaged in a 20 Lead TSSOP package, making it ideal for use
in space constrained applications such as PCI Express add-in
cards.
Features
•Three differential LVDS output pairs
•One differential clock input
•CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
•Input frequency range: 98MHz to 128MHz
•Output frequency range: 98MHz to 320MHz
•VCO range: 490MHz - 640MHz
•Supports PCI-Express Spread-Spectrum Clocking
•High PLL bandwidth allows for better input tracking
•PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
•0°C to 70°C ambient operating temperature
•Full 3.3V operating supply
•Available in lead-free (RoHS 6) packages
F_SEL[2:0] Function Table
HiPerClockS™
ICS
Inputs Outputs
F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0
0 (default) 0 (default) 0 (default) ÷2 ÷2
100 ÷5 ÷2
010 ÷4 ÷2
110 ÷2 ÷4
001 ÷2 ÷5
101 ÷5 ÷4
011 ÷4 ÷5
111 ÷4 ÷4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
VDDA
nc
F_SEL0
MR
nQA0
QA0
VDDO
QA1
VDD
nQA1
VDDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
CLK
OEA
Pin Assignment
ICS874003-05
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 2
ICS874003BG-05 REV. A APRIL 15, 2009
Block Diagram
÷5
÷4
÷2 (default)
÷5
÷4
÷2 (default)
VCO
490 - 640MHz
Phase
Detector
M = ÷5 (fixed)
3
QA0
nQA0
QA1
nQA1
QB0
nQB0
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
OEA
F_SEL2:0
CLK
nCLK
MR
OEB
3
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 3
ICS874003BG-05 REV. A APRIL 15, 2009
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Table 3. Output Enable Function Table
Number Name Type Description
1, 20 QA1, nQA1 Output Bank A differential output pair. LVDS interface levels.
2, 19 VDDO Power Output supply pins.
3, 4 QA0, nQA0 Output Bank A differential output pair. LVDS interface levels.
5 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (nQx) to go low and the inverted outputs (Qx) to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
6,
9,
16
F_SEL0,
F_SEL1,
F_SEL2
Input Pulldown Frequency select pin for QAx/nQAx and QB0/nQB0 outputs.
LVCMOS/LVTTL interface levels.
7 nc Unused No connect.
8V
DDA Power Analog supply pin.
10 VDD Power Core supply pin.
11 OEA Input Pullup
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active.
When LOW, the QAx/nQAx outputs are in a high-impedance state.
LVCMOS/LVTTL interface levels.
12 CLK Input Pulldown Non-inverting differential clock input.
13 nCLK Input Pullup Inverting differential clock input.
14 GND Power Power supply ground.
15 OEB Input Pullup
Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active.
When LOW, the QB0/nQB0 outputs are in a high-impedance state.
LVCMOS/LVTTL interface levels.
17, 18 nQB0, QB0 Output Bank B differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
Inputs Outputs
OEA OEB QA[0:1], nQA[0:1] QB0, nQB0
0 0 High Impedance High Impedance
1 (default) 1 (default) Enabled Enabled
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 4
ICS874003BG-05 REV. A APRIL 15, 2009
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 86.7°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage VDD – 0.16 3.3 VDD V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 75 mA
IDDA Analog Supply Current 16 mA
IDDO Output Supply Current 75 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current
OEA, OEB VDD = VIN = 3.465V 5 µA
F_SEL0, F_SEL1,
F_SEL2, MR VDD = VIN = 3.465V 150 µA
IIL Input Low Current
OEA, OEB VDD = 3.465V, VIN = 0V -150 µA
F_SEL0, F_SEL1,
F_SEL2, MR VDD = 3.465V, VIN = 0V -5 µA
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 5
ICS874003BG-05 REV. A APRIL 15, 2009
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current CLK VDD = VIN = 3.465V 150 µA
nCLK VDD = VIN = 3.465V 5 µA
IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA
nCLK VDD = 3.465V, VIN = 0V -150 µA
VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 275 375 485 mV
∆VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.20 1.35 1.50 V
∆VOS VOS Magnitude Change 50 mV
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 6
ICS874003BG-05 REV. A APRIL 15, 2009
Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note PCI Express Reference Clock
Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall
composite transfer function.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS
(High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and
also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer
function.
NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 98 320 MHz
tjit(cc) Cycle-to-Cycle Jitter;
NOTE 4 35 ps
tsk(o) Output Skew; NOTE 4, 5 145 ps
tsk(b) Bank Skew; NOTE 4, 6 Bank A 55 ps
tR / tFOutput Rise/Fall Time 20% to 80% 200 600 ps
odc Output Duty Cycle 47 53 %
tj
Phase Jitter Peak-to-Peak;
NOTE 1, 3
100MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.54 ps
125MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.13 ps
250MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
12.87 ps
tREFCLK_HF_RMS
Phase Jitter RMS;
NOTE 2, 3
100MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.22 ps
125MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.17 ps
250MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.11 ps
tREFCLK_LF_RMS
Phase Jitter RMS;
NOTE 2, 3
100MHz output,
Low Band: 10kHz - 1.5MHz 0.25 ps
125MHz output,
Low Band: 10kHz - 1.5MHz 0.22 ps
250MHz output,
Low Band: 10kHz - 1.5MHz 0.22 ps
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 7
ICS874003BG-05 REV. A APRIL 15, 2009
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Bank Skew
Output Skew
Differential Input Level
Cycle-to-Cycle Jitter
Output Duty Cycle/Pulse Width/Period
SCOPE
Qx
nQx
3.3V±5%
POWER SUPPLY
+–
Float GND
LVDS
VDDA
VDD,
VDDO
tsk(b)
QA0
nQA0
QA1
nQA1
tsk(o)
Qx
nQx
Qy
nQy
VDD
nCLK
CLK
GND
V
CMR
Cross Points
V
PP
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
QAx, QB0
nQAx, nQB0
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
QAx, QB0
nQAx, nQB0
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 8
ICS874003BG-05 REV. A APRIL 15, 2009
Parameter Measurement Information, continued
Output Rise/Fall Time
Differential Output Voltage Setup
Offset Voltage Setup
20%
80% 80%
20%
t
R
t
F
V
OD
QAx, QB0
nQAx, nQB0
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
out
out
LVDS
DC Input
➤
➤
➤
VOS/∆ VOS
VDD
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 9
ICS874003BG-05 REV. A APRIL 15, 2009
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS874003-05
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
VDD
VDDA
3.3V
10Ω
10µF.01µF
.01µF
V_REF
Single Ended Clock Input
VDD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 10
ICS874003BG-05 REV. A APRIL 15, 2009
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50
R2
50
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
3.3V
LVPECL HiPerClockS
Input
HCSL
*R3 33
*R4 33
CLK
nCLK
2.5V 3.3V
Zo = 50Ω
Zo = 50Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
CLK
nCLK
HiPerClockS
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 11
ICS874003BG-05 REV. A APRIL 15, 2009
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
–
+
3.3V 50Ω
50Ω
100Ω Differential Transmission Line
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 12
ICS874003BG-05 REV. A APRIL 15, 2009
Schematic Example
Figure 5 shows an example of ICS874003-05 application
schematic. In this example, the device is operated at VDD = 3.3V.
The decoupling capacitors should be located as close as possible
to the power pin. Two examples of LVDS terminations are shown in
this schematic. The input is driven either by a 3.3V LVPECL driver
or a 3.3V LVCMOS.
Figure 5. ICS874003-05 Schematic Example
ICS874003-05
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 13
ICS874003BG-05 REV. A APRIL 15, 2009
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The below block diagram shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the Tx and Rx serdes PLLs are modeled as
well as the phase interpolator in the receiver. These transfer
functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist
(e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter
result is reported in peak-peak. For PCI Express Gen 2, two
transfer functions are defined with 2 evaluation ranges and the final
jitter number is reported in rms. The two evaluation ranges for PCI
Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz -
Nyquist (High Band). The below plots show the individual transfer
functions as well as the overall transfer function Ht. The respective
-3 dB pole frequencies for each transfer function are labeled as F1
for transfer function H1, F2 for H2, and F3 for H3. For a more
thorough overview of PCI Express jitter analysis methodology,
please refer to IDT Application Note PCI Express Reference Clock
Requirements.
Ht s() H3 s() H1 s() H2 s()–[]×=
Ys() Xs() H3 s()×H1 s() H2 s()–[]×=
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 14
ICS874003BG-05 REV. A APRIL 15, 2009
PCIe Gen 1 Magnitude of Transfer Function
PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function
103104105106107
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 1
F1: 2.2e+007 F2: 1.5e+006
F3: 1.5e+006
H1
H2
H3
Ht=(H1-H2)*H3
103104105106107
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 2A
F1: 1.6e+007 F2: 5.0e+006
F3: 1.0e+006
H1
H2
H3
Ht=(H1-H2)*H3
103104105106107
-60
-50
-40
-30
-20
-10
0
Frequency (Hz)
Mag (dB)
Magnitude of Transfer Functions - PCIe Gen 2B
F1: 1.6e+007 F2: 8.0e+006
F3: 1.0e+006
H1
H2
H3
Ht=(H1-H2)*H3
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 15
ICS874003BG-05 REV. A APRIL 15, 2009
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS874003-05.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS74003-05 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 16mA) = 315.315mW
• Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW
Total Power_MAX = 315.3mW + 259.9mW = 575.2mW
•
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.575W * 86.7°C/W = 119.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board.
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 16
ICS874003BG-05 REV. A APRIL 15, 2009
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for ICS874003-05 is: 1418
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N20
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D6.40 6.60
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
IDT™ / ICS™
PCI EXPRESS™ JITTER ATTENUATOR 17
ICS874003BG-05 REV. A APRIL 15, 2009
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
874003BG-05LF 874003BG-05LF “Lead-Free” 20 Lead TSSOP Tube 0°C to 70°C
874003BG-05LFT 874003BG-05LF “Lead-Free” 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
www.IDT.com
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Contact Information:
www.IDT.com
