SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
1
FEATURES
• High Speed: 35, 45, 55, and 70
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS MARKING
• Timing
35ns access -35
45ns access -45
55ns access -55*
70ns access -70*
• Package(s)
Ceramic DIP (300 mil) C No. 106
Ceramic LCC EC No. 204
• Operating Temperature Ranges
Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-88725
• SMD 5962-88544
• MIL-STD-883
24-Pin DIP (C)
(300 MIL)
GENERAL DESCRIPTION
The Micross Components SRAM family employs
high-speed, low-power CMOS and are fabricated using double-
layer metal, double-layer polysilicon technology.
For fl exibility in high-speed memory applications,
Micross Components offers chip enable (CE\) on all or ganiza-
tions. This enhancement can place the outputs in High-Z for
additional fl exibility in system design. The x1 confi guration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is ac-
complished when WE\ remains HIGH and CE\ goes LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power
requirements.
These devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
256K x 1 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.micross.com
28-Pin LCC (EC)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A6
A7
A8
A9
A10
A11
A14
A15
A0
Q
WE\
Vss
Vcc
A5
A4
A3
A2
A1
A17
A16
A13
A12
D
CE\
3 2 1 28 27
13 14 15 16 17
4
5
6
7
8
9
10
11
12
26
25
24
23
22
21
20
19
18
NC
A9
A10
A11
A14
A15
A0
Q
NC
NC
A4
A3
A2
A1
A17
A16
A13
NC
A12
D
CE\
Vss
WE\
A8
A7
A6
Vcc
A5
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
ROW DECODER
262,144-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
GND
D
Q
CE\
WE\
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
COLUMN DECODER
A5 A6 A7 A8 A9 A10 A11 A12
POWER
DOWN
MODE CE\ WE\ DQ POWER
STANDBY H X HIGH-Z STANDBY
READ L H Q ACTIVE
WRITE L L HIGH-Z ACTIVE
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
3
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specifi cation is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
CAPACITANCE
Voltage on Any Pin Relative to Vss..............................-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.........................-0.5V to +7V
Voltage Applied to Q....................................................-0.5V to +6V
Storage Temperature.................................................-65oC to +150oC
Power Dissipation.........................................................................1W
Short Circuit Output Current.....................................................50mA
Lead Temperature (soldering 10 seconds).............................+260oC
Junction Temperature..............................................................+175oC
SYM -35 -45 UNITS NOTES
ICCSP 120 120 mA 3
ICCLP 100 100 mA 3
Power Supply
Current: Standby ISBT1 25 25 mA
ISBCSP 20 20 mA
"L" Version Only ISBCLP 33mA
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz
CE\ > V
IH
; All Other Inputs
< VIL or > VIH, V
CC
= MAX
f = 0 Hz
MAX
CONDITIONS
Power Supply
Current: Operating
PARAMETER
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES
Input High (Logic 1) Voltage V
IH
2.2 V
CC
+0.5 V1
Input Low (Logic 0) Voltage V
IL
-0.5 0.8 V 1, 2
Input Leakage Current 0V<V
IN
<V
CC
IL
I
-10 10 μA
Output Leakage Current Output(s) disabled
0V<V
OUT
<V
CC
IL
O
-10 10 μA
Output High Voltage I
OH
= -4.0mA V
OH
2.4 V 1
Output Low Voltage I
OL
= 8.0mA V
OL
0.4 V 1
PARAMETER CONDITIONS SYM MAX UNITS NOTES
Input Capacitance C
I
10 pF 4
Output Capacitance C
O
12 pF 4
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
MIN MAX MIN MAX UNITS NOTES
READ CYCLE
READ cycle time tRC 35 45 ns
Address access time tAA 35 45 ns
Chip Enable access time tACE 35 45 ns
Output hold from address change tOH 33ns
Chip Enable to output in Low-Z tLZCE 33ns7
Chip disable to output in High-Z tHZCE 20 20 ns 6, 7
Chip Enable to power-up time tPU 00ns4
Chip disable to power-down time tPD 35 45 ns 4
WRITE CYCLE
WRITE cycle time tWC 35 45 ns
Chip Enable to end of write tCW 30 40 ns
Address valid to end of write tAW 30 40 ns
Address setup time tAS 00ns
Address hold from end of write tAH 55ns
WRITE pulse width tWP 30 40 ns
Data setup time tDS 20 20 ns
Data hold time tDH 00ns
Write disable to output in Low-Z tLZWE 00ns7
Write Enable to output in High-Z tHZWE 0 15 0 20 ns 6, 7
-35 -45
DESCRIPTION SYMBOL
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specifi ed value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specifi ed with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE are
specifi ed with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state volt-
age, allowing for actual tester RC time constant.
7. At any given temperature and voltage condition, tHZCE is
less than tLZCE, and tHZWE is less than tLZWE and tHZOE is
less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
VTH =
QVTH =
Q5pF
DATA RETENTION MODE
VDR > 2V
4.5V 4.5V
VDR
tCDR tR
VIH
VIL
VCC
CE\
DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES
VCC for Retention Data V
DR
2 --- V
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V I
CCDR
900 µA
Chip Deselect to Data
Retention Time t
CDR
0 --- ns 4
Operation Recovery Time t
R
t
RC
ns 4, 11
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
6
tAA
tOH
tRCtRC
PREVIOUS DATA VALID
VALID
DATA VALID
ADDRESS
DQ
READ CYCLE NO. 1 8, 9
tRC
tAA
tOH
tRCtRC
CE\
READ CYCLE NO. 2 7, 8, 10
tRC
tPD
tPU
tHZCEtACE
tLZCE
DATA VALID
DQ
Icc
tHZCE
tLZCE tACE
tPU tPD
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
7
NOTE: Output enable (OE\) is inactive (HIGH).
WRITE CYCLE NO. 2 7, 12
(Write Enabled Controlled)
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
tDHtDS
tWP1tWP1
tAH
tCW
tAW
tCWtAS
tWCtWC
HIGH Z
DATA VAILD
ADDRESS
CE\
WE\
D
Q
tWC
tAW
tAS tCW
tAH
tWP
tDS tDH
tDH
tWP1tWP1
tAS
tAW
tCW tAH
tCW
tWCtWC
DATA VALID
ADDRESS
CE\
WE\
D
Q
HIGH-Z
tDH
tDS
tWC
tAW tAH
tCW
tAS tWP
tHZWE tLZWE
DON’T CARE
UNDEFINED
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
8
MECHANICAL DEFINITIONS*
Micross Case #106 (Package Designator C)
SMD #5962-88544 & #5962-88725, Case Outline L
*All measurements are in inches.
D
Pin 1
NOTE: These dimensions are per the SMD. Micross’ package dimensional limits
may differ, but they will be within the SMD limits.
eb
b2
AQ
L
S1
c
NOTE
E
0o to 15oeA
MIN MAX
A --- 0.200
b 0.014 0.026
b2 0.045 0.065
c 0.008 0.018
D --- 1.280
E 0.220 0.310
eA
e
L 0.125 0.200
Q 0.015 0.060
S1 0.005 ---
SYMBOL
0.100 BSC
SMD SPECIFICATIONS
0.300 BSC
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
9
MECHANICAL DEFINITIONS*
Micross Case #204 (Package Designator EC)
SMD# 5962-88544, Case Outline X
*All measurements are in inches.
NOTE: These dimensions are per the SMD. Micross’ package dimensional limits
may differ, but they will be within the SMD limits.
A
A1
D3
E
D
E3
hx45o
E1
L2
B1
D1
L
e
B2
E2
D2
h x 45o
MIN MAX
A 0.060 0.120
A1 0.050 0.088
B1 0.022 0.028
B2
D 0.342 0.358
D1
D2
D3 --- 0.358
E 0.540 0.560
E1
E2
E3 --- 0.558
e
h
L 0.045 0.055
L2 0.075 0.095
0.100 BSC
0.040 REF
0.050 BSC
0.200 BSC
0.400 BSC
SYMBOL SMD SPECIFICATIONS
0.072 REF
0.200 BSC
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
10
*AVAILABLE PROCESSES
IT = Industrial Temperature Range -40oC to +85oC
XT = Extended Temperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
ORDERING INFORMATION
EXAMPLE: MT5C2561EC-70/XT
Device
Number Package
Type Speed
ns Options** Process Device
Number Package
Type Speed
ns Options** Process
MT5C2561 C -35 L /* MT5C2561 EC -35 L /*
MT5C2561 C -45 L /* MT5C2561 EC -45 L /*
MT5C2561 C -55 L /* MT5C2561 EC -55 L /*
MT5C2561 C -70 L /* MT5C2561 EC -70 L /*
EXAMPLE: MT5C2561C-45L/IT
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
11
MICROSS TO DSCC PART NUMBER
CROSS REFERENCE*
Micross Package Designator EC
Micross Part # SMD Part #
MT5C2561EC-35/883C 5962-8872501XX
MT5C2561EC-45/883C 5962-8872502XX
MT5C2561EC-55/883C 5962-8872503XX
MT5C2561EC-70/883C 5962-8872504XX
MT5C2561EC-35L883C 5962-8854401XX
MT5C2561EC-45L883C 5962-8854402XX
MT5C2561EC-55L883C 5962-8854403XX
MT5C2561EC-70L883C 5962-8854404XX
Micross Package Designator C
Micross Part # SMD Part #
MT5C2561C-35/883C 5962-8872501LX
MT5C2561C-45/883C 5962-8872502LX
MT5C2561C-55/883C 5962-8872503LX
MT5C2561C-70/883C 5962-8872504LX
MT5C2561C-35L883C 5962-8854401LX
MT5C2561C-45L883C 5962-8854402LX
MT5C2561C-55L883C 5962-8854403LX
MT5C2561C-70L883C 5962-8854404LX
* Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
SRAM
MT5C2561
MT5C2561
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifi cations without notice.
12
DOCUMENT TITLE
256K x 1 SRAM SRAM MEMORY ARRAY
REVISION HISTORY
Rev # History Release Date Status
2.7 Updated EC Pin Assignment from September 2008 Release
A17 to A5
2.8 Updated Micross Information January 2010 Release
