ICS8741004AGIT - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS8741004I is a high performance

Differential-to-LVDS/HCSL Jitter Attenuator

designed for use in PCI Express™ systems. In

some PCI Express systems, such as those found

in desktop PCs, the PCI Express clocks are

generated from a low bandwidth, high phase noise PLL

frequency synthesizer. In these systems, a jitter attenuator

may be required to attenuate high frequency random and

deterministic jitter components from the PLL synthesizer

and from the system board. The ICS8741004I has 3 PLL

bandwidth modes: 200kHz, 400kHz, and 800kHz. The

200kHz mode will provide maximum jitter attenuation, but

with higher PLL tracking skew and spread spectrum

modulation from the motherboard synthesizer may be

attenuated. 400kHz provides an intermediate bandwidth

that can easily track triangular spread profiles, while provid-

ing good jitter attenuation. 800kHz bandwidth provides the

best tracking skew and will pass most spread profiles, but

the jitter attenuation will not be as good as the lower band-

width modes. Because some 2.5Gb serdes have x20

multipliers while others have x25 multipliers, the 8741004I

can be set for 1:1 mode or 5/4 multiplication mode

(i.e. 100MHz input/125MHz output) using the FSEL pins.

The ICS8741004I uses ICS 3rd Generation FemtoClockTM

PLL technology to achive the lowest possible phase noise.

The device is packaged in a 24 Lead TSSOP package,

making it ideal for use in space constrained applications such

as PCI Express add-in cards.

FEATURES

•Two differential LVDS and two HCSL output pairs

•One differential clock input

•CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

•Output frequency range: 98MHz - 160MHz

•Input frequency range: 98MHz - 128MHz

•VCO range: 490MHz - 640MHz

•Cycle-to-cycle jitter: 15ps (typical)

•3.3V operating supply

•Three bandwidth modes allow the system designer to

make jitter attenuation/tracking skew design trade-offs

•-40°C to 85°C ambient operating temperature

•Available in both standard and lead-free RoHS-compliant

packages

HiPerClockS™

ICS

QA0

nQA0

BLOCK DIAGRAM

BW_SEL

0 = PLL Bandwidth: ~200kHz

Float = PLL Bandwidth: ~400kHz (Default)

1 = PLL Bandwidth: ~800kHz

PLL BANDWIDTH

F_SELA

0 ÷5 (default)

1 ÷4

F_SELB

0 ÷5 (default)

1 ÷4

VCO

490 - 640 MHz

Phase

Detector

M = ÷5 (fixed)

Current Set

OEA

F_SELA

BW_SEL

0 = ~200kHz

Float = ~400kHz

1 = ~800kHz

CLK

nCLK

F_SELB

IREF

OEB PU

QA1

nQA1

QB0

nQB0

QB1

nQB1

Float

PIN ASSIGNMENT

ICS8741004I

24-Lead TSSOP

4.40mm x 7.8mm x 0.92mm

package body

G Package

Top View

nQA1

QA1

VDDO

QA0

nQA0

BW_SEL

VDDA

F_SELA

VDD

OEA

nQB1

QB1

VDDO

QB0

nQB0

IREF

F_SELB

OEB

GND

nCLK

CLK

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL

stupnIstuptuO

AEOBEOxAQn/xAQxBQn/xBQ

00 ZiHZiH

11 delbanEdelbanE

stupnI LLP

htdiwdnaB

WB_LLP

0zHk002~

1zHk008~

taolFzHk004~

rebmuNemaNepyTnoitpircseD

2,11AQ,1AQntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD

22,3V

ODD

rewoP.snipylppustuptuO

5,40AQn,0AQtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD

6RMtupnInwodlluP

erasredivi

dlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA

stuptuodetrevniehtdnawologot)xQ(stuptuoeurtehtgnisuac

teser

stuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgihogot)xQn(

.slevelecafretniLTTVL/SOMCVL.delbanee

7LES_WBtupnI /pulluP

nwodlluP .slevelecafretniLTTVL/SOMCVL.tupnihtdiwdnaBLLPstceleS

8cndesunUtcennocoN

ADD

rewoP.nipylppusgolanA

01ALES_FtupnInwodlluP .stuptuoxAQn/xAQrofniptcelesycneuqerF

.slevelecafretniLTTVL/SOMC

11V

rewoP.nipylppuseroC

21AEOtupnIpulluP

erastuptuoxAQn/xAQeht,HGIHnehW.snipAQrofnipelbanetuptuO

ecnadepmihgihan

ierastuptuoxAQn/xAQeht,WOLnehW.evitca

.slevelecafretniLTTVL/SOMCVL.etats

31KLCtupnInwodlluP.tupnikcolclaitn

ereffidgnitrevni-noN

41KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI

61,51DNGrewoP.dnuorgylppusrewoP

71BEOtupnIp

ulluP

erastuptuoxBQn/xBQeht,HGIHnehW.snipBQrofnipelbanetuptuO

ecnadepmihgihanierastuptuoxBQn/xBQeht,WOLnehW.evitca

.slevelecafretniLTTVL/SOMCVL.etats

81BLES_FtupnInwodlluP .stuptuoxBQn/xBQrofniptcelesycneuqerF

.slevelecafretniLTTVL/SOMCVL

91FERItupnI

574=FERR(rotsisernoisicerpdexifA Ωdnuorgotnipsihtmorf)

edom-tnerruc

laitnereffidrofdesutnerrucecnereferasedivorp

.stuptuokcolc0BQn/0BQ

12,020BQ,0BQntuptuO.slevelecafretniLSCH

.riaptuptuolaitnereffiD

42,321BQn,1BQtuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD

:ETON pulluP dna nwodl

luP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, VO-0.5V to VDDO + 0.5V

Package Thermal Impedance, θJA 70°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

ODD

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 52Am

ADD

tnerruCylppuSgolanA 8Am

ODD

tnerruCylppuStuptuO 56Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI

,B_LSEF,ALES_F

BEO,AEO,RM 2V

3.0+V

LES_WBV

3.0-V

3.0+V

egatloVwoLtupnI

,B_LSEF,ALES_F

BEO,AEO,RM 3.0-8.0V

LES_WB3.0-3.0+V

tnerruChgiHtupnI

BEO,AEOV

V564.3=5Aµ

,RM,LES_WB

B_LSEF,ALES_F V

V564.3=051Aµ

tupnItnerruCwoL

,LES_WB

,BEO,AEO V

V,V564.3=

V0=051-Aµ

,ALES_F,RM

B_LSEF V

V,V564.3=

V0=5-Aµ

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruChgiHtupnI KLCV

V564.3=051Aµ

KLCnV

V564.3=5 Aµ

tnerruCwoLtupnI KLCV

V564.3=051Aµ

KLCnV

V564.3=051-Aµ

egatloVtupnIkaeP-ot-kaeP 51.03.1V

RMC

2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV

58.0-V

VsadenifedsiegatlovedomnommoC:1ETON

VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON

.V3.0+

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO 89061zHM

t)cc(tij1ETON,rettiJelcyC-ot-elcyC 51sp

emiTllaF/esiRtuptuO%08ot%02004sp

cdoelcyCytuDtuptuO 05%

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsih

T:1ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 053Vm

ΔV

egnahCedutingaM 05Vm

egatloVtesffO 3.1V

ΔV

egnahCedutingaM 04Vm

TABLE 4E. HCSL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C, RREF = 475Ω

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruCtuptuO 98.31Am

egatloVhgiHtuptuO 37.0V

egatloVwoLtuptuO 30.0V

tnerruCegakaeLecnadepmIhgiH 01-01Aµ

egatloVrevossorCtuptuO 052055Vm

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

CYCLE-TO-CYCLE JITTER

DIFFERENTIAL INPUT LEVEL

3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

3.3V ± 5%

CMR

Cross Points

GND

CLK

nCLK

VDD

Clock

Outputs 20%

80% 80%

20%

SWING

DIFFERENTIAL OUTPUT VOLTAGE SETUP

tPERIOD

PERIOD

odc = x 100%

QAx,

QBx

nQAx,

nQBx

➤

QAx,

QBx

nQAx,

nQBx

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

tcycle n tcycle n+1

SCOPE

nQx

LVDS

3.3V±5%

POWER SUPPLY

Float GND

OFFSET VOLTAGE SETUP

OUTPUT RISE/FALL TIME

➤

100

out

LVD S

DC Input VOD/Δ VOD

VDD

out

LVDS

DC Input

➤

/Δ V

SCOPE

HCSL

3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT

3.3V±5%

VDD

GND

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLK

nCLK

VDD

POWER SUPPLY FILTERING T ECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8741004I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VDD, VDDA, and VDDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VDDA pin. The 10Ω

resistor can also be replaced by a ferrite bead. FIGURE 1. POWER SUPPLY FILTERING

10Ω

VDDA

10μF

.01μF

3.3V

.01μF

VDD

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 3A to 3D show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in Figure 3A, the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

INPUTS:

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS OUTPUT

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, there

should be no trace attached.

HCSL OUTPUT

All unused HCSL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

LVDS DRIVER T ERMINATION

A general LVDS interface is shown in Figure 4. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

100 Ohm Differiential Transmission Line

100

3.3V

LVDS_Driv er

3.3V

FIGURE 4. TYPICAL LVDS DRIVER T ERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8741004I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8741004I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

•Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (25mA + 8mA) = 114.34mW

•Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 65mA = 225.22mW

Total Power_MAX = 294.52mW + 381.15mW = 339.56mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used.

Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per

Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.340W * 63°C/W = 106.4°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air

flow, and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θθ

θθ

θJA FOR 24-LEAD TSSOP, FORCED CONVECTION

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 63°C/W 60°C/W

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS8741004I is: 1318

TABLE 7. θJAVS. AIR FLOW T ABLE FOR 24 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 63°C/W 60°C/W

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

N42

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D07.709.7

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

Integrated

Circuit

Systems, Inc.

8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006

ICS8741004I

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and

may be registered in certain jurisdictions.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

IGA4001478SCIIGA4001478SCIPOSSTdaeL42ebutC°58otC°04

TIGA4001478SCIIGA4001478SCIPOSSTdaeL42leer&epat0052C°58otC°04-

FLIGA4001478SCILIA4001478SCIPOSST"eerF-daeL"

daeL42ebutC°58otC°04-

TFLIGA4001478SCILIA4001478SCIPOSST"eerF-daeL"daeL42leer&epat0052C°58otC°04-

.tnailpmocS

HoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON