PRELIMINARY Integrated Circuit Systems, Inc. ICS8741004I PCI EXPRESSTM JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS8741004I is a high performance Differential-to-LVDS/HCSL Jitter Attenuator HiPerClockSTM designed for use in PCI ExpressTM systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS8741004I has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the 8741004I can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins. * Two differential LVDS and two HCSL output pairs ICS * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 160MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 15ps (typical) * 3.3V operating supply * Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages PLL BANDWIDTH The ICS8741004I uses ICS 3rd Generation FemtoClockTM PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (Default) 1 = PLL Bandwidth: ~800kHz BLOCK DIAGRAM PIN ASSIGNMENT OEA PU F_SELA PD QA0 BW_SEL Float 0 = ~200kHz Float = ~400kHz 1 = ~800kHz F_SELA 0 /5 (default) 1 /4 QA1 CLK PD nCLK PU nQA0 Phase Detector VCO nQA1 490 - 640 MHz QB0 M = /5 (fixed) F_SELB 0 /5 (default) 1 /4 PD 24 23 22 21 20 19 18 17 16 15 14 13 nQB1 QB1 VDDO QB0 nQB0 IREF F_SELB OEB GND GND nCLK CLK ICS8741004I QB1 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View MR PD IREF 1 2 3 4 5 6 7 8 9 10 11 12 nQB0 nQB1 F_SELB nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA Current Set OEB PU The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8741004AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2006 1 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQA1, QA1 Output Type Differential output pair. LVDS interface levels. 3, 22 VDDO Power Output supply pins. 4, 5 QA0, nQA0 Output 6 MR Input 7 BW_SEL Input 8 nc Unused 9 VDDA Power 10 F_SELA Input 11 VDD Power 12 OEA Input 13 CLK Input 14 nCLK Input 15, 16 GND Power 17 OEB Input 18 F_SELB Input 19 IREF Input 20, 21 nQB0, QB0 Output 23, 24 QB1, nQB1 Output Description Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pulldown No connect Analog supply pin. Frequency select pin for QAx/nQAx outputs. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx/nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. A fixed precision resistor (RREF = 475) from this pin to ground provides a reference current used for differential current-mode QB0/nQB0 clock outputs. Differential output pair. HCSL interface levels. Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs Inputs Outputs OEA OE B 0 0 1 1 8741004AGI TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL QBx/nQBx PLL_BW PLL Bandwidth HiZ HiZ 0 ~200kHz Enabled Enabled 1 ~800kHz Float ~400kHz QAx/nQAx www.icst.com/products/hiperclocks.html 2 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 70C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VDDA Analog Supply Voltage 3.135 3. 3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 25 mA IDDA Analog Supply Current 8 mA IDDO Output Supply Current 65 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter VIH Test Conditions Maximum Units 2 VDD + 0.3 V Input High Voltage VDD - 0.3 VDD + 0.3 V Input Low Voltage F_SELA, FESL_B, MR, OEA, OEB -0.3 0.8 V BW_SEL -0.3 +0.3 V VDD = VIN = 3.465V 5 A VDD = VIN = 3.465V 150 A BW_SEL VIL Minimum Typical F_SELA, FESL_B, MR, OEA, OEB IIH Input High Current IIL Input Low Current OEA, OEB BW_SEL, MR, F_SELA, FESL_B BW_SEL, OEA, OEB, MR, F_SELA, FESL_B VDD = 3.465V, VIN = 0V -150 A VDD = 3.465V, VIN = 0V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V Minimum Typical 3 150 A A 150 -150 0.15 www.icst.com/products/hiperclocks.html Units 5 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. 8741004AGI Maximum A A 1.3 V VDD - 0.85 V REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter VOD Differential Output Voltage Test Conditions Minimum Typical Maximum Units 350 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.3 V VOS VOS Magnitude Change 40 mV TABLE 4E. HCSL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C, RREF = 475 Symbol Parameter IOH Output Current Test Conditions Minimum Typical 13.89 Maximum Units mA VOH Output High Voltage 0.73 V VOL Output Low Voltage 0.03 V IOZ High Impedance Leakage Current -10 10 A VOX Output Crossover Voltage 250 550 mV Maximum Units 160 MHz TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency t jit(cc) Cycle-to-Cycle Jitter, NOTE 1 tR / tF Output Rise/Fall Time Test Conditions Minimum 98 20% to 80% odc Output Duty Cycle NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. 8741004AGI Typical www.icst.com/products/hiperclocks.html 4 15 ps 400 ps 50 % REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 3.3V5% 3.3V 5% SCOPE VDD SCOPE Qx 3.3V5% POWER SUPPLY + Float GND - Qx HCSL LVDS nQx GND 0V 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT nQAx, nQBx QAx, QBx VDD t PW nCLK t V PP PERIOD V Cross Points CMR CLK odc = t PW x 100% t PERIOD GND OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL INPUT LEVEL nQAx, nQBx 80% QAx, QBx 80% VSW I N G tcycle n tcycle n+1 Clock Outputs 20% 20% tR t jit(cc) = tcycle n -tcycle n+1 tF 1000 Cycles OUTPUT RISE/FALL TIME CYCLE-TO-CYCLE JITTER VDD VDD out LVDS 100 DC Input LVDS VOD/ VOD out out DC Input out VOS/ VOS DIFFERENTIAL OUTPUT VOLTAGE SETUP 8741004AGI OFFSET VOLTAGE SETUP www.icst.com/products/hiperclocks.html 5 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8741004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead. 3.3V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8741004AGI www.icst.com/products/hiperclocks.html 6 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. HCSL OUTPUT All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 8741004AGI www.icst.com/products/hiperclocks.html 7 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION 8741004AGI www.icst.com/products/hiperclocks.html 8 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8741004I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8741004I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (25mA + 8mA) = 114.34mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 65mA = 225.22mW Total Power_MAX = 294.52mW + 381.15mW = 339.56mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.340W * 63C/W = 106.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 24-LEAD TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 8741004AGI 0 200 500 70C/W 63C/W 60C/W www.icst.com/products/hiperclocks.html 9 REV. A MAY 31, 2006 PRELIMINARY ICS8741004I Integrated Circuit Systems, Inc. PCI EXPRESSTM JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70C/W 63C/W 60C/W TRANSISTOR COUNT The transistor count for ICS8741004I is: 1318 8741004AGI www.icst.com/products/hiperclocks.html 10 REV. A MAY 31, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX ICS8741004I PCI EXPRESSTM JITTER ATTENUATOR FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8741004AGI www.icst.com/products/hiperclocks.html 11 REV. A MAY 31, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS8741004I PCI EXPRESSTM JITTER ATTENUATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8741004AGI ICS8741004AGI 24 Lead TSSOP tube -40C to 85C ICS8741004AGIT ICS8741004AGI 24 Lead TSSOP 2500 tape & reel -40C to 85C ICS8741004AGILF ICS8741004AIL 24 Lead "Lead-Free" TSSOP tube -40C to 85C ICS8741004AGILFT ICS8741004AIL 24 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8741004AGI www.icst.com/products/hiperclocks.html 12 REV. A MAY 31, 2006