CT12864AC667.M8FH8 - Crucial Technology

June, 2012 − Rev. 10

1Publication Order Number:

N25S830HA/D

N25S830HA

256 kb Low Power Serial

SRAMs

32 k x 8 Bit Organization

Introduction

The ON Semiconductor serial SRAM family includes several

integrated memory devices including this 256 kb serially accessed

Static Random Access Memory, internally organized as 32 k words by

8 bits. The devices are designed and fabricated using

ON Semiconductor’s advanced CMOS technology to provide both

high−speed performance and low power. The devices operate with a

single chip select (CS) input and use a simple Serial Peripheral

Interface (SPI) serial bus. A single data in and data out line is used

along with a clock to access data within the devices. The N25S830HA

devices include a HOLD pin that allows communication to the device

to be paused. While paused, input transitions will be ignored. The

devices can operate over a wide temperature range of −40°C to +85°C

and can be available in several standard package offerings.

Features

•Power Supply Range: 2.7 to 3.6 V

•Very Low Standby Current: Typical Isb as low as 1 mA

•Very Low Operating Current: As low as 3 mA

•Simple Memory Control:

Single chip select (CS)

Serial input (SI) and serial output (SO)

•Flexible Operating Modes:

Word read and write

Page mode (32 word page)

Burst mode (full array)

•Organization: 32 K x 8 bit

•Self Timed Write Cycles

•Built−in Write Protection (CS High)

•HOLD Pin for Pausing Communication

•High Reliability: Unlimited write cycles

•Green SOIC and TSSOP

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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Device Package

ORDERING INFORMATION

N25S830HAS22I SOIC−8

(Pb−Free)

Shipping†

100 Units / Tube

N25S830HAT22I TSSOP−8

(Pb−Free)

100 Units / Tube

N25S830HAS22IT SOIC−8

(Pb−Free)

3000 / Tape &

Reel

N25S830HAT22IT TSSOP−8

(Pb−Free)

3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

TSSOP−8

T SUFFIX

CASE 948AL

MARKING

DIAGRAMS

D125

XXXXYZZ

XXXX = Date Code

Y = Assembly Code

ZZ = Lot Traceability

SOIC−8

S SUFFIX

CASE 751BD

D115

XXXXYZZ

N25S830HA

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VSS

VCC

SCK

HOLD

VCC

SCK

HOLD

VSS

SOIC−8

TSSOP−8

Figure 1. Pin Connections

(Top View)

Table 1. DEVICE OPTIONS

Part Number Density

Power

Supply (V)

Speed

(MHz) Package

Typical Standby

Current

Read/Write

Operating Current

N25S830HAS2

256 Kb 3.0 20

SOIC

1 mA3 mA @ 1 Mhz

N25S830HAT2 TSSOP

Table 2. PIN NAMES

Pin Name Pin Function

CS Chip Select Input

SCK Serial Clock Input

SI Serial Data Input

SO Serial Data Output

HOLD Hold Input

NC No Connect

VCC Power

VSS Ground

SRAM

Array

Decode

Logic

Clock

Circuitry

SCK

Data In

Receiver

Data Out

Buffer

Figure 2. Functional Block Diagram

HOLD

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Table 3. ABSOLUTE MAXIMUM RATINGS

Item Symbol Rating Unit

Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC + 0.3 V

Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V

Power Dissipation PD500 mW

Storage Temperature TSTG –40 to 125 °C

Operating Temperature TA−40 to +85 °C

Soldering Temperature and Time TSOLDER 260°C, 10 sec °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 4. OPERATING CHARACTERISTICS (Over Specified Temperature Range)

Item Symbol Test Conditions Min

Typ

(Note 1) Max Unit

Supply Voltage VCC 2.7 3.6 V

Input High Voltage VIH 0.7 x VCC VCC + 0.3 V

Input Low Voltage VIL −0.3 0.8 V

Output High Voltage VOH IOH = −0.4 mA VCC – 0.5 V

Output Low Voltage VOL IOL = 1 mA 0.2 V

Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 0.5 mA

Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 0.5 mA

Read/Write Operating Current ICC1 F = 1 MHz, IOUT = 0 3 mA

ICC2 F = 10 MHz, IOUT = 0 6 mA

ICC3 F = fCLK MAX, IOUT = 0 10 mA

Standby Current ISB CS = VCC, VIN = VSS or VCC 1 4 mA

1. Typical values are measured at Vcc = Vcc Typ., TA = 25°C and are not 100% tested.

Table 5. CAPACITANCE (Note 2)

Item Symbol Test Condition Min Max Unit

Input Capacitance CIN VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF

I/O Capacitance CI/O VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF

2. These parameters are verified in device characterization and are not 100% tested

N25S830HA

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Table 6. TIMING TEST CONDITIONS

Item

Input Pulse Level 0.1 VCC to 0.9 VCC

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Levels 0.5 VCC

Output Load CL = 100 pF

Operating Temperature −40 to +85°C

Table 7. TIMING

Item Symbol Min Max Units

Clock Frequency fCLK 20 MHz

Clock Rise Time tR2ms

Clock Fall Time tF2ms

Clock High Time tHI 25 ns

Clock Low Time tLO 25 ns

Clock Delay Time tCLD 25 ns

CS Setup Time tCSS 25 ns

CS Hold Time tCSH 50 ns

CS Disable Time tCSD 25 ns

SCK to CS tSCS 5 ns

Data Setup Time tSU 10 ns

Data Hold Time tHD 10 ns

Output Valid From Clock Low tV25 ns

Output Hold Time tHO 0 ns

Output Disable Time tDIS 20 ns

HOLD Setup Time tHS 10 ns

HOLD Hold Time tHH 10 ns

HOLD Low to Output High−Z tHZ 10 ns

HOLD High to Output Valid tHV 50 ns

N25S830HA

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MSB in

SCK

SI LSB in

High−Z

Figure 3. Serial Input Timing

MSB out

SCK

SO LSB out

Don’t Care

Figure 4. Serial Output Timing

n+2

SCK

SO n+1 n High−Znn−1

nn−1

n+2 n+1 n Don’t Care

Figure 5. Hold Timing

tSCS

tCSD

tCSH

tCLD

tCSS

tHD

tSU

tDIS

tCSH

tLO tHI

HOLD

tSU

tHH

tHS

tHV

tHS

tHH

tHZ

N25S830HA

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Table 8. CONTROL SIGNAL DESCRIPTIONS

Signal Name I/O Description

CS Chip Select IA low level selects the device and a high level puts the device in standby mode. If CS is brought

high during a program cycle, the cycle will complete and then the device will enter standby mode.

When CS is high, SO is in high−Z. CS must be driven low after power−up prior to any sequence

being started.

SCK Serial Clock ISynchronizes all activities between the memory and controller. All incoming addresses, data and

instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge

of SCK.

SI Serial Data In IReceives instructions, addresses and data on the rising edge of SCK.

SO Serial Data Out OData is transferred out after the falling edge of SCK.

HOLD Hold I A high level is required for normal operation. Once the device is selected and a serial sequence is

started, this input may be taken low to pause serial communication without resetting the serial se-

quence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the

Hold function will not be invoked until the next SCK high to low transition. The device must remain

selected during this sequence. SO is high−Z during the Hold time and SI and SCK are inputs are

ignored. To resume operations, HOLD must be pulled high while the SCK pin is low.

Lowering the HOLD input at any time will take to SO output to High−Z.

Functional Operation

Basic Operation

The 256 Kb serial SRAM is designed to interface directly

with a standard Serial Peripheral Interface (SPI) common on

many standard micro−controllers. It may also interface with

other non−SPI ports by programming discrete I/O lines to

operate the device.

The serial SRAM contains an 8−bit instruction register

and is accessed via the SI pin. The CS pin must be low and

the HOLD pin must be high for the entire operation. Data is

sampled on the first rising edge of SCK after CS goes low.

If the clock line is shared, the user can assert the HOLD input

and place the device into a Hold mode. After releasing the

HOLD pin, the operation will resume from the point where

it was held.

The following table contains the possible instructions and

formats. All instructions, addresses and data are transferred

MSB first and LSB last.

Table 9. INSTRUCTION SET

Instruction Instruction Format Description

READ 0000 0011 Read data from memory starting at selected address

WRITE 0000 0010 Write data to memory starting at selected address

RDSR 0000 0101 Read status register

WRSR 0000 0001 Write status register

READ Operations

The serial SRAM READ is selected by enabling CS low.

First, the 8−bit READ instruction is transmitted to the device

followed by the 16−bit address with the MSB being a don’t

care. After the READ instruction and addresses are sent, the

data stored at that address in memory is shifted out on the SO

pin after the output valid time from the clock edge.

If operating in page mode, after the initial word of data is

shifted out, the data stored at the next memory location on

the page can be read sequentially by continuing to provide

clock pulses. The internal address pointer is automatically

incremented to the next higher address on the page after each

word of data is read out. This can be continued for the entire

page length of 32 words long. At the end of the page, the

addresses pointer will be wrapped to the 0 word address

within the page and the operation can be continuously

looped over the 32 words of the same page.

If operating in burst mode, after the initial word of data is

shifted out, the data stored at the next memory location can

be read sequentially by continuing to provide clock pulses.

The internal address pointer is automatically incremented to

the next higher address after each word of data is read out.

This can be continued for the entire array and when the

highest address is reached (7FFFh), the address counter

wraps to the address 0000h. This allows the burst read cycle

to be continued indefinitely.

All READ operations are terminated by pulling CS high.

N25S830HA

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Instruction

04325169810711

SCK

15 14 13 12 21 0

76543210

High−Z

16−bit address

Data Out

21 2322 24 28 29 30 3126 2725

000 00 011

Figure 6. Word READ Sequence

Instruction

04325169810711

SCK

15 14 13 12 210

76543210High−Z

16−bit address

Data Out from ADDR 1

21 2322 24 28 29 30 3126 2725

000 00011

76543210

Data Out from ADDR 2

76543210 76543210

...

32 3433 35 39 40 41 4237 3836 43 4544 46 47

Don’t Care

ADDR 1

Data Out from ADDR n

Figure 7. Page and Burst READ Sequence

Data Out from ADDR 3

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Figure 8. Page READ Sequence

Page X

Word Y

Page XPage X

Word Y+1

Page X

Word 31

Page X

Word 0

Page X

Word 1

Data Words: sequential, at the end of the page the

address wraps back to the beginning of the page

16−bit address

Page address (X)

Word address (Y)

Word Y+2

Figure 9. Burst READ Sequence

Page X

Word Y

Page X

Word 31

Page X

Word Y+1

Page X

Word 0

Page X+1

Word Y

Page X+1

Word Y+1

16−bit address

Page address (X)

Word address (Y)

Data Words: sequential, at the end of the page the address wraps to the beginning

of the page and continues incrementing up to the starting word address. At that

time, the address increments to the next page and the burst continues.

. . .

Page X

Word 1

. . .

Page X

Word Y−1

WRITE Operations

The serial SRAM WRITE is selected by enabling CS low.

First, the 8−bit WRITE instruction is transmitted to the

device followed by the 16−bit address with the MSB being

a don’t care. After the WRITE instruction and addresses are

sent, the data to be stored in memory is shifted in on the SI

pin.

If operating in page mode, after the initial word of data is

shifted in, additional data words can be written as long as the

address requested is sequential on the same page. Simply

write the data on SI pin and continue to provide clock pulses.

The internal address pointer is automatically incremented to

the next higher address on the page after each word of data

is written in. This can be continued for the entire page length

of 32 words long. At the end of the page, the addresses

pointer will be wrapped to the 0 word address within the

page and the operation can be continuously looped over the

32 words of the same page. The new data will replace data

already stored in the memory locations.

If operating in burst mode, after the initial word of data is

shifted in, additional data words can be written to the next

sequential memory locations by continuing to provide clock

pulses. The internal address pointer is automatically

incremented to the next higher address after each word of

data is read out. This can be continued for the entire array

and when the highest address is reached (7FFFh), the

address counter wraps to the address 0000h. This allows the

burst write cycle to be continued indefinitely. Again, the new

data will replace data already stored in the memory

locations.

All WRITE operations are terminated by pulling CS high.

Instruction

04325169810711

SCK

15 14 13 12 21076543210

High−Z

16−bit address Data In

21 2322 24 28 29 30 3126 2725

000 00010 ...

Figure 10. Word WRITE Sequence

N25S830HA

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Instruction

04325169810711

SCK

15 14 13 12 21076543210

High−Z

16−bit address

Data In to ADDR 1

21 2322 24 28 29 30 3126 2725

000 00010

76543210

Data In to ADDR 2

76543210 76543210

...

32 3433 35 39 40 41 4237 3836 43 4544 46 47

ADDR 1

Data In to ADDR 3 Data In to ADDR n

High−Z

Figure 11. Page and Burst WRITE Sequence

16−bit address

Page address (X)

Word address (Y)

Page X

Word Y

Page X

Word Y+2

Page X

Word Y+1

Page X

Word 31

Page X

Word 0

Page X

Word 1

Data Words: sequential, at the end of the page the

address wraps back to the beginning of the page

High−Z

Figure 12. Page WRITE Sequence

Page X

Word Y

Page X

Word 31

Page X

Word Y+1

Page X

Word 0

Page X+1

Word Y

Page X+1

Word Y+1

16−bit address

Page address (X)

Word address (Y)

Data Words: sequential, at the end of the page the address wraps to the beginning of the page and

continues incrementing up to the starting word address. At that time, the address increments to the

next page and the burst continues.

. . .

Page X

Word 1

. . .

Page X

Word Y−1

High−Z

Figure 13. Burst WRITE Sequence

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WRITE Status Register Instruction (WRSR)

This instruction provides the ability to write the status

of the register bits must be set to a low ‘0’ if any of the other

bits are written. The timing sequence to write to the status

status register.

Instruction

04325169810711

SCK

76543210

High−Z

Status Register Data In

00 000 10

12 13 14 15

Figure 14. WRITE Status Register Sequence

Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

Hold Function

0 = Hold (Default)

1 = No Hold

Reserved

Must = 0

Reserved

Must = 0

Mode

0 0 = Word Mode (Default)

1 0 = Page Mode

0 1 = Burst Mode

1 1 = Reserved Figure 15. Status Register

READ Status Register Instruction (RDSR)

This instruction provides the ability to read the Status register. The register may be read at any time by performing the

following timing sequence.

Instruction

04325169810711

SCK

76543210

High−Z

Status Register Data Out

00 000 10

12 13 14 15

Figure 16. READ Status Register Instruction (RDSR)

Power−Up State

The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level

on CS is required to enter an active state.

N25S830HA

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

N25S830HA

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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Phone: 81−3−5817−1050

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