TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
D
Wide Analog Channel Input: 0 V to AVDD
D
Eight Analog Input Channels
D
Channel Auto-Scan
D
Differential Nonlinearity Error: < ±1 LSB
D
Integral Nonlinearity Error: < ±1 LSB
D
Signal-to-Noise and Distortion Ratio: 57 dB
D
Single 2.7-V to 5.5-V Supply Operation
D
Very Low Power: 40 mW at 5.5 V,
8 mW at 2.7 V
D
Autopower-Down: 300 µA Max
D
Software Power Down: 10 µA Max
D
Glueless Serial Interface to TMS320 DSPs
and (Q)SPI Compatible Microcontrollers
D
Programmable Internal Reference Voltage:
3.8-V Reference for 5-V Operation,
2.3-V Reference for 3-V Operation
applications
D
Mass Storage and Hard Disk Drive
D
Automotive
D
Digital Servos
D
Process Control
D
General-Purpose DSP
D
Image Sensor Processing
description
The TLV1570 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, an on-chip reference, and a high-speed serial interface. The device contains an on-chip
control register allowing control of channel selection, conversion start, reference voltage levels, and power
down via the serial port. The MUX is independently accessible, which allows the user to insert a signal
conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and the ADC.
Therefore one signal conditioning circuit can be used for all eight channels.
The TLV1570 operates from a single 2.7-V to 5.5-V power supply. The device accepts an analog input range
from 0 V to AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate. Power dissipation is only
8 mW with a 2.7-V supply or 40 mW with a 5.5-V supply. The device features an autopower-down mode that
automatically powers down to 300 µA, 10 ns after a conversion is performed. With software power down
enabled, the device is further powered down to only 10 µA.
The TLV1570 communicates with digital microprocessors via a simple 4- or 5-wire serial port that interfaces
directly to Texas Instruments TMS320 DSPs, and SPI and QSPI compatible microcontrollers without using
additional glue logic.
A very high throughput rate, a simple serial interface, and low power consumption make the TLV1570 an ideal
choice for high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS
PACKAGED DEVICES
TASMALL OUTLINE
(DW) SMALL OUTLINE
(PW)
0°C to 70°C TLV1570CDW TLV1570CPW
–40°C to 85°C TLV1570IDW TLV1570IPW
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SPI and QSPI are trademarks of Motorola, Inc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CH4
CH3
CH2
CH1
CH0
DVDD
DGND
FS
SCLK
SDIN
AIN
MO
CH5
CH6
CH7
AVDD
AGND
REF
CS
SDOUT
DW OR PW PACKAGE
(TOP VIEW)
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SCLK
SDIN
CS
SDOUT
FS
MUX
REFERENCE
10-BIT
SAR ADC
I/O REGISTERS
AND CONTROL LOGIC
AVDD DVDD
AGND DGND
MO AIN
REF
AGND
REF+
REF–
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 14 Analog ground
AIN 20 IADC analog input
AVDD 15 Analog supply voltage, 2.7 V to 5.5 V
CH0 – CH7 5,4,3,2,1,
18,17,16 IAnalog input channels 0 – 7
CS 12 IChip select. A low level signal on CS enables the TLV1570. A high level signal on CS disables the device
and disconnects power to the TLV1570.
DGND 7Digital ground
DVDD 6Digital supply voltage, 2.7 V to 5.5 V
FS 8 I Frame sync. The falling edge of the frame sync pulse from a DSP indicates the start of a serial data frame
shifted out of the TLV1570. FS is pulled high when interfaced to a microcontroller .
MO 19 OOn-chip MUX analog output
REF 13 IReference voltage input. The voltage applied to REF defines the input span of the TLV1570. In external
reference mode, a 0.1 µF decoupling capacitor must be placed between the reference and AGND. This is
not required for internal reference mode.
SCLK 9 I Serial clock input. SCLK synchronizes the serial data transfer and is also used for internal data conversion.
SDIN 10 ISerial data input used to configure the internal control register.
SDOUT 11 OSerial data output. A/D conversion results are output at SDOUT.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
analog-to-digital converter
The TLV1570 ADC uses the SAR architecture described in this section. The CMOS threshold detector in the
successive-approximation conversion system determines the value of each bit by examining the charge on a
series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input
is sampled by closing the SC switch and all ST switches simultaneously. This action charges all of the capacitors
to the input voltage.
SC
Threshold
Detector
Node 512
REF–
REF+
ST
512
VI
To Output
Latches
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
REF–
ST
REF+
ST
REF+
REF–
ST
REF+
REF–
ST
11248128256
REF–
NOTE: REF– is tied to AGND
Figure 1. Simplified Model of the Successive-Approximation System
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage (REF– is tied to AGND). In the switching sequence, ten capacitors are examined separately until all ten
bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase,
the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the
REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the
voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC),
a bit 0 is placed in the output register and the 512-weight capacitor is switched to REF–. If the voltage at the
summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the
512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation
process. The process is repeated for the 256-weight capacitor , the 128-weight capacitor, and so forth down the
line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
In the case of the TLV1570, REF– is tied to ground and REF+ is connected to the REF input.
The TLV1570 can be programmed to use the on-chip internal reference (DI6=1). The user can select between
two values of internal reference, 2.3 V or 3.8 V, using the control bit DI5.
During internal reference mode, the reference voltage is not output on the REF pin. Therefore it cannot be
decoupled to analog ground (AGND), which acts as the negative reference for the ADC, using an external
capacitor. Hence this mode requires the ground noise to be very low. The REF pin can be left open in this mode.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sampling frequency, fs
The TLV1570 requires 16 SCLKs for each sampling and conversion, therefore the equivalent maximum
sampling frequency achievable with a given SCLK frequency is:
fs(MAX) = (1/16)fSCLK
power down
The TL V1570 offers two different power-down options. With autopower-down mode enabled, (DI4=0) the ADC
proceeds to power down if FS is not detected on the 17th falling SCLK edge of a cycle (a cycle starts with FS
being detected on a falling edge of SCLK) in DSP mode and after 16 SCLKs in µC mode. The TLV1570 will
recover from auto power down when FS goes high in DSP mode or when the next SCLK comes in µC mode.
In the case of software power down, the ADC goes to the software power-down state one cycle after CR.DI15
is set to 1. Unlike autopower down which recovers in 1 SCLK, software power down takes 16 SCLKs to recover.
DESCRIPTION AUTOPOWER DOWN SOFTWARE
POWERDOWN
CS = DVDD
Maximum power down dissipation current 300 µA 10 µA
Comparator Power down Powerdown
Clock buffer†Power down Powerdown
Reference Active Powerdown
Register Not saved Not saved
Minimum power down time 1 SCLK 1 µs
Minimum resume time 1 SCLK 800 ns
Power down
DSP mode No FS present one SCLK after previous conversion completed CR.DI15 set to 1
Po
w
er
do
w
n
Microprocessor mode (FS = 1) SCLK stopped after previous conversion completed CR.DI15 set to 1
Power u
pDSP mode FS present CR.DI15 set to 1
Po
w
er
u
p
Microprocessor mode (FS = 1) SCLK present CR.DI15 set to 1
†Only in DSP mode is input buffer of clock in power-down mode.
‡The software power down enable/disable bit is not acted until the start of the next cycle (see section
configuring the TLV1570 for more information
.
configuring the TLV1570
The TLV1570 is to be configured by writing the control bits to SDIN. The configuration will not take affect until
the next cycle. A new configuration is needed for each conversion. Once the channel input and other options
are selected, the conversion takes place in the next cycle. Conversion results are shifted out as conversion
progresses ( see Figure 2).
17 32
One Cycle Second Cycle
tstconv tstconv
Result 0 Result 1
Configure Data 1 Configure Data 2
SCLK
SDOUT
SDIN
Figure 2. TLV1570 Configuration Cycle Timing
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
configuration register (CR) definition
BIT DESCRIPTION 5 V 3 V
Software power down: X X
DI15 0:
1: Normal
Power down enabled X X
DI14 Reads out values of the internal register, 1 – read. Only DI15 – DI1 are read out. X X
These two bits select the self-test voltage to be applied to the ADC input during next clock cycle: X X
00: Allow AIN to come in normally
DI13, DI12 01: Apply AGND to AIN
10: Apply VREF/2 to AIN
11: N/A
Choose speed application X X
DI11 0: High speed (higher power consumption)
1: Low speed (lower power consumption)
This bit enables channel auto-scan function. X X
DI10 0:
1: Autoscan disabled
Autoscan enabled
DI9 – DI7 These three bits select which of the eight
channels is to be used (if DI10 = 0). DI9, DI8 These two bits select the channel swept
sequence used by auto scan mode (if DI10 = 1) X X
000: Channel 0 selected as input 00: Analog inputs CH0, CH1, CH2, ….., CH7
sequentially selected
001: Channel 1 selected as input 01: Analog inputs CH1, CH3, CH5, CH7
sequentially selected
DI9, DI8, DI7 010: Channel 2 selected as input 10: Analog inputs CH0, CH2, CH4, CH6
sequentially selected
011: Channel 3 selected as input 11: Analog inputs CH7, CH6, CH5, ….., CH0
sequentially selected
100: Channel 4 selected as input DI7 Auto-scan reset
101: Channel 5 selected as input 0: No reset
110: Channel 6 selected as input 1: Reset autoscan sequence
111: Channel 7 selected as input
Selects Internal or external reference voltage: X X
DI6 0:
1: External
Internal
Selects internal reference voltage value to be applied to the ADC during next conversion cycle.
DI5 0: 2.3 V X
1: 3.8 V X
Enables/disables autopower-down function: X X
DI4 1: Enable
0: Disable
DI3 Performance optimizer – linearity
0: AVDD = 5.5 V to 3.6 V
1: AVDD = 3.5 V to 2.7 V X X
DI2 Always write 0 (reserved bit) X X
DI1 Always write 0 (reserved bit) X X
DI0 Always write 0 (reserved bit) X X
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
initialization-software sequence
This sequence shows the default settings, unless otherwise specified. The ADC requires that the user write to
it every cycle. There is a cycle delay before control bits are implemented.
Example 1. Normal Sample Mode With Internal Reference
CYCLE WRITE TO
SDIN CHANNEL
SAMPLED OUTPUT FROM
SDOUT COMMENT
1st 0040h N/A Invalid No analog input channel sampled
2nd 01C0h N/A Invalid No analog input channel sampled
3rd 0040h 3From Channel 3
4th 8040h 0From Channel 0 Software power down enabled
5th 0040h N/A Invalid Software power-down mode, no analog input channel sampled
W ait 800 ns Recovery time, no analog input channel sampled (16 SCLKs if AVDD = 5 V and
fCLK = 20 MHz)
6th 0140h N/A Invalid Recovery time, no analog input channel sampled
7th 0040h 2From Channel 2
Example 2. Auto Scan Mode
CYCLE WRITE TO
SDIN CHANNEL
SAMPLED OUTPUT FROM
SDOUT COMMENT
1st 0480h N/A Invalid Autoscan reset enabled, no analog input channel sampled
2nd 0480h N/A Invalid No analog input channel sampled
3rd 0400h 0From Channel 0
4th 0400h 1From Channel 1
5th 0400h 2From Channel 2
6th 0400h 3From Channel 3
7th 0400h 4From Channel 4
8th 0400h 5From Channel 5
9th 0400h 6From Channel 6
10th 0400h 7From Channel 7
11th 0400h 0From Channel 0
NOTE: If software power down is enabled during auto-scan mode, the next channel in the sequence is skipped.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
initialization-software sequence (continued)
Example 3. Auto-Scan Mode
This example shows a change in sequence in the middle of the current sequence. The following shows that after
the initial autoscan reset, a reset is not necessary again when switching channel sequences.
CYCLE WRITE TO
SDIN CHANNEL
SAMPLED OUTPUT FROM
SDOUT COMMENT
1st 0480h N/A N/A No analog input channel sampled
2nd 0480h N/A N/A Autoscan reset enabled, no analog input channel sampled
3rd 0400h 0From Channel 0 Start of sequence 0
4th 0700h 1From Channel 1 Enable channel sequence 3 (no auto-scan reset required)
5th 0700h 7From Channel 7 Start of sequence 3
6th 0700h 6From Channel 6
7th 0700h 5From Channel 5
8th 0700h 4From Channel 4
9th 0700h 3From Channel 3
10th 0700h 2From Channel 2
11th 0700h 1From Channel 1
12th 0700h 0From Channel 0
Example 4. Auto-Scan Mode
This example shows a switch in sequence in the course of a sequence. The following shows that a particular
sequence does not have to be continued if remaining channels do not need to be sampled (i.e., only channel
1 through channel 5 sampled, not channels 6, 7, 8)
CYCLE WRITE TO
SDIN CHANNEL
SAMPLED OUTPUT FROM
SDOUT COMMENT
1st 0480h N/A N/A No analog input channel sampled
2nd 0480h N/A N/A Autoscan reset enabled, no analog input channel sampled
3rd 0400h 0From Channel 0
4th 0400h 1From Channel 1
5th 0400h 2From Channel 2
6th 0400h 3From Channel 3
7th 0400h 4From Channel 4
8th 0480h 5From Channel 5 Autoscan reset enabled
9th 0400h 0From Channel 0 Sequence is reset to channel 0
10th 0400h 1From Channel 1
11th 0400h 2From Channel 2
The TLV1570 is a 800-ns 10-bit 8-analog input channel analog-to-digital converter with a throughput of up to
1.25 MSPS at 5 V and up to 625 KSPS at 3 V respectively. T o run at its fastest conversion rate, it must be clocked
at 20 MHz at 5-V or 10 MHz at 3-V. The TLV1570 can be easily interfaced to microcontrollers, ASICs, DSPs,
or shift registers. The TL V1570 serial interface is designed to be fully compatible with serial peripheral interface
(SPI) and TMS320 DSP serial ports. No additional hardware is required to interface between the TL V1570 and
a microcontroller (µCs) with a SPI serial port or a TMS320 DSP. However , the speed is limited by the SCLK rate
of the µC or the DSP.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
initialization-software sequence (continued)
The TL V1570 interfaces to a DSP over five lines: CS, SCLK, SDOUT , SDIN, and FS, and interfaces to a µC over
four lines: CS, SCLK, SDOUT , and SDIN. The FS input should be pulled high in µC mode. The device is in 3-state
and power-down mode when CS is high. After CS falls, the TL V1570 checks the FS input at the CS falling edge
to determine the operation mode. If FS is low, DSP mode is set, otherwise µC mode is set.
CS
SCLK
FS
SDIN
SDOUT
XF
CLKX
CLKR
FSX
FSR
DX
DR
TLV1570 TMS320
CS
SCLK
FS
SDIN
SDOUT
I/O Terminal
SCLK
DX
DR
TLV1570 µC
DVDD
Figure 3. DSP to TLV1570 Interface Figure 4. µC to TLV1570 Interface
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines (see Figure 5). This requires that the supply and reference pins be sufficiently
bypassed. In most cases 0.1 µF ceramic chip capacitors are adequate to keep the impedance low over a wide
frequency range. Since their effectiveness depends largely on the proximity to the individual supply pin. They
should be placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog ground be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND, under the package.
AVDD
AGND
REF
TLV1570
100 nF
100 nF
DVDD
DGND
100 nF
Figure 5. Placement of Decoupling Capacitors
power supply ground layout
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simplified analog input analysis
Using the equivalent circuit in Figure 6, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows:
The capacitance charging voltage is given by:
Where:Rt = Rs + Ri
Ri = Ri(ADC) + Ri(MUX)
tch = Charge time
VC(t)
+
VS
ǒ
1–e–tch
ń
RtCi
Ǔ
The input impedance Ri is 718 Ω at 5 V, and is higher (~1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
VC (1/2 LSB) = VS – (VS/2048)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1/2 LSB) = Rt × Ci × ln(2048)
VS
*ǒ
VS
ń
2048
Ǔ+
VS
ǒ
1–e–tch
ń
RtCi
Ǔ
Where:
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
Therefore the maximum SCLK frequency is:
Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)
RsRi(MUX)
VSVC
15 pF
Driving Source†TLC1570
Ci
VI
VI= Input Voltage at AIN
VS= External Driving Source Voltage
Rs= Source Resistance
Ri(ADC)= Input Resistance of ADC
Ri(MUX)= Input Resistance (MUX on resistance)
Ci= Input Capacitance
VC= Capacitance Charging Voltage
†Driving source requirements:
•Noise and distortion for the source must be equivalent to the resolution of the converter.
•Rs must be real at the input frequency.
Ri(ADC)
MO AIN
Figure 6. Equivalent Input Circuit Including the Driving Source
(1)
(2)
(3)
(4)
(5)
(6)
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
definitions of specifications and terminology
integral nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, AGND to AVDD, DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range –0.3 V to AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to DVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV1570C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV1570I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
power supplies
MIN TYP MAX UNIT
Analog supply voltage, AVDD (see Note 1) 2.7 5.5 V
Digital supply voltage, DVDD (see Note 1) 2.7 5.5 V
NOTE 1: Abs (AVDD – DVDD) < 0.5 V
analog inputs
MIN TYP MAX UNIT
Analog input voltage, AIN AGND VREF V
Reference in
p
ut voltage REF
DVDD = 3.3 V to 2.7 V 55% AVDD AVDD
V
Reference
inp
u
t
v
oltage
,
REF
DVDD = 5.5 V to 4.5 V 60% AVDD AVDD
V
digital inputs
MIN TYP MAX UNIT
High-level input voltage, VIH DVDD = 2.7 V to 5.5 V 2.1 V
Low-level input voltage, VIL DVDD = 2.7 V to 5.5 V 0.8 V
In
p
ut SCLK frequency
DVDD = 5.5 V to 4.5 V 20
MHz
Inp
u
t
SCLK
freq
u
enc
yDVDD = 3.6 V to 2.7 V 1 10
MH
z
SCLK
p
ulse duration clock high t (SCLKH)
DVDD = 5.5 V to 4.5 V 23
ns
SCLK
p
u
lse
d
u
ration
,
clock
high
,
t
w(SCLKH) DVDD = 3.6 V to 2.7 V 46
ns
SCLK
p
ulse duration clock low t (SCLKL)
DVDD = 5.5 V to 4.5 V 23
ns
SCLK
p
u
lse
d
u
ration
,
clock
lo
w,
t
w(SCLKL) DVDD = 3.6 V to 2.7 V 46
ns
electrical characteristics,over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
digital specifications (SDOUT at 25 pF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Logic inputs
IIH High-level input current DVDD = 5 V, VI = 5 V 1µA
IIL Low-level input current DVDD = 5 V, VI = 0 V –1 µA
CIInput capacitance Control inputs 5 15 pF
Logic outputs
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOH High-level output voltage IOH = 50 µA – 0.5 mA DVDD–0.4 V
VOL Low-level output voltage IOL = 50 µA – 0.5 mA 0.4 V
IOZH High-impedance-state output current 1µA
IOZL Low-impedance-state output current –1 µA
COOutput capacitance 5 pF
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
dc specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 Bits
Accuracy
Integral nonlinearity , INL Best fit ±0.6 ±1 LSB
Differential nonlinearity, DNL ±0.65 ±1 LSB
EOOffset error ±0.1 ±0.15 %FSR
EGGain error ±0.1 ±0.2 %FSR
Analog input
CiInput capacitance 15 20 pF
Ilkg Input leakage current VAIN = 0 V to AVDD ±1µA
Ri(MUX)
In
p
ut MUX ON resistance
DVDD = 3 V, AVDD = 3 V 265 780 Ω
R
i(MUX)
Inp
u
t
MUX
ON
resistance
DVDD = 5 V, AVDD = 5 V 235 450 Ω
Ri(ADC)
In
p
ut MUX ON resistance
DVDD = 3 V, AVDD = 3 V 158 465 Ω
R
i(ADC)
Inp
u
t
MUX
ON
resistance
DVDD = 5 V, AVDD = 5 V 140 268 Ω
Voltage reference
REF
Internal reference voltage
Internal reference mode, VDD = 3 V 2.08 2.26 2.48 V
REF
Internal
reference
v
oltage
Internal reference mode, VDD = 5 V 3.48 3.82 4.15 V
Temperature coef ficient 100 ppm/°C
riInput resistance External reference mode 3 kΩ
Ci(VR) Input capacitance External reference mode 300 pF
Power supply
IDD +I
REF
O
p
erating su
pp
ly current
AVDD = 2.7 V, DVDD = 2.7 V, fSCLK = 10 MHz†3 5 mA
I
DD +
I
REF
Operating
s
u
ppl
y
c
u
rrent
AVDD = 5.5 V, DVDD = 5.5 V, fSCLK = 20 MHz‡7.2 8.5 mA
PD
Power dissi
p
ation
AVDD = 2.7 V, DVDD = 2.7 V 8 13 mW
PD
Power
dissi ation
AVDD = 5.5 V, DVDD = 5.5 V 40 47 mW
AVDD=27V
CS = AVDD 3 10
µA
Software
IDD +I
REF
AVDD
=
2
.
7
V
CS = AGND 500 µ
A
Supply current in
Soft
w
are
I
DD +
I
REF
AVDD=55V
CS = AVDD 3 10
µA
y
power down
AVDD
=
5
.
5
V
CS = AGND 2000 µ
A
Auto
IDD +I
REF
AVDD = 2.7V 175 275 µA
A
u
to
I
DD +
I
REF AVDD = 5.5V 200 300 µA
†IREF = 0.7 mA typ.
‡IREF = 1.5 mA typ.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
s
= 1.25 MSPS, External reference 58 61
f
i
= 100 kHz,
s,
AVDD = 5 V Internal reference 53 56
i,
70% of FS f
s
= 625 KSPS, External reference 56 61
SNR
Signal to noise ratio
s,
AVDD = 3 V Internal reference 53 55
dB
SNR
Signal
-
to
-
noise
ratio
f
s
= 1.25 MSPS, External reference 61
dB
f
i
= 50 kHz,
s,
AVDD = 5 V Internal reference 56
i,
90% of FS f
s
= 625 KSPS, External reference 61
s,
AVDD = 3 V Internal reference 55
f
s
= 1.25 MSPS, External reference 55 58
f
i
= 100 kHz,
s,
AVDD = 5 V Internal reference 53 55
i,
70% of FS f
s
= 625 KSPS, External reference 53 58
SINAD
Signal to noise ratio + distortion
s,
AVDD = 3 V Internal reference 52 54
dB
SINAD
Signal
-
to
-
noise
ratio
+
distortion
f
s
= 1.25 MSPS, External reference 59
dB
f
i
= 50 kHz,
s,
AVDD = 5 V Internal reference 55
i,
90% of FS f
s
= 625 KSPS, External reference 60
s,
AVDD = 3 V Internal reference 55
f
s
= 1.25 MSPS, External reference –60 –55
f
i
= 100 kHz,
s,
AVDD = 5 V Internal reference –70 –58
i,
70% of FS f
s
= 625 KSPS, External reference –60 –55
THD
Total harmonic distortion
s,
AVDD = 3 V Internal reference –66 –58
dB
THD
Total
harmonic
distortion
f
s
= 1.25 MSPS, External reference –64
dB
f
i
= 50 kHz
s,
AVDD = 5 V Internal reference –72
i
90% of FS f
s
= 625 KSPS, External reference –63
s,
AVDD = 3 V Internal reference –68
f
s
= 1.25 MSPS, External reference –63 –57
f
i
= 100 kHz,
s,
AVDD = 5 V Internal reference –73 –59
i,
70% of FS f
s
= 625 KSPS, External reference –61 –57
SFDR
S
p
urious free dynamic range
s,
AVDD = 3 V Internal reference –68 –60
dB
SFDR
Sp
u
rio
u
s
-
free
d
y
namic
range
f
s
= 1.25 MSPS, External reference –66
dB
f
i
= 50 kHz,
s,
AVDD = 5 V Internal reference –75
i,
90% of FS f
s
= 625 KSPS, External reference –65
s,
AVDD = 3 V Internal reference –70
f
s
= 1.25 MSPS, External reference 8.8 9.3
f
i
= 100 kHz,
s,
AVDD = 5 V Internal reference 8.6 8.9
i,
70% of FS f
s
= 625 KSPS, External reference 8.6 9.3
ENOB
Effective number of bits
s,
AVDD = 3 V Internal reference 8.4 8.8
dB
ENOB
Effecti
v
e
n
u
mber
of
bits
f
s
= 1.25 MSPS, External reference 9.5
dB
f
i
= 50 kHz,
s,
AVDD = 5 V Internal reference 8.9
i,
90% of FS f
s
= 625 KSPS, External reference 9.5
s,
AVDD = 3 V Internal reference 8.9
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ac specifications (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
Channel-to-channel crosstalk –75 dB
BW
Full
p
ower bandwidth
–1 dB full-scale input sine wave 12 15 MHz
BW
F
u
ll
-
po
w
er
band
w
idth
–3 dB full-scale input sine wave 25 MHz
BW
Small-signal bandwidth
–1 dB 15 20 MHz
BW
Small
-
signal
bandwidth
–3 dB 35 MHz
f
Sam
p
ling rate
AVDD = 5 V 0.0625 1.25
MSPS
f
s
Sampling
rate
AVDD = 3 V 0.0625 0.625
MSPS
timing requirements†
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(SCLK)
SCLK cycle time
DVDD = 5.5 V to 4.5 V 50 ns
t
c(SCLK)
SCLK
c
y
cle
time
DVDD = 3.6 V to 2.7 V 100
tw(1) Pulse duration, chip select 100 ns
t(s) Sampling period 6SLCK
cycles
t(conv) Conversion period 10 SLCK
cycles
tsu(1) Setup time, FS to SCLK falling edge in DSP mode 5 ns
th(1) Hold time, FS to SCLK falling edge in DSP mode 2 ns
tsu(2) Setup time, FS to CS falling edge in DSP mode 5.5 ns
th(2) Hold time, FS to CS falling edge in DSP mode 9 ns
td(1) Delay time, FS falling edge to next SCLK falling edge in DSP mode 6 ns
td(2) Delay time, SCLK rising edge after CS falling edge in µC mode 4 ns
td(3) Delay time, output after SCLK rising edge in µC mode and DSP
mode 10 20 ns
tsu(3) Setup time, serial input data to SCLK falling edge 10 ns
th(3) Hold time, serial input data to SCLK falling edge 4 ns
trRise time 3 200 ns
†Specifications subject to change without notice.
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
123
tc(SCLK)
tw(1)
tsu(1) th(1)
td(1)
tsu(2) th(2) tsu(3) th(3)
td3
MSB
DI15 DI14 DI13
00
SCLK
CS
FS
SDIN
SDOUT
Figure 7. DSP Mode Timing Diagrams
123 4
tw(1)
tsu(3) th(3)
td(3)
DI15 DI14 DI13 DI12
MSB
000
SCLK
CS
FS
SDIN
SDOUT
td(2)
Figure 8. µC Mode Timing Diagrams
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
200
150
50
0
–45 25
Analog Mux Input Resistance
250
300
ANALOG MUX INPUT RESISTANCE
vs
FREE-AIR TEMPERATURE
350
90
100
TA – Free-Air Temperature – °C
AVDD = 2.7 V, AIN = 2 V
AVDD = 5.5 V, AIN = 3.8 V
Figure 9 Figure 10
4
2
0
–45 25
Total Supply Current – mA
6
TOTAL SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
8
90
TA – Free-Air Temperature – °C
ICC
AVDD = 5.5 V
AVDD = 2.7 V
4
3
2
02.5 5 6.2 7.5 10 12.5 15.4
– Supply Current – mA
6
7
f – Clock Frequency – MHz
SUPPLY CURRENT
vs
CLOCK FREQUENCY (SCLK)
8
18 20
5
1
VDD = 2.7 V
VDD = 5.5 V
Figure 11
ICC
––2
–3
–4
–5 01
Gain – dB
–1
0
f – Input Frequency – MHz
GAIN
vs
INPUT FREQUENCY
1
10 100
Figure 12
VDD = 5 V, AIN = 90% of FS,
REF = 5 V, TA = 25°C
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.4
–1 0511
DNL – Differential Nonlinearity – LSB
0
0.4
Samples
1
1023
0.8
0.6
0.2
–0.2
–0.6
–0.8
VCC = 2.7 V, Internal REF = 2.3 V,
SCLK = 10 MHz,
TA = 25°C
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Figure 13
–0.6
–1 0
INL – Integral Nonlinearity – LSB
0
0.6
1
511
0.8
0.4
0.2
–0.2
–0.4
–0.8
1023
VCC = 2.7 V, Internal REF = 2.3 V,
SCLK = 10 MHz,
TA = 25°C
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Samples
Figure 14
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.4
–1 0511
DNL – Differential Nonlinearity – LSB
0
0.4
Samples
1
1023
0.8
0.6
0.2
–0.2
–0.6
–0.8
VCC = 2.7 V, External REF = 2.7 V,
SCLK = 10 MHz,
TA = 25°C
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Figure 15
–0.6
–1 0
0
0.4
1
1023
0.8
0.6
0.2
–0.2
–0.4
–0.8
511
VCC = 2.7 V, External REF = 2.7 V,
SCLK = 10 MHz,
TA = 25°C
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Samples
Figure 16
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.4
–1 0511
0
0.8
1
1023
0.6
0.4
0.2
–0.2
–0.6
–0.8
DNL – Differential Nonlinearity – LSB
Samples
VCC = 5.5 V, Internal REF = 3.8 V,
SCLK = 20 MHz,
TA = 25°C
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Figure 17
–0.6
0
0
0.4
1
1023
0.8
0.6
0.2
–0.2
–0.4
–0.8 511
INL – Integral Nonlinearity – LSB
VCC = 5.5 V, Internal REF = 3.8 V,
SCLK = 20 MHz,
TA = 25°C
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Samples
Figure 18
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.4
–1 0511
0
0.8
1
1023
0.6
0.4
0.2
–0.2
–0.6
–0.8
DNL – Differential Nonlinearity – LSB
Samples
VCC = 5.5 V, External REF = 5.5 V,
SCLK = 20 MHz,
TA = 25°C
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Figure 19
–0.6
–1 0
0
0.4
1
1023
0.8
0.6
0.2
–0.2
–0.4
–0.8
511
INL – Integral Nonlinearity – LSB
VCC = 5.5 V, External REF = 5.5 V,
SCLK = 20 MHz,
TA = 25°C
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Samples
Figure 20
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.4
–1 0511
0
0.8
1
1023
0.6
0.4
0.2
–0.2
–0.6
–0.8
DNL – Differential Nonlinearity – LSB
Samples
VCC = 5.5 V, External REF = 3.3 V,
SCLK = 20 MHz,
TA = 25°C
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Figure 21
–0.6
0
0
0.4
1
1023
0.8
0.6
0.2
–0.2
–0.4
–0.8 511
INL – Integral Nonlinearity – LSB
VCC = 5.5 V, External REF = 3.3 V,
SCLK = 20 MHz,
TA = 25°C
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
Samples
Figure 22
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
6
4
2
00 50 100 150
ENOB – Effective Number of Bits – BITS
8
10
f – Input Frequency – kHz
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
12
200 250 300
AVDD = DVDD = 3 V,
External REF = 3 V
Figure 24
6
4
2
00 100 200 300
ENOB – Effective Number of Bits – BITS
8
10
f – Input Frequency – kHz
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
12
400 500 600
AVDD = DVDD = 5 V,
External REF = 5 V
Figure 25
7
6
2
00 50 100 150
ENOB – Effective Number of Bits – BITS
8
9
f – Input Frequency – kHz
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
10
200 250 300
AVDD = DVDD = 3 V,
Internal REF = 2.3 V
5
4
3
1
Figure 26
7
6
2
00 100 200 300
ENOB – Effective Number of Bits – BITS
8
9
f – Input Frequency _ kHz
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
10
400 500 600
AVDD = DVDD = 5 V,
Internal REF = 3.8 V
5
4
3
1
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–80
–120 0
FFT – Fast Fourier Transform – dB
–40
–20
FAST FOURIER TRANSFORM
vs
FREQUENCY
300 600
0
–60
–100
100 200 400 500
Frequency – KHz
AIN = 200 kHz,
SCLK = 20 MHz,
AVDD = DVDD = 3 V,
Internal REF = 2.3 V
Figure 27
–80
–120 0
FFT – Fast Fourier Transform – dB
–40
–20
FAST FOURIER TRANSFORM
vs
FREQUENCY
300 600
0
–60
–100
100 200 400 500
AIN = 200 kHz,
SCLK = 20 MHz,
AVDD = DVDD = 5 V,
Internal REF = 3.8 V
Frequency – KHz
Figure 28
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–80
–120 0
FFT – Fast Fourier Transform – dB
–40
–20
FAST FOURIER TRANSFORM
vs
FREQUENCY
300 600
0
–60
–100
100 200 400 500
AIN = 200 kHz,
SCLK = 20 MHz,
AVDD = DVDD = External REF = 3 V
Frequency – KHz
Figure 29
–80
–120 0
FFT – Fast Fourier Transform – dB
–40
–20
Frequency – KHz
FAST FOURIER TRANSFORM
vs
FREQUENCY
300 600
0
–60
–100
100 200 400 500
AIN = 200 kHz,
SCLK = 20 MHz,
AVDD = DVDD = External REF = 5 V
Figure 30
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI14 DI13 DI12 DI11DI15
0 0 0 0 0 0 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 0 0 0 00
12345678
9 10111213141516 12345
SCLK
CS
FS
SDIN
SDOUT
Configure
Previous Conversion Output
Figure 31. Typical Timing Diagram for DSP Application
tstconv
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169B – DECEMBER 1997– REVISED OCT OBER 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
DI15
12345678910111213141516 12345
DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI1 DI15 DI14 DI13 DI12 DI11
00 0 0 0 0 DO9 DO8 DO7 DO6 DO5 D04 D03 D02 DO1 DO0 0 0 0 0 0
SCLK
CS
FS
SDIN
SDOUT
Configure
Previous Conversion Output
tstconv
Figure 32. Typical Timing Diagram for µC Application
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV1570CDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CPW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570CPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IPW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV1570IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV1570CPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TLV1570IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV1570CPWR TSSOP PW 20 2000 367.0 367.0 38.0
TLV1570IPWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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