(R) (R) ADC-208A 8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible) FEATURES * * * * * * * * * * 8-bit flash A/D converter 20MHz sampling rate 10MHz full-power bandwidth Sample-hold not required Low power CMOS +5Vdc operation 1.2 Micron CMOS 8-Bit latched outputs Surface-mount version No missing codes INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION The ADC-208A utilizes an advanced VLSI 1.2 micron CMOS in providing 20MHz sampling rates at 8-bits. The flexibility of the design architecture and process delivers latch-up free operation without external components and operation over the full military range. The ADC-208A is mechanically and electrically equivalent to the ADC-208 Series, with the exception of the OVERFLOW (pin 13) and ENABLE (pins 11 and 12) functions. These functions are not offered on the ADC-208A. PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 VDD CLOCK INPUT -REFERENCE ANA/DIG GND (VSS) ANALOG INPUT REF MIDPOINT ANALOG INPUT ANA/DIG GND (VSS) +REFERENCE VDD N.C. N.C. 5,7 +REFERENCE 9 FUNCTION 24 23 22 21 20 19 18 17 16 15 14 13 BIT 8 (LSB) BIT 7 BIT 6 BIT 5 REF 1/4 FS VDD REF 3/4 FS BIT 4 BIT 3 BIT 2 BIT 1 (MSB) N.C. 02 02 01 ANALOG INPUT PIN CLOCK GENERATOR 2 CLOCK Q 14 BIT 1 Q 15 BIT 2 Q 16 BIT 3 Q 17 BIT 4 Q 21 BIT 5 Q 22 BIT 6 Q 23 BIT 7 24 BIT 8 (LSB) 01 R2 D D G R G Q 1 3/4 REFERENCE D 18 G D G Q D R G 1 R2 MIDPOINT REFERENCE 6 D G Q R2 256 to 7 ENCODER 1/4 REFERENCE D G 1 20 R2 D G D G Q R - REFERENCE D G R2 3 D PINS 1, 10, 19 +5V +VDD D G Q G DIGITAL GND PINS 4-8 ANALOG GND Figure 1. ADC-208A Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com ADC-208A ABSOLUTE MAXIMUM RATINGS PARAMETERS Power Supply Voltage (VDD Pin 1, 10, 19) Digital Inputs Analog Input Reference Inputs Digital Outputs (short circuit protected to ground) Lead Temperature (10 sec. max.) Storage Temperature LIMITS UNITS -0.5 to +7 -0.5 to +5.5 -0.5 to (+VDD +0.5) -0.5 to (+VDD +0.5) -0.5 to +5.5 Volts Volts Volts Volts Volts +300 max. -65 to +150 C C PERFORMANCE Int. Linearity Over Temp. (ref. unadjusted) End-point Best-fit Line Zero-Scale Offset (Code "0" to "1" transition) Gain Error Differential Gain Differential Phase Aperture Delay Aperture Jitter Harmonic Distortion (8MHz second order harm.) Ref. bandwidth (See tech note 5) Power Supply Rejection No Missing Codes FUNCTIONAL SPECIFICATIONS (Typical at +5V power, +25C, 20MHz clock, +REFERENCE = +5V, -REFERENCE = ground, unless noted) ANALOG INPUT Single-Ended, Non-Isolated Input Range DC - 20MHz Analog Input Capacitance (static - Pin 5 to 7) (dynamic - Pin 5 to 7) Reference Ladder Resistance Reference Input (Note 5) MIN. TYP. MAX. UNITS 0 - +5.0 Volts - - - -0.5 20 64 500 - - - - VDD +0.5 pF pF Ohms Volts 3.2 -- -- -- -- 0.8 Volts Volts -- -- 15 +1 +1 25 +5 +5 -- A A nSec Power Supply Range (+VDD) Power Supply Current +25C +125C -55C Power Dissipation +25C +125C -55C 2.4 -- 4.5 -- 5.0 0.4 Volts Volts 4 4 -- -- -- -- mA mA 5 5 -- 8 10 Operating Temp. Range, Case: MC/LM Versions MM/LM/QL Versions Storage Temp. Range Package Type DIP LCC UNITS -- -- -- 2.3 1.8 1 2.6 2.0 2 LSB LSB LSB -- -- -- -- -- 1.5 2 1.1 8 50 3 -- -- -- -- LSB % degrees ns ps -40 -46 -- dB -- 10 -- MHz -- 0.02 0.05 %FSR/%Vs Over the operating temperature range +3.0 +5.0 +5.5 Volts -- -- -- +45 +40 +50 +65 +60 +70 mA mA mA -- -- -- 225 200 250 325 300 350 mW mW mW 0 -55 -65 -- -- -- +70 +125 +150 C C C 24-pin ceramic DIP 24-pin ceramic LCC Footnotes: Maximum input impedance is a function of clock frequency. At full-power input. For 10-step, 40 IRE NTSC ramp test. 15 nSec 10 25 -- 40 -- -- Straight binary nSec nSec Bits TECHNICAL NOTES 1. The Reference ladder is floating with respect to VDD and may be referenced anywhere within the specified limits. AC modulation of the reference voltage may also be utilized; contact DATEL for further information. PERFORMANCE Sampling Rate Full Power Bandwidth Diff. Linearity @ +25C (See tech note 7) Code Transitions Center of Codes Diff. Linearity Over Temp. Code Transitions Center of Codes Int. Linearity @ +25C (See tech note 4)(ref. adjusted) End-point Best-fit Line Int. Linearity Over Temp. (ref. adjusted) Best-fit Line Int. Linearity @ +25C (ref. unadjusted) End-point Best-fit Line MAX. PHYSICAL ENVIRONMENTAL DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading Logic Loading "1" Logic Loading "0" Output Data Valid Delay From Rising Clock Edge 99% probability 100% probability +25C -55C to +125C Data Output Resolution Data Coding TYP. POWER REQUIREMENTS DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading Logic Loading "1" Logic Loading "0" Clock Low Pulse Width MIN. 15 10 20 -- -- -- MSPS MHz -- -- 0.5 0.25 1.0 -- LSB LSB -- -- 0.5 0.25 1.0 -- LSB LSB -- -- -- -- 1/2 1/2 LSB LSB -- 1/2 1 LSB -- -- 2 1.6 2.6 1.9 LSB LSB 2. Clock Pulse Width - To improve performance when input signals may exceed Nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the input voltage slews and prevents the comparators from saturating. 3. A full-scale input produces all "1" on the data outputs. 4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and Differential Linearity (code transition). The specifications using the less conservative definition have also been provided as a comparative specification for products specified this way. DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com 2 ADC-208A 5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena that has plagued CMOS devices in the past. These converters do not require external protection diodes. Table 1. ADC-208A Output Code ANALOG INPUT 0.00V +0.02V +1.28V +2.54V +2.56V +2.58V +3.84V +5.10V 6. For clock rates less than 100kHz, there may be some degradation in offset and differential nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). 7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2. Then apply an appropriate clock input.The reference input should be held to 0.1% accuracy or better. Do not use the +5V power supply as a reference without precision regulation and high-frequency decoupling capacitors. CODE DATA 1234 DATA 5678 Zero 0000 +1 LSB +1/4 FS +1/2 FS-ILSB +1/2 FS +1/2 FS+ILSB +3/4 FS +FS 0000 0000 0100 0111 1000 1000 1100 1111 0000 0001 0000 1111 0000 0001 0000 1111 DECIMAL HEX 0 1 64 127 128 129 192 255 00 01 40 7F 80 81 C0 FF Note: Values shown here are for a +5.12Vdc reference. Scale other refereces proportionally. (+REF=+5.12V, -REF=GND, 1/4, 1/2, and 3/4 References FS=No Connection) 8. Zero Adjustment - Adjusting the voltage at -REFERENCE (pin 3) adjusts the offset or zero of the device. Pin 3 can be tied to GROUND for operation without adjustments 10.Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral Nonlinearity through access of the reference's 1/4, 1/2, and 3/4 full scale points. For example, the REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE and -REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1F capacitors for operation without INL adjustments 9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment. +5V 4.7F + +15 0.01F 4.7F 5 CLOCK 2 20MHz CLOCK 12 11 HA-5033 VDD 1,10,19 + D GND 4 0.1F A GND 8 +5V 10 VIN 5,7 10 +15V +15V 2 2 REF MID 6 + REF-3 REF+9 -15 0.1F 24 (LSB) B7 23 B6 22 B5 21 B4 17 B3 16 B2 15 B1 14 (MSB) 20 HP2811 4.7F B8 R1/4 18 R3/4 1-N 6 1 LM324 REF. D2 3 5 1+N 10k 1-N 9 4 8 + 4.7F 0.1F 10 2k LM324 + 0.1F 4.7F 1+N 1k 0.1F 1.5k 6 1-N 7 LM324 1k + 5 0.1F 0.1F 4.7F 1+N 1.5k 12 1-N 14 LM324 1k 13 0.1F + 1+N 0.1F 4.7F 2k Figure 2. ADC-208A Typical Connection Diagram DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com 3 ADC-208A MECHNICAL DIMENSIONS ADC-208A DIP ADC-208A LCC 0.250 0.005 (6.35) 1.250 (31.7) 0.050 (1.27) Pin 9 DATEL 0.500 (12.7) ADC-208A 0.400 SQ. +0.010, -0.005 (10.16) 0.610 (15.5) Pin 21 Pin 1 PIN 1 IDENTIFIER 0.020 0.005 (0.50) 0.090 Max. (2.28) 0.190 (4.9) 0.38 (9.7) 0.190 (4.9) 0.050 (1.3) 0.020 (0.5) AUTO ZERO 01 0.100 (2.5) SAMPLE N AUTO ZERO 02 01 SAMPLE N+1 02 AUTO ZERO SAMPLE N+2 01 02 N+1 DATA N DATA 40nSec max. ORDERING INFORMATION 40nSec max. Figure 3 Timing Diagram (R) MODEL TEMP. RANGE PACKAGE ADC-208AMC 0C to +70C 24-pin DIP ADC-208AMM -55C to +125C 24-pin DIP ADC-208ALC 0C to +70C 24-pin LCC ADC-208ALM -55C to +125C 24-pin LCC The ADC-208AMM-QL replaces the ADC-208MM-QL and includes DATEL QL High-Reliability Screening. The ADC-208ALM-QL replaces the ADC-208LM-QL. (R) DS-0500C 01/03 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark. 4