Copyright © Future Technology Devices International Limited 65
FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC Datasheet
Version 2.6
Document No.: FT_000061 Clearance No.: FTDI#77
Appendix B – List of Figures and Tables
List of Tables
Table 3.1 FT2232H Pin Configurations for 64-pin QFN and LQFP package ............................................. 9
Table 3.2 Power and Ground for 64-pin QFN and LQFP package ........................................................ 10
Table 3.3 Common Function pins for 64-pin QFN and LQFP package .................................................. 10
Table 3.4 EEPROM Interface Group for 64-pin QFN and LQFP package ............................................... 11
Table 3.5 Channel A and Channel B RS232 Configured Pin Descriptions ............................................. 11
Table 3.6 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions ................................ 12
Table 3.7 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions.......... 13
Table 3.8 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions
................................................................................................................................................ 14
Table 3.9 Channel A and Channel B MPSSE Configured Pin Descriptions ............................................. 15
Table 3.10 Channel B Fast Serial Interface Configured Pin Descriptions ............................................. 15
Table 3.11 Channel A and Channel B CPU-style FIFO Interface Configured Pin Descriptions .................. 15
Table 3.12 Channel A and Channel B Host Bus Emulation Interface Configured Pin Descriptions ........... 16
Table 3.13 FT2232H Pin Configurations for 56-pin VQFN package ..................................................... 18
Table 3.14 Power and Ground for 56-pin VQFN package .................................................................. 19
Table 3.15 Common Function pins for 56-pin VQFN package ............................................................ 19
Table 3.16 EEPROM Interface Group for 56-pin VQFN package ......................................................... 19
Table 3.17 Channel A and Channel B RS232 Configured Pin Descriptions for FT4232H-56Q .................. 20
Table 3.18 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions for FT4232H-56Q ..... 21
Table 3.19 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions for
FT4232H-56Q ............................................................................................................................. 22
Table 3.20 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions
for FT4232H-56Q ........................................................................................................................ 22
Table 3.21 Channel A and Channel B MPSSE Configured Pin Descriptions for FT4232H-56Q .................. 23
Table 3.22 Channel B Fast Serial Interface Configured Pin Descriptions for FT4232H-56Q .................... 24
Table 3.23 Channel A and Channel B CPU-style FIFO Interface Configured Pin Descriptions for FT4232H-
56Q .......................................................................................................................................... 24
Table 3.24 Channel A and Channel B Host Bus Emulation Interface Configured Pin Descriptions for
FT4232H-56Q ............................................................................................................................. 25
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings ............................................................ 32
Table 4.2 Asynchronous FIFO Timings (based on standard drive level outputs) ................................... 33
Table 4.3 MPSSE Signal Timings ................................................................................................... 34
Table 4.4 MCU Host Bus Emulation Mode Signal Timings – write cycle ............................................... 36
Table 4.5 MCU Host Bus Emulation Mode Signal Timings– read cycle ................................................. 37
Table 4.6 Fast Opto-Isolated Serial Interface Signal Timings ............................................................ 39
Table 4.7 CPU-Style FIFO Interface Operation Select ....................................................................... 40
Table 4.8 CPU-Style FIFO Interface Operation Read Status Description .............................................. 41
Table 4.9 CPU-Style FIFO Interface Operation Signal Timing. ........................................................... 41
Table 4.10 Synchronous Bit-Bang Mode Timing Interface Example Timings ........................................ 43
Table 4.11 Configuration Using EEPROM and Application Software .................................................... 46