Full-Feature −48 V Hot Swap Controller
Data Sheet
ADM1073
Rev. A
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FEATURES
Precision inrush linear current limit
Soft start inrush current limit profiling
Precision maximum on-time in current limit
Maximum on-time modulated by FET drain voltage for
additional SOA protection
Adjustable PWM retry scheme and multiple device cascading
capability for charging large capacitive loads
Limited number of PWM cycles for FET SOA protection under
short circuit condition
Ability to configure device as continuous autoretry with a
5-second cooling period
Shunt regulator topology to allow very large transient input
supplies
Separate UV and OV pins for programming allowable input
supply window
Programmable OV hysteresis using current source into pin
when supply is high
Programmable UV hysteresis using current sink from pin
when supply is low
PWRGD output indicates when capacitor charging complete
SPLYGD output indicates when supply is within
valid window
LATCHED output indicates the end of the retry cycle before
load capacitance is charged
SHDN input for user-commanded shutdown
RESTART input for user-triggered 5-second shutdown and
autorestart— virtual card reseat
FUNCTIONAL BLOCK DIAGRAM
04488-PrG-001
FAULT TIMER
AND CONTROL
OSCILLATOR PWM
TIMEOUT
FOLDBACK
AND PWRGD
5 SECOND
SHUTDOWN
t
ON
CONTROL
SOFT START
CONTROL
UNDERVOLTAGE
DETECTOR
OVERVOLTAGE
DETECTOR
V
CC
AND
REFERENCE
GENERATOR
LATCHEDRESTART
SPLYGDV
IN
OV
UV
SS
TIMER
SHDN
V
EE
SENSE
GATE
DRAIN
PWRGD
100mV(MAX) 50mA
V
IN
Figure 1.
APPLICATIONS
Central office switching
Telecommunication and data communication equipment
−48 V distributed power systems
Negative power supply control
High availability servers
−48 V power supply modules
Disk arrays
GENERAL DESCRIPTION
The ADM1073 is a full-feature, negative voltage, hot swap
controller that allows boards to be safely inserted and removed
from a live −48 V backplane. The part provides precise and
robust current limiting, and protection against both transient
and nontransient short circuits in overvoltage and undervoltage
conditions. The ADM1073 can operate from a negative voltage
of −18 V to −80 V and can tolerate transient voltages of up to
−200 V.
Inrush current is limited to a programmable value by control-
ling the gate drive of an external N-channel FET. The maximum
current limit is set by the choice of the sense resistor, RSENSE.
A built-in soft start function allows control of the inrush
current profile by an external capacitor on the soft start (SS)
pin.
An external capacitor on the TIMER pin determines the time
for which the FET gate is controlled to be high when maximum
inrush current flows. The ADM1073 employs a limited consec-
utive retry scheme, whereby, if the load capacitance is not fully
charged within one attempt, the FET gate is pulled low and
retries after a cooling period.
(continued on Page 3)
ADM1073 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Functional Description .................................................................. 13
Hot Circuit Insertion ................................................................. 13
Initial Startup .............................................................................. 13
Board Removal ........................................................................... 14
Controlling the Current ............................................................. 14
Sense ............................................................................................. 15
Sense Resistor .............................................................................. 15
Soft Start (SS Pin) ....................................................................... 15
GATE ............................................................................................ 15
VIN ................................................................................................. 15
VEE ................................................................................................. 15
Timing Control—TIMER ......................................................... 15
Drain ............................................................................................ 16
PWRGD ....................................................................................... 16
LATCHED ................................................................................... 16
SPLYGD ....................................................................................... 16
RESTART..................................................................................... 16
SHDN ........................................................................................... 16
Undervoltage/Overvoltage Detection ..................................... 16
Functionality and Timing.............................................................. 18
Live Insertion .............................................................................. 18
Overvoltage and Undervoltage Faults ..................................... 18
Soft Start ...................................................................................... 19
Current Faults ............................................................................. 20
Logic Inputs................................................................................. 21
Kelvin Sense Resistor Connection ........................................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
2/12—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
4/04—Revision 0: Initial Version
Data Sheet ADM1073
Rev. A | Page 3 of 24
GENERAL DESCRIPTION
(continued from Page 1)
Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).
The default duty cycle of the pulse train is 6%, decreasing to
2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
the power is reset. The LATCHED output signal indicates when
the seven retries are complete.
Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and
VEE allows the ratio of on-time to off-time to be decreased,
while a resistor between TIMER and VIN allows the ratio to be
increased.
The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold
(typically −36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically −80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Detection section). The SPLYGD output signal indicates when
the backplane supply is within the externally programmable
operating voltage range.
Other functions include
• PWRGD output, which can be used to enable a power
module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged)
• SHDN input to manually disable the GATE drive
• RESTART input to remotely initiate a 5 second shutdown
The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.
ADM1073 Data Sheet
Rev. A | Page 4 of 24
SPECIFICATIONS
VDD = 0 V, VEE = −48 V; TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
BOARD SUPPLY (Not Connected Directly to Device) Limited by external components
Maximum Voltage Range −200 −48 −18 V
Typical Operating Voltage Range −80 −48 −35 V
VIN PIN—SHUNT REGULATOR
Operating Supply Voltage Range 11.7 12.3 12.9 V IIN = 0.6 mA to 2 mA
Quiescent Supply Current 300 500 μA VIN = 11.7 V
Maximum Shunt Supply Voltage 14 V IIN = 10 mA
Undervoltage Lockout, VLKO 8 V
Power-On Reset Delay 150 ms
UV, OV PINS—UNDERVOLTAGE AND OVERVOLTAGE DETECTION
Undervoltage Falling Threshold, VUVF 825 868 910 mV
Undervoltage Hysteresis Current 5 μA
Undervoltage Fault Filter 0.6 ms
Overvoltage Rising Threshold, VOVR 1.86 1.93 2.00 V
Overvoltage Hysteresis Current 5 μA
Overvoltage Fault Filter 5 μs
Input Current 0.2 μA
GATE PIN—FET DRIVER
Maximum Gate Voltage 11.5 VIN(MAX) V IGATE = −1.0 μA
Minimum Gate Voltage 10 100 mV IGATE = 1.0 μA
Pull-Up Current −50 μA VGATE = 0 V to 8 V; VSS = 2 V
−36 μA VGATE = 0 V to 8 V; VSS = 0 V
Pull-Down Current 20 mA VGATE > 2 V
50 mA VGATE > 5 V
SENSE PIN—CURRENT SENSE—SOFT START
Current Limit Control Loop Threshold, VACL 97 100 103 mV IGATE = 0 mA
Circuit Breaker Limit Voltage, VCB 86 90 mV
Fast Current Limit Voltage, VFCL 110 mV
Control Loop Transconductance 4.5 μA/mV
Soft Start Pin Current 5 μA
TIMER PIN—PWM CONTROL
Minimum TIMER Pull-Up Current 18 19 20 μA I PWRGD < 4 μA; TA = 25°C to 85°C
16 19 20 μA I PWRGD < 4 μA
Maximum TIMER Pull-Up Current 37 39 41 μA I PWRGD = 24 μA; TA = 25°C to 85°C
34 39 41 μA I PWRGD = 24 μA
TIMER Pull-Down Current 1 μA
TIMER Low Voltage Trip Point 0.45 0.50 0.55 V
TIMER High Voltage Trip Point 2.34 2.42 2.50 V
Current Limit On-Time, tON 6 ms IDRAIN = 4 μA; CTIMER = 47 nF
Current Limit On-Time, tON, with Foldback 3 ms IDRAIN = 20 μA; CTIMER = 47 nF
Number of Consecutive PWM Retry Cycles 7
Continuous Short-Circuit Time before Latched Shutdown 0.6 s CTIMER = 47 nF
Data Sheet ADM1073
Rev. A | Page 5 of 24
Parameter Min Typ Max Unit Test Conditions
DRAIN (FOLDBACK) AND PWRGD
DRAIN Voltage at Which PWRGD Asserts 1.9 2 2.1 V RDRAIN = 3.75 M to 20 M
Maximum DRAIN Pin Current Allowable, IDRAIN(MAX) 36 µA VDS = 80 V; RDRAIN = 3.25 M
PWRGD Output Voltage Low 1 2 V I PWRGD = 2.5 mA
0.2 0.4 V I PWRGD = 0.5 mA
PWRGD Internal Pull-Up Current 6 µA
PWRGD Output Voltage High VIN V
RESTART
Time before Restart 5 s
Input Threshold 1.35 1.45 1.55 V
Glitch Filter 5 µs
Internal Pull-Up Current 6 µA
SHDN
Glitch Filter 5 µs
Input Threshold 1.35 1.45 1.55 V
Internal Pull-Up Current
6
µA
LATCHED AND
SPLYGD
Output Voltage Low 1 2 V ILATCHED, ISPLYGD = 2.5 mA
0.2 0.4 V ILATCHED, ISPLYGD = 0.5 mA
Internal Pull-Up Current 6 µA
Output Voltage High VIN V
ADM1073 Data Sheet
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
All voltages referred to VEE, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage (VDD − VEE) −0.3 V to −200.0 V
Maximum Shunt Supply Voltage, VSS 16 V
SENSE Pin −2 V to +2 V
GATE Pin −0.3 V to +16 V
UV Pin −0.3 V to +6 V
OV Pin −0.3 V to +6 V
SS Pin
−0.3 V to +6 V
TIMER Pin −0.3 V to +6 V
DRAIN Pin −0.3 V to +6 V
SHDN Pin −0.3 V to +16 V
SPLYGD Pin −0.3 V to +16 V
LATCHED Pin −0.3 V to +16 V
PWRGD Pin −0.3 V to +16 V
RESTART Pin −0.3 V to +16 V
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Continuous Power Dissipation 180 mW
Storage Temperature Range
−65°C to +150°C
Lead Temperature (Soldering, 10 s) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
14-lead TSSOP Package:
θJA = 240°C/W
θJC = 43°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Data Sheet ADM1073
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM1073
TOP VIEW
(Not to Scale)
RESTART
1
V
IN 2
PWRGD
3
SS
4
SENSE
5
SHDN
TIMER
UV
OV
DRAIN
14
13
12
11
10
V
EE 6
LATCHED
7
GATE
SPLYGD
9
8
04488-PrG-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin Number Mnemonic Function
1 RESTART Input Pin. Edge-triggered 5-second shutdown and automatic restart.
2
V
IN
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF
capacitor to VEE is recommended on the VIN pin.
3 PWRGD Open Drain Output. Signals that the hot swap is complete.
4 SS Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current
profile. This pin can be overdriven to alter the current limit control loop threshold.
5 SENSE Voltage Input from External Sense Resistor.
6 VEE Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
7 LATCHED Open Drain Output. Signals the end of the PWM retry period after a current fault.
8 SPLYGD Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage
window.
9 GATE Output to External FET Gate Drive.
10 DRAIN Analog Input for Monitoring of FET Drain Voltage.
11 OV Input Pin for Overvoltage Detection Circuitry.
12 UV Input Pin for Undervoltage Detection Circuitry.
13 TIMER Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the
PWM on-time, and the PWM duty cycle.
14 SHDN Input Pin. Level-triggered device shutdown and reset.
ADM1073 Data Sheet
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
04488-PrG-003
TEMPERATURE (°C) 85–50–35–20–51025405570
I
IN
(A)
0
500
450
400
350
300
250
200
150
100
50
Figure 3. IIN vs. Temperature
04488-PrG-004
V
IN
(V)
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.511.512.513.514.5
I
IN
(mA)
0.1
100.0
10.0
1.0
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
Figure 4. IIN vs. VIN
04488-PrG-005
TEMPERATURE (°C) 85–50–35–20–51025405570
R
Z
()
0
10
7
8
9
3
4
5
6
1
2
Figure 5. RZ (VIN Forward Voltage) vs. Temperature
04488-PrG-006
TEMPERATURE (°C) 85–50–35–20–51025405570
V
IN
(V)
11.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
Figure 6. VIN vs. Temperature
04488-PrG-007
TEMPERATURE (°C) 85–50 –35 –20 –5 –10 25 40 55 70
V
LKO
(V)
0
12
8
10
4
6
2
Figure 7. Undervoltage Lockout, VLKO, vs. Temperature
04488-PrG-008
TEMPERATURE (°C) 85–50 –35 –20 –50 10 25 40 55 70
DELAY (ms)
0
400
250
300
350
150
200
100
50
Figure 8. POR Delay vs. Temperature
Data Sheet ADM1073
Rev. A | Page 9 of 24
04488-PrG-009
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
V
GATEL
(mV)
0
10
100
70
80
90
30
40
50
60
20
Figure 9. VGAT EL vs. Temperature
04488-PrG-010
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
V
GATEH
(V)
10.0
10.5
14.0
12.5
13.0
13.5
11.0
11.5
12.0
Figure 10. VGATEH vs. Temperature
04488-PrG-011
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
I
GATE
(mA)
0
100
90
80
70
60
50
40
30
20
10
SS = 2V
SS = 0V
Figure 11. IGATE (Source) vs. Temperature
04488-PrG-012
VGATE (V) 12.08.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5
IGATE (mA)
0
50
30
35
40
45
15
20
25
5
10
SS = 0V
SS = 2V
Figure 12. IGATE (Source) vs. VGATE
04488-PrG-013
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
I
GATE
(mA)
0
60
40
30
50
20
10
Figure 13. IGATE (FCL, Sink) vs. Temperature (VGATE = 2 V)
04488-PrG-014
VGATE (V) 121234567891011
IGATE (mA)
0
100
90
80
60
70
30
40
50
20
10
Figure 14. IGATE (FCL, Sink) vs. VGATE
ADM1073 Data Sheet
Rev. A | Page 10 of 24
04488-PrG-015
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
V
UV
(V)
800
1000
980
960
920
900
880
940
860
840
820
Figure 15. UV Threshold vs. Temperature
04488-PrG-016
TEMPERATURE (°C) 85–50 –35 –20 –50 10 25 40 55 70
V
OV
(V)
1.80
1.82
2.00
1.92
1.94
1.96
1.98
1.84
1.86
1.88
1.90
Figure 16. OV Threshold vs. Temperature
04488-PrG-017
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
DELAY (ms)
0
2.0
1.2
1.4
1.6
1.8
0.8
1.0
0.6
0.2
0.4
Figure 17. UV Voltage Fault Filter Time vs. Temperature
04488-PrG-018
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
DELAY (ms)
0
10
7
6
5
4
9
8
3
2
1
Figure 18. OV Voltage Fault Filter Time vs. Temperature
04488-PrG-019
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
I
SENSE
(mA)
0
0.5
1.0
5.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
Figure 19. ISENSE vs. Temperature (VSENSE = 50 mV)
04488-PrG-020
VSENSE (V) 2.0–2 –1.5 –1.0 –0.5 0 0.5 1.0 1.5
ISENSE (mA)
–80
–60
–40
80
20
40
60
0
–20
Figure 20. ISENSE vs. (VSENSE − VEE)
Data Sheet ADM1073
Rev. A | Page 11 of 24
04488-PrG-021
TEMPERATURE (°C) 85–50–35–20–51025405570
V (mV)
80
85
90
120
105
110
115
95
100
V
FCL
V
ACL
V
CB
Figure 21. Voltage Limits for Load Current Control vs. Temperature
04488-PrG-022
TEMPERATURE (°C) 85–50–35–20–51025405570
TIMER THRESHOLD (V)
0
0.5
3.0
2.0
2.5
1.0
1.5
V
TMR
(LOW)
V
TMR
(HIGH)
Figure 22. High and Low TIMER Thresholds vs. Temperature
04488-PrG-023
TEMPERATURE (°C) 85–50–35–20–51025405570
TIMER
(ms)
0
2
4
20
12
14
16
18
6
8
10
Figure 23. Maximum Current Limit On-Time vs. Temperature
(IDRAIN = 4 μA, CTIMER = 47 nF)
04488-PrG-024
C
TIMER
(nF) 1000302010 40 50 60 70 80 90
1.0nF
4.7nF
10.0nF
22.0nF
33.0nF
47.0nF
68.0nF
82.0nF
100.0nF
TIMER (ms)
0
12
10
8
6
4
2
14
Figure 24. Current Limit On-Time vs. CTIMER (1 nF − 100 nF)
04488-PrG-025
TEMPERATURE (°C) 85–50–35–20–51025405570
PWM (%)
0
10
9
8
7
6
5
4
3
2
1
Figure 25. Current Limit PWM vs. Temperature
04488-PrG-026
RTIMER (M)100123456789
PWM (%)
0
5
10
50
30
35
40
45
15
20
25
Figure 26. Current Limit PWM vs. RTIMER
ADM1073 Data Sheet
Rev. A | Page 12 of 24
04488-PrG-027
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
t
SHORT
(s)
0
0.1
0.2
1.0
0.6
0.7
0.8
0.9
0.3
0.4
0.5
Figure 27. Continuous Short Circuit Time before Shutdown vs. Temperature
04488-PrG-028
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
t
RESTART
(s)
0
1
2
10
6
7
8
9
4
5
3
Figure 28. RESTART Time vs. Temperature
04488-PrG-029
CSS (nF) 100123456789
TRAMP (ms)
0
0.5
1.0
5.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
1.0nF 1.5nF
2.2nF
3.3nF
4.7nF
6.8nF
10.0nF
Figure 29. Soft Start Ramp Time vs. CSS
04488-PrG-030
TEMPERATURE (°C) 85–50 –35 –20 –5 10 25 40 55 70
I
UV/OV
(mA)
0
1
2
10
6
7
8
9
3
4
5
Figure 30. IUV/OV vs. Temperature
Data Sheet ADM1073
Rev. A | Page 13 of 24
FUNCTIONAL DESCRIPTION
HOT CIRCUIT INSERTION
Inserting circuit boards into a live −48 V backplane can cause
large transient currents to be drawn as the board capacitance
charges up. These transient currents can cause glitches on the
system power supply and can permanently damage the board
connectors and components.
The ADM1073 is designed to control the manner in which a
board’s supply voltage is applied so that harmful transient
currents do not occur and the board can be safely inserted or
removed from a live backplane. Undervoltage, overvoltage, and
overcurrent protection are other features of the part. The
ADM1073 ensures that the input voltage is stable and within
tolerance before being applied to the power module.
INITIAL STARTUP
The ADM1073 hot swap controller normally resides on a
removable circuit board and controls the manner in which
power is applied to the board upon connection. This is achieved
using a FET, Q1, in the power path (see Figure 31). By
controlling the gate voltage of the transistor, the surge of current
to charge load capacitance can be limited to a safe value when
the board makes connection. The ADM1073 can also reside on
the backplane itself and perform the same function from there.
Figure 32 shows a typical ADM1073 application circuit. When
the plug-in board is inserted into the live backplane, the −48 V
and 0 V lines connect to the live supply. This powers up the
device with the voltage on VIN exceeding VLKO. When the
voltage on the UV pin exceeds the undervoltage rising
threshold (0.868 V), it is now inside the programmed operating
voltage window. It must stay inside this window for the duration
of the power-on reset delay time, tPOR (150 ms).
SHDN RESTART
RDROP
RDRAIN
LATCHED
SPLYGD
PWRGD
ADM1073
CTIMER
CSS
CLOAD
R4
R3
R2
R1
DC-DC
CONVERTER
VIN+
VIN–
04488-PrG-031
RSENSE FET
LIVE
BACKPLANE
0V
–48V
PLUG-IN BOARD
Figure 31. ADM1073 Topology
FAULT TIMER
AND CONTROL
OSCILLATOR PWM
TIMEOUT
FOLDBACK
AND PWRGD
5 SECOND
SHUTDOWN
TIMER CONTROL
SOFT START
CONTROL
UNDERVOLTAGE
DETECTOR
OVERVOLTAGE
DETECTOR
V
CC
AND
REFERENCE
GENERATOR
LATCHEDRESTART
SPLYGDV
IN
OV
UV
SS
TIMER
SHDN
V
EE
SENSE
GATE
DRAIN
R
DRAIN
PWRGD
100mV(MAX) 50mA
V
IN
FET
R
SENSE
R
DROP
DC-DC
CONVERTER
5V
3.3V
2.8V
...etc.
GND
R1
R2
R
TIMER
*C
TIMER
R3
R4
C
SS
–48V RTN
+48V
04488-PrG-032
V
EE
*R
TIMER
IS AN OPTIONAL COMPONENT
Figure 32. ADM1073 Application Diagram
ADM1073 Data Sheet
Rev. A | Page 14 of 24
When the device detects that the supply voltage is valid, it
ramps up the GATE voltage until the FET turns on and the load
current increases. The ADM1073 monitors the level of the
current flowing through the FET by sensing the voltage across
the external sense resistor, RSENSE. When the SENSE voltage
reaches 100 mV, the GATE pin is actively controlled, limiting
the load current. In this way, the maximum current permitted
to flow through the load is set by the choice of RSENSE.
If a change in the level of the supply voltage causes the voltage
on UV to fall below the undervoltage falling threshold (VUVF),
or the voltage on OV to rise above the overvoltage rising
threshold (VOVR), then the gate drive is disabled.
BOARD REMOVAL
If the board is removed from a card cage, the voltage on the UV
pin falls to zero (that is, outside operating range) and the GATE
drive is de-asserted, turning off the FET.
CONTROLLING THE CURRENT
The ADM1073 features the following current control functions:
• Precision maximum current limit
• Controlled time in current limit
• Limited number of consecutive maximum current events
• Current limit profiling—soft start
• Overcurrent fast limit
In the following sections, five distinct system operating
conditions are described with reference to the current control
features.
Startup into Nominal Load Capacitance
Once the supply voltage has exceeded the UV threshold, and
following the 0.6 ms UV filter time, the current to the load
ramps up linearly as the capacitor on the Soft Start (SS) pin is
charged to 2.5 V. At the same time, current is sourced into the
capacitor on the TIMER pin, both from an on-chip source and
via the drain resistor. Once the soft start voltage has reached
2.5 V, the current to the load is limited to IMAX (100 mV/RSENSE).
Assuming that the values of RSENSE and the TIMER capacitance
have been chosen to allow the load capacitance to charge within
one ON period (tON period), the load capacitor is fully charged
before the voltage on TIMER reaches 2.5 V. At this point, the
current to the load decreases, and the FET gate voltage increases
to VSS, connecting the supply to the load.
Startup into Load with Large Capacitance
If the load capacitance is sufficiently large that to charge it fully
in one attempt would compromise the FET’s SOA, consecutive
maximum current events may be used. The use of this tech-
nique assumes that the load is not yet enabled, so negligible
load current is demanded. The initial current profiling is
identical to that for startup into a nominal load capacitance. If
the charge passed to the load in time tON with maximum current
flowing is insufficient to fully charge the load capacitance, at the
end of the tON period the load capacitance is still demanding
maximum current. The ADM1073 now controls the FET gate to
zero for a time tOFF, determined by the time taken for the on-
chip current sink to discharge the TIMER capacitance to 0.5 V.
At the end of time tOFF, the device retries, again following the
soft start current profile. In this way, a large load capacitance
can be charged using consecutive current limit periods. The
external components should be chosen to ensure that the
capacitance is fully charged within seven TIMER periods, if the
default limited consecutive retry mode is used.
Startup into a Short Circuit or over Current Fault
The load might demand large currents at initial connection.
The ADM1073 follows the Soft Start current profile as
described for startup into a nominal load. The current is limited
at IMAX for time tON following which the FET gate is pulled low.
The FET gate is held low for time tOFF, before retrying, again
with the soft start current profile. The ADM1073 cycles through
7 retries, after which it latches the FET off, assuming the default
limited consecutive retry mode is used.
Voltage Step during Normal Operation
Once the load capacitance is charged at initial board insertion
and a PWRGD signal is issued by the ADM1073, the load
begins to demand current. Therefore, following a step increase
in the magnitude of the supply voltage, not all the FET current
is available for charging of the load capacitance. Because the
FET is fully on following a step in the supply voltage, the
current increases immediately from ILOAD to supply charge to
the load capacitance. If the current remains below the fast
current limit, the FET gate drive amplifier controls it back to
IMAX. If the current exceeds the fast current limit, the FET gate is
strongly pulled down and back into regulation with the current
at IMAX. The size of the voltage step and the headroom between
the load current and IMAX determine the time required at IMAX to
charge the load capacitance. External components should be
chosen to ensure that any expected step size leads to a
requirement of less than time tON to charge the load capacitance.
Short Circuit or Overcurrent Fault during Operation
If a short circuit or an overcurrent fault occurs during normal
operation, the FET is fully on and initially allows increased
current to flow. If the current remains below the fast current
limit, the FET gate drive amplifier controls it back to IMAX. If the
current exceeds the fast current limit, the FET gate is strongly
pulled down and back into regulation with the current at IMAX.
Following a period, tON, the ADM1073 pulls the FET gate low
for a time tOFF, then retries following the soft start current
profile. If the fault persists, the ADM1073 cycles through 7
retries before latching off. If the fault clears within the 7-retry
period, the ADM1073 controls the FET gate high to allow
normal operation to continue.
Data Sheet ADM1073
Rev. A | Page 15 of 24
SENSE
The SENSE pin is used for sensing the voltage across an
external power sense resistor. This voltage is differentially
measured with respect to VEE, and used to control the GATE.
If SENSE is lower than 100 mV (after the soft start time), the
GATE pin is allowed to increase up to 12 V to provide
maximum FET enhancement. If the current increases such that
the SENSE pin tries to go above 100 mV, the GATE pin is
controlled in a feedback loop to ensure that the voltage across
the sense resistor is regulated at exactly 100 mV.
SENSE RESISTOR
The ADM1073’s current limiting function can operate at
different current levels. The current limit is determined by
selection of the sense resistor, RSENSE. Table 4 shows how the
maximum allowable load current (ILOAD(MAX)) and the minimum
and maximum inrush currents (ILIMIT(MIN) and ILIMIT(MAX)) are
related to the value of RSENSE.
Table 4. Minumum and Maximum Inrush Current and Load
Current Levels for Different Values of RSENSE
RSENSE (mΩ) ILOAD(MAX) (A) ILIMIT(MIN) (A) ILIMIT(MAX) (A)
5 17.20 19.40 20.60
10 8.60 9.70 10.30
15 5.73 6.47 6.87
18 4.78 5.39 5.72
22 3.91 4.41 4.68
33 2.61 2.94 3.12
47 1.83 2.06 2.19
51
1.69
1.90
2.02
68 1.26 1.43 1.51
75 1.15 1.29 1.37
90 0.96 1.08 1.14
SOFT START (SS PIN)
The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. Whenever the FET
is requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few mV. A current source is then turned
on, which linearly ramps the capacitor up to 2.5 V. The
reference voltage for the GATE linear control amplifier is
derived from the soft start voltage, such that the inrush linear
current limit is defined as
SENSE
STARTSOFTLIMIT
RVI ×= 20/
_
Overdriving the SS Pin
The SS pin can be overdriven externally from 0.360 V to 1.95 V
to offset the current limit control loop threshold from 18 mV to
100 mV. This allows different current limits to be selected at
different points of operation without using multiple sense
resistors. The current limit voltage is clamped at 100 mV
maximum.
GATE
Analog output for driving the external FET gate. This pin is
switched to VEE when the FET is off, is linearly controlled when
the FET is at the programmed inrush current limit, and is
switched to VIN when the FET is fully enhanced. The source
current capability is small to provide slow controlled turn-on,
and the sink current capability is large to provide fast turn-off.
VIN
Positive supply pin. This current-driven supply is shunt-
regulated at 12.3 V internally, and should be connected to the
most positive input supply terminal (usually −48 V RTN or 0 V)
through a dropper resistor. The resistor should be chosen such
that it always supplies enough current to overcome the
maximum quiescent supply current of the chip. Default RDROP =
30 kΩ.
VEE
Negative supply input. This pin should be connected directly to
the most negative input supply terminal (−48 V). This pin is
also used for differentially sensing across the external power
resistor, and should, therefore, be connected as close to the
sense resistor as possible. (See the Kelvin Sense Resistor
Connection section.)
TIMING CONTROL—TIMER
The TIMER pin is an analog pin that determines the maximum
on-time when the FET is in linear current limit, and controls
the PWM duty cycle for pulsed load capacitor charging. A
capacitor should be attached to this pin. When the FET is in
current limit, a 19 µA current source charges the external
capacitor. If the FET is still in current limit when the TIMER
capacitor reaches 2.5 V, the GATE driver is turned off and a
1 µA discharge current sink is turned on. The GATE remains
low until the TIMER capacitor is reduced to 0.5 V. At this point,
the GATE pin is turned on again. If the FET goes back into
current limit, the TIMER recharging starts again.
The PWM duty cycle is set at 6% default level by the size of
these two current sources. Adding a resistor from TIMER to VEE
decreases the duty cycle. Adding a resistor from TIMER to VIN
increases the duty cycle.
In addition, a current proportional to the current into the
DRAIN pin is added to the charging current. The additional
current varies linearly with DRAIN voltage. This reduces the
maximum on-time and the percentage PWM duty cycle when
there is a large voltage across the FET.
ADM1073 Data Sheet
Rev. A | Page 16 of 24
DRAIN
Analog input fed by a resistor connected to the drain of the
FET. This pin is clamped to go no higher than 4 V with respect
to VEE. Below this level, the voltage on the pin is monitored so
that, if it falls below 2 V, the PWRGD output can be set. Above
the 4 V level, the current into the pin is detected and used to
modulate the maximum on-time for the linear FET driver. This
is done by summing a proportion of the drain input current
with the charging current for the TIMER timing capacitor,
thereby reducing the allowable on-time.
PWRGD
Output to indicate when the load capacitor is fully charged.
This is an open collector output with internal pull-up to VIN.
When a normal startup is initiated, the PWRGD output is
latched low when the DRAIN pin falls below 2 V. The latch is
reset, if either the input supply goes out of range or a current
limit time-out event occurs. The second of these cases ensures
that, if a voltage step of greater than 2 V is presented at the
input, the PWRGD flag does not go high while the load
capacitor is being charged up to the additional voltage.
LATCHED
Output to indicate when the device has completed the maxi-
mum number (7) of PWM cycles. This is an open collector
output with an internal current source pull-up. If this PWM
time-out event occurs, the GATE pin is latched low and the
LATCHED output is set low. This condition can then be reset
by either a power cycling event or a low signal to either the
SHDN input or the RESTART input. By connecting the
LATCHED signal directly to SHDN, the device can effectively
be put into a continuous PWM mode. By connecting the
LATCHED signal directly to RESTART, the device can
effectively be put into autoretry mode, with a 5-second cooling
period.
SPLYGD
Output to indicate when the input supply is within the pro-
grammed voltage window. This is an open collector output with
an internal pull-up current source. For very large capacitive
loads where multiple FETs and controllers are required to meet
the inrush requirements, this output can be used to drive
directly into the UV pin of a second controller. This allows the
second FET to start 1 ms after the first one, with the added
advantage that the input supply UV detection is done on one
controller only. The SPLYGD output is asserted only when the
ADM1073 is not in reset mode.
RESTART
Edge-triggered input. Allows the user to remotely command a
5-second shutdown and restart of the hot swap function,
effectively simulating a board removal and replacement. The
shutdown function is triggered by a low pulse of at least 5 µs at
the pin. This pin has an internal pull-up of approximately 6 µA,
allowing it to be driven by an open collector pull-down output
or a push-pull output. The input threshold is 1.5 V.
SHDN
Level-triggered input. Allows the user to command a shutdown
of the hot swap function. When this input is set low, the GATE
output is switched to VEE to turn the FET off. This pin has an
internal pull-up of approximately 6 µA, allowing it to be driven
by an open collector pull-down output or a push-pull output.
The input threshold is 1.5 V.
UNDERVOLTAGE/OVERVOLTAGE DETECTION
The ADM1073 incorporates dual pin undervoltage and
overvoltage detection, with a programmable operating voltage
window. When the voltage on the UV pin falls below the UV
falling threshold or the voltage on the OV pin rises above the
OV rising threshold, a fault signal is generated that disables the
linear current regulator and results in the GATE pin being
pulled low. The voltage fault signal is time filtered so that faults
of a duration less than the UV glitch filter time (0.6 ms) and OV
glitch filter time (5 µs) do not force the gate drive low. The filter
operates only on the faulting edge, that is, on a high-to-low
transition on the undervoltage monitor and on a low-to-high
transition on the overvoltage monitor.
04488-PrG-033
1.93V
868mV
UNDERVOLTAGE
DETECTOR
OVERVOLTAGE
DETECTOR
ADM1073
FET DRIVE
ENABLE
SPLYGD
–48V RTN
–48V IN
R4
R3
R2
R1 OV
UV
V
IN
Figure 33. Undervoltage and Overvoltage Circuitry
(Standard 4-Resistor Configuration)
The operating voltage window is determined by selecting the
resistor ratios R1/R2 and R3/R4. These resistor networks form
two resistor dividers that generate the voltages at the UV and
OV pins, which are proportional to the supply voltage. By
choosing these ratios carefully, the user can program the
ADM1073 to apply the supply voltage to the load only when it is
within specific thresholds. Note that 1% tolerance resistors
should always be used to maintain the accuracy of the pro-
grammed thresholds.
Data Sheet ADM1073
Rev. A | Page 17 of 24
UV (Undervoltage)
The voltage on the UV pin is compared to an internal 0.868 V
reference. For the implementation in Figure 33, the undervolt-
age level is then set as
VUV = 0.868 × (R1 + R2)/R2
If the UV pin voltage is less than 0.868 V and the comparator
trips, an internal 5 µA current sink is turned on. This pulls the
UV voltage down by
VUVHYST(PIN) = 5 µA × R1 × R2/(R1 + R2)
at the UV pin, or by
VUVHYST(SUPPLY) = 5 µA × R1
at the supply.
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The UV comparator has an internal 0.6 ms time delay
to prevent nuisance shutdowns under noisy supply conditions.
OV (Overvoltage)
The voltage on the UV pin is compared to an internal 1.93 V
reference. For the implementation in Figure 33, the overvoltage
level is then set as
VOV = 1.93 × (R3 + R4)/R3
If the OV pin voltage exceeds 1.93 V and the comparator trips,
an internal 5 µA current source is turned on. This pulls the OV
voltage up by
VOVHYST(PIN) = 5 µA × R3 × R4/(R3 + R4)
at the OV pin, or by
VOVHYST(SUPPLY) = 5 µA × R3
at the supply.
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The OV comparator has an internal 5 µs time delay.
If the voltage on UV or OV goes out of range (below 0.868 V on
UV or above 1.93V on OV), GATE is pulled low. If the supply
subsequently reenters the operating voltage window, the
ADM1073 restores the GATE drive.
Hysteresis must be considered when reentering the operating
window, that is, VUV must increase above
0.868 V + VUVHYST(SUPPLY)
when recovering from an undervoltage fault, and VOV must
drop below
1.93 V − VOVHYST(SUPPLY)
when recovering from an overvoltage fault for GATE to be
restored.
Alternative UV and OV Configurations
A 2-resistor or a 3-resistor implementation can also be used to
set the UV and OV levels (see Figure 34 and Figure 35).
04488-PrG-052
ADM1073
–48V RTN
–48V IN
R2
R1 OV
UV
Figure 34. 2-Resistor UV/OV Implementation
04488-PrG-034
ADM1073
–48V RTN
–48V IN
R3
R1
R2
OV
UV
Figure 35. 3-Resistor UV/OV Implementation
ADM1073 Data Sheet
Rev. A | Page 18 of 24
FUNCTIONALITY AND TIMING
LIVE INSERTION
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1073 are shown in Figure 36. The
long connector pins are the first to make connection, and the
GND − VEE potential climbs to 48 V. As this voltage is applied,
the voltage at the VIN pin ramps to a constant 12.3 V and is held
at this level with the shunt resistor and external resistor
combination at the VIN pin. In this case, the connection pins are
staggered so that the R1/R2 and R3/R4 resistor dividers are the
last to connect to the backplane. This means that VUV and VOV
begin to ramp after the other pins connect. Note that staggered
connector pins are optional, because an internal time filter is
included on the UV pin.
When VUV crosses the undervoltage rising threshold, it is now
inside the operating voltage window and the −48 V supply must
be applied to the load. The SPLYGD output is asserted and after
a time delay, tPOR, the ADM1073 begins to ramp up the gate
drive. When the voltage on the SENSE pin reaches 100 mV (the
analog current limit level), the gate drive is held constant. When
the board capacitance is fully charged, the sense voltage begins
to drop below the analog current limit voltage and the gate
voltage is free to ramp up further. The gate voltage eventually
climbs to its maximum value of 12.3 V and the PWRGD output
is asserted. Figure 37 shows some typical startup waveforms.
tPOR
V
LKO
V
UVR
–48V RTN – VEE
V
IN
V
UV
GATE
SENSE
V
OUT
SPLYGD
PWRGD
04488-PrG-035
Figure 36. Timing Waveforms Associated with a Live Insertion Event
04488-PrG-036
Figure 37. Typical Startup Sequence
(Ch1 = GATE; Ch2 = SENSE; Ch3 = PWRGD; Ch4 = SPLYGD)
OVERVOLTAGE AND UNDERVOLTAGE FAULTS
The waveforms for an overvoltage glitch are shown in Figure 38.
When VOV glitches above the overvoltage threshold of 1.93 V, an
overvoltage condition is detected and the GATE voltage is
pulled low. VOV begins to drop back toward the operating
voltage window, and the GATE drive is restored when the
overvoltage falling threshold (1.93 V minus preset OV
hysteresis level) is reached. Figure 38 illustrates the ADM1073’s
reactions to an overvoltage condition.
04488-PrG-037
Figure 38. Timing Waveforms Associated with an Overvoltage Fault
(Ch1 = GATE; Ch2 = OV; Ch3 = PWRGD; Ch 4 = SPLYGD)
Data Sheet ADM1073
Rev. A | Page 19 of 24
An undervoltage glitch is dealt with in a similar way. When VUV
falls below the undervoltage threshold of 0.868 V, the GATE
voltage is pulled low. VUV begins to rise back toward the
operating voltage window, and the GATE drive is restored when
the undervoltage rising threshold (0.868 V plus preset UV
hysteresis level) is reached. Figure 39 illustrates the ADM1073’s
operation in an undervoltage situation.
04488-PrG-038
Figure 39. Timing Waveforms Associated with an Undervoltage Fault
(Ch1 = GATE; Ch2 = UV; Ch3 = PWRGD; Ch4 = SPLYGD)
SOFT START
The ADM1073 offers a variable soft start feature. The value of
the capacitor on the SS pin sets the ramp rate of the inrush
current profile at startup. Figure 40 to Figure 42 show different
inrush current ramp rates for three SS capacitors.
04488-PrG-039
Figure 40. Soft Start Profile with a 0.1 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
04488-PrG-040
Figure 41. Soft Start Profile with a 1.5 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
04488-PrG-041
Figure 42. Soft Start Profile with an 8.2 nF Capacitor
(Ch1 = GATE; Ch2 = SENSE)
ADM1073 Data Sheet
Rev. A | Page 20 of 24
CURRENT FAULTS
Some timing waveforms associated with overcurrent faults are
shown in the following figures. Figure 43 shows how a perma-
nent current fault is dealt with after startup. SPLYGD going low
indicates when the supply voltage is good. Because the output is
shorted, the sense voltage immediately rises through the 90 mV
circuit breaker threshold, and the fault timer is started. The
linear current control loop then goes into regulation at VSENSE =
100 mV, accurately limiting the load current at the preset level.
The limited consecutive retry scheme PWMs the GATE pin
seven times. When the seventh retry occurs, the permanent
fault is deemed permanent and the part latches off. The
LATCHED output asserts at this time. Power must now be
cycled to restart the device. This can be achieved via a manual
card reseating event (which cycles the power) or with an
external RESTART or SHDN signal.
04488-PrG-042
Figure 43. Timing Waveforms Associated with a Current Fault at Startup,
Using Limited Consecutive Retry (Ch1 = GATE; Ch2 = SENSE;
Ch3 = SPLYGD; Ch4 = LATCHED)
Note that the LATCHED output can also be tied back to the
RESTART input, giving an infinite retry during current fault
with a 5-second cool-down period after every seven retries. The
waveforms for this event are similar to those in Figure 43, but
repeats every five seconds.
Figure 44 shows the behavior of ADM1073 when a temporary
current fault occurs followed by a permanent current fault.
When the first overcurrent fault occurs, the first 97.5 mV spike
on the SENSE line can be seen. The ADM1073 retries a number
of times, and during the fifth tOFF time this current fault corrects
itself. After this time period, a no-fault condition is detected
and the limited consecutive counter is reset. GATE is reasserted.
When the overcurrent fault returns permanently, the limited
consecutive retry counter detects seven consecutive faults and
the part latches off. In this way, the ADM1073 prevents
nuisance shutdowns caused by transient shorts of a
programmable duration (typically ~0.6 s, set via TIMER, as
follows), but provides latched shutdown protection from
permanently shorted loads.
04488-PrG-044
Figure 44. Timing Waveforms Associated with a Temporary Current Fault
Followed by a Permanent Current Fault
(Ch1 = GATE; Ch2 = SENSE)
Figure 45 shows the behavior of the TIMER pin during a retry
cycle. Different current sources are switched in during the
on-time (TIMER ramping up) and off-times (TIMER ramping
down). This can be seen in the varying ramp-up and ramp-
down rates of TIMER below. The default ratio of tON to tOFF is
6%. This ratio can be reduced with a resistor from TIMER to
VEE or increased with a resistor from TIMER to VIN. The total
retry period can be extended or reduced by changing the value
of the TIMER capacitor.
04488-PrG-045
Figure 45. Timing Waveforms during a Retry Cycle for CTIMER = 0.82 nF
(Ch1 = GATE; Ch2 = SENSE; Ch3 = TIMER)
Data Sheet ADM1073
Rev. A | Page 21 of 24
LOGIC INPUTS
Figure 46 shows assertion of the level-triggered SHDN signal
for 150 ms, causing the ADM1073 to shut down for this
duration.
04488-PrG-046
Figure 46. Timing Waveforms Associated with a RESET Event
(Ch1 = GATE; Ch2 = SHDN; Ch3 = PWRGD; Ch4 = SPLYGD)
Figure 47 shows the assertion of the edge-triggered RESTART
signal, causing the ADM1073 to shut down for approximately
five seconds before restarting automatically.
04488-PrG-047
Figure 47. Timing Waveforms Associated with a RESTART Event
(Ch1 = GATE; Ch2 = RESTART; Ch3 = PWRGD; Ch4 = SPLYGD)
KELVIN SENSE RESISTOR CONNECTION
When using a low-value sense resistor for high current
measurement, the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 48 shows the correct way to connect the sense resistor
between the SENSE and VEE pins of the ADM1073.
KELVIN SENSE TRACES
SENSE V
EE
ADM1073
CURRENT
FLOW FROM
LOAD
CURRENT
FLOW TO –48V
BACKPLANE
SENSE RESISTOR
04488-PrG-048
Figure 48. Kelvin Sensing with the ADM1073
ADM1073 Data Sheet
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
COM P LIANT TO JEDE C S TANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PI N 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1073ARUZ −40°C to +85°C 14-Lead TSSOP RU-14
ADM1073ARUZ-REEL −40°C to +85°C 14-Lead TSSOP RU-14
ADM1073ARUZ-REEL7 −40°C to +85°C 14-Lead TSSOP RU-14
EVAL-ADM1073MEBZ Micro Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADM1073
Rev. A | Page 23 of 24
NOTES
ADM1073 Data Sheet
Rev. A | Page 24 of 24
NOTES
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04488–0–2/12(A)
