CY2DL1504
Document Number: 001-56312 Rev. *I Page 15 of 16
*C 3090644 CXQ 11/19/2010 Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Added “VOUT = 0.75V - 1.75V” to IOZ comments.
Moved VPP from AC spec table to DC spec table, removed VPP.
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets.
Added “Measured at 1 GHz” to tR, tF spec condition.
Removed specs tS, tH, tOD, and tOE from AC spec table.
Removed VPP reference from Figure 4.
*D 3135189 CXQ 01/12/2011 Removed “Preliminary” status heading.
Removed “Functional equivalent” bullet on page 1.
Added “(see IOZ)” note to pin 8 description in Pin Definitions.
Fixed typo and removed resistors from INX/INX# in Logic Block Diagram.
Added Figure 10 to describe TSOE and TSOD.
*E 3090938 CXQ 02/25/11 Post to external web.
*F 3208968 CXQ 03/29/2011 Changed RP max from 140 k to 165 k and updated RP in Logic Block
Diagram.
*G 3308039 CXQ 07/11/2011 Updated supported differential input clock types to include CML in Features,
Functional Description, Pin Definitions, and DC specs table sections.
*H 3395868 PURU 10/05/11 Updated supported differential input clock types to include HCSL in Features,
Pinouts, and DC Electrical Specifications table.
Changed Min value of VICM.
*I 3892255 PURU 02/01/2013 Updated Features (Added “Translates any single-ended input signal to 3.3 V
LVPECL levels with resistor bias on INx# input”).
Updated AC Electrical Specifications:
Added Note 8 and Note 13.
Added FIN parameter values for “Single Ended Input” condition
(Minimum value = DC, Maximum value = 250 MHz).
Added FOUT parameter values for “Single Ended Input” condition
(Minimum value = DC, Maximum value = 250 MHz).
Added tODC parameter values for “Single Ended Input” condition
(Minimum value = 45%, Maximum value = 55%).
Updated Description of PNADD parameter (Replaced “Additive RMS phase
noise, 156.25-MHz input, Rise/fall time < 150 ps (20% to 80%), VID > 400 mV”
with “Additive RMS phase noise, 156.25-MHz input, Rise/fall time < 150 ps
(20% to 80%), VID > 400 mV or Input Swing = 3.0 V[8]”).
Added tJIT parameter values for the Condition “156.25 MHz Sinewave,
12 kHz to 20 MHz offset, input rise/fall time < 150 ps (20% to 80%),
Input Swing = 3.0 V [13]” (Maximum value = 0.11 ps).
Added Application Information.
Updated in new template.
Document History Page (continued)
Document Title: CY2DL1504, 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input
Document Number: 001-56312
Revision ECN Orig. of
Change
Submission
Date Description of Change