CS5466-ISZR - Cirrus Logic Inc - Datasheet.Directory

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CS5466

Low-cost Power/Energy IC with Pulse Output

Features

Single-chip Power Measurement Solution

Energy Data Linearity:

±0.1% of Reading, over 1000:1 Dynamic Range

On-chip functions: Measures Power and

Performs Energy-to-pulse Conversions

Meets Accuracy Spec for IEC, ANSI, & JIS.

High-pass Filter Option

Four Input Ranges for Current Channel

On-chip, 2.5 V Reference

Pulse Outputs for Stepper Motor or

Mechanical Counter

On-chip Energy Direction Indicator

Ground-referenced Input Signals with Single

Supply

High-frequency Output for Calibration

On-chip, Power-on Reset (POR)

Power Supply Configurations:

VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to 5 V

Description

The CS5466 is a low-cost power meter solution incorpo-

rating dual delta-sigma (analog-to-digital converters

ADCs), an energy-to-frequency converter, and energy

pulse outputs on a single chip. The CS5466 is designed

to accurately measure and calculate energy for single

phase, 2- or 3-wire power metering applications with

minimal external components.

The low-frequency pulse outputs, E1 and E2, provide

pulses at a frequency which is proprtional to the active

power and can be used to drive a stepper motor or a me-

chanical counter. Energy direction output, NEG,

indicates when pulse outputs E1 and E2 represen t neg-

ative active power. The high-frequency pulse output

FOUT is designed to assist in system calibration.

The CS5466 has configuration pins which allow for direct

configuration of pulse output frequency, current channel

input range, and high-pass filter enable option.

The CS5466 also has a power-on reset function which

holds the part in reset until the supply reaches an oper-

able level.

ORDERING INFORMATION

See page 16.

IIN+

IIN-

IGAIN0

IGAIN1

VIN+

VIN-

VREFOUT

VA+ RESET VD+

DGNDAGND

FOUT

CPUCLK

XOUT

XIN

FREQ0

FREQ1

FREQ2

PGA

x10

NEG

4th Order 

Modulator

2nd Order 

Modulator

HPF

Option

Config

Clock

Generator

Digital

Filter

Digital

Filter

2.5V On-Chip

Reference

VREFIN x1

HPF

Option

HPF

Energy-to-

Frequency

Conversion

APR ‘11

DS659F2

CS5466

2DS659F2

TABLE OF CONTENTS

1. OVERVIEW ...............................................................................................................................3

2. PIN DESCRIPTION ...................................................................................................................4

3. CHARACTERISTICS & SPECIFICATIONS .............................................................................5

RECOMMENDED OPERATING CONDITIONS.......................................................................5

ANALOG CHARACTERISTICS................................................................................................5

VOLTAGE REFERENCE .........................................................................................................6

DIGITAL CHARACTERISTICS.................................................................................................7

SWITCHING CHARACTERISTICS ..........................................................................................8

ABSOLUTE MAXIMUM RATINGS ...........................................................................................9

4. THEORY OF OPERATION .....................................................................................................10

4.1 Digital Filters .... ... ... ... ................. ... ... ... ................ .... ... ... ................ ... .... ... ... ......................10

4.2 Active Power Computation ......... ... ... ... ... .... ... ... ................ .... ... ... ... ... .... ... ... ... .... ...............10

5. FUNCTIONAL DESCRIPTION ...............................................................................................11

5.1 Analog Inputs ................ ... ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... ...................11

5.1.1 Voltage Channel .. ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................ ...11

5.1.2 Current Channel ............ ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ...............11

5.2 High-pass Filter ................................................................................................................11

5.3 Energy Pulse Outputs ......... ... .... ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ...............11

5.3.1 Pulse Output Format. ................ .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... ...11

5.3.2 Selecting Frequency of E1 and E2 ... ... ... ................. ... ... ... ... .... ... ... ... .... ... ... ... ... ...11

5.3.3 Selecting Frequency of FOUT .............................................................................12

5.3.4 Absolute Max Frequency on E1 and E2 ..............................................................12

5.3.5 E1 and E2 Frequency Calculation .......................................................................13

5.4 Energy Direction Indicator ..... .... ... ... ................ ... .... ... ................ ... ... .... ................ ... ... ... ...13

5.5 Power-on Reset ..... ... .... ... ... ................ ... .... ... ... ... ................. ... ... ... ... ................. ... ... ... ......13

5.6 Oscillator Characteristics .................... ... .... ................ ... ... .... ... ... ... ... .... ... ................ ... ... ...13

5.7 Basic Application Circuit ..................................................................................................14

6. PACKAGE DIMENSIONS .......................................................................................................15

7. REVISION HISTORY ..............................................................................................................16

LIST OF FIGURES

Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale)......................................................8

Figure 2. Data Flow.......................................................................................................................10

Figure 3. Oscillator Connection.....................................................................................................13

Figure 4. Typical Connection Diagram..........................................................................................14

LIST OF TABLES

Table 1. Current Channel PGA Setting.........................................................................................11

Table 2. Maximum Frequency for E1, E2, and FOUT...................................................................12

Table 3. Absolute Max Frequency on E1 and E2..........................................................................12

CS5466

DS659F2 3

1. OVERVIEW

The CS5466 is a CMOS monolithic power measurement device with an energy computation engine. The CS5466

combines a p rogrammable gain am plifier, two  ADCs, and energy-to-frequency conversion circuitry on a single

chip.

The CS5466 is designed for energy measurement applications and is optimized to interface to a shunt or current

transformer for current mea surement, and to a resistive divider or transfor mer for voltage measurement. The current

channel has a programmable gain amplifier (PGA) which provides four full-scale input options. With a single +5 V

supply on VA+/AGND, both of the CS5466’s input channels accommodate common-mode plus signal levels be-

tween (AGND - 0.25 V) and VA+.

The CS5466 has three pulse output pins: E1, E2, and FOUT. E1 an d E2 can b e used to di rectly drive a m echanical

counter or stepper motor, or interface to a microcontrolle r. The FOUT pin conve ys active (real) power at a pulse fre-

quency many times higher than that of the E1 or E2 pulse frequency, allowing for high-speed calibration.

CS5466

4DS659F2

2. PIN DESCRIPTION

Clock Generator

Crystal Out

Crystal In 1, 24 XOUT, XIN - A single stage amplifier inside the chip is connected to these pins and can be used

with a crystal to provide the system clock for the device. Alternatively, an external clock can be

supplied to the XIN pin to provide the system clock for the device.

CPU Clock Output 2CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.

Control Pins

Gain Select 5, 7 IGAIN1, IGAIN0 - Used to select the current channel input gain range.

Frequency Select 17, 20, 23 FREQ2,FREQ1,FREQ0 - Used to select max pulse output frequency for E1, E2, and FOUT.

High Pass Filter Enable 8HPF - High disables the HPF. Low activates HPF on Voltage channel. Connecting HPF pin to

FOUT pin activates HPF on Current channel.

Reset 19 RESET - Low activates Reset.

Energy Pulse Ou tp uts

Energy Output 22, 21 E1, E2 - Active low alternating pulses with an output frequency that is proportional to the active

(real) power.

High Freq Outpu t 18 FOUT - Outputs energy pulses at a frequency higher than E1 and E2 outputs. Used for calibra-

tion purposes.

Neg Energy Indicato r 6NEG - High indicates negative energy.

Analog Inputs/Outputs

Differential Voltage Inputs 9, 10 VIN+, VIN- - Differential analog input pins for voltage channel.

Voltage Reference

Output 11 VREFOUT - The on-chip voltage reference output pin. The voltage reference has a nominal

magnitude of 2.5 V and is referenced to the AGND pin on the converter.

Voltage Reference Input 12 VREFIN - Voltage input to this pin establishes the voltage reference for the on-chip modulators.

Differential Current Inputs 16, 15 IIN+, IIN- - Differential analog input pins for current channel.

Power Supply Connections

Positive Digital Supply 3VD+ - The positive digital supply.

Digital Ground 4DGND - Digital Ground.

Analog Ground 13 AGND - Analog Ground.

Positive Analog Supply 14 VA+ - The positive analog supply.

VREFIN 12Vol t age R eference Input VREFOUT 11Vol t age Reference O ut put VIN- 10Different i al V ol t a ge I nput VIN+ 9Different i al V ol t a ge I nput HPF 8High-pa ss Fi l t er Enabl e IGAIN1 7Gain Select 1 NEG 6Negative Energy I ndi c at or IGAIN0 5Gain Select 0 DGND 4Di gital Gr ound VD+ 3Positive Power Supply CPUCLK 2CPU Cl ock O ut put XOUT 1Crystal Out

AGND13 Analog Groun d

VA+14 Positi ve Anal og Suppl y

IIN-15 Differential Cur rent Inpu t

IIN+16 Differential Cur rent Inpu t

FREQ217 Frequency S elect 2

FOUT18 High-fr equenc y Out put

RESET19 Reset

FREQ120 Frequency S elect 1

E221 Energy O ut put 2

E122 Energy O ut put 1

FREQ023 Frequency S elect 0

XIN24 Crystal In

CS5466

DS659F2 5

3. CHARACTERISTICS & SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ANALOG CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all operating ponditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

•MCLK = 4.096 MHz

Notes: 1. Applies when the HPF option is enabled

2. Applies before system calibration. Specified as a percentage of full scale (FS).

Parameter Symbol Min Typ Max Unit

Positive Digital Power Supply VD+ 3.135 5.0 5.25 V

Positive Analog Power Supply VA+ 4.75 5.0 5.25 V

Voltage Reference VREFIN - 2.5 - V

Specifie d Temperature Rang e TA-40 - +85 °C

Parameter Symbol Min Typ Max Unit

Analog Inputs (Current Channel)

Differential Input Range (Gain = 10)

[(IIN+)-(IIN-)] (Gain = 50)

(Gain = 100)

(Gain = 150)

IIN -

±250

±50

±25

±16.7

Input Capacitance (All Gain Ranges) CinI-25-pF

Effective In put Impedance (All Gain Ranges) ZinI30 - - k

Analog Inputs (Voltage Channel)

Differential Input Range [(VIN+)-(VIN-)] VIN --±250mV

Input Capacitance CinV-0.2-pF

Effective Input Impedance ZinV2--M

Accuracy (Energy Outputs)

Active Energy Linearity All Gain ranges

(Note 1) Input Range 0.1% - 100% - - ±0.1 - %

Full-scale Error (Note 2) - - 4.0 - %FS

Offset Error (Note 2) - - 0.06 - %FS

CS5466

6DS659F2

ANALOG CHARACTERISTICS (Continued)

Notes: 3. All outputs unloaded. All inputs CMOS level.

4. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sine wave (frequency =

60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input

channels are shorted to VA-. Then the CS5466 is put into an internal test mode and digital output data is collected

for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value

is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel’s inputs,

in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):

VOLTAGE REFERENCE

Notes: 5. The voltage at VREFOUT is measured across the temperature range. From these measurements the following

formula is used to calculate the VREFOUT Temperature Coefficient:.

6. Specified at maximum recommended output current of 1 A, source or sink.

Parameter Symbol Min Typ Max Unit

Power Supplies

Power Supply Currents IA+

ID+ (VA+ = VD+ = 5 V)

ID+ (VA+ = 5 V, VD+ = 3.3 V)

1.3

2.9

1.7

Power Consumption (VA+ = VD+ = 5 V)

(Note 3) (VA+ = 5 V, VD+ = 3.3 V) -

-21

11.6 25

-mW

Power Supply Rejection Ratio (50, 60 Hz)

(Note 4) Voltage Channel (Gain = 10)

Current Channel (All Gains) PSRR 45

-dB

PSRR 20 0.150V

Veq

------------------







log=

Parameter Symbol Min Typ Max Unit

Reference Output

Output Voltage REFOUT + 2.4 +2.5 +2.6 V

VREFOUT Temperature Coefficient (Note 5) TCVREF - 25 60 ppm/°C

Load Regulation (Note 6) VR-610mV

Reference Input

Input Voltage Range VREFIN - +2.5 - V

Input Capacitance - - 4 - pF

Input CVF Current - - 70 - nA

(VREFOUTMAX - VREFOUTMIN)

VREFOUTAVG

(

TAMAX - TAMIN

(

1.0 x 10

(

TCVREF =

CS5466

DS659F2 7

DIGITAL CHARACTERISTICS (Note 7)

• Min / Max characteristics and specifications are guaranteed over all operating conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz

Notes: 7. All measurements performed under static conditions.

8. If external MCLK is used, then the duty cycle must be betwe en 45% and 55% to maintain this specific ation.

9. The frequency of CPUCLK is equal to MCLK.

10. VOL and VOH are not specified under this condition.

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency Internal Gate Oscillator MCLK 3 4.096 5 MHz

Master Clock Duty Cycle - 40 - 60 %

CPUCLK Duty Cycle (Note 8 and 9) - 40 - 60 %

Filter Characteristics

High-pass Filter Corner Frequency -3 dB - - 0.125 - Hz

Input/Output Characteristics

High-level Input Voltage XIN

RESET

VIH (VD+) - 0.5

0.8VD+ -

-V

Low-level Input Voltage (VD = 5 V) XIN

RESET

VIL -

-1.5

0.2VD+ V

Low-level Input Voltage (VD = 3.3 V) XIN

RESET

VIL -

-0.3

0.2VD+ V

High-level Output Voltage (except XOUT) Iout = +5 mA VOH (VD+) - 1.0 - - V

Low-level Output Voltage (except XOUT) Iout = -5 mA VOL --0.4V

Input Leakage Current Iin -±1±10µA

Digital Output Pin Capacitance Cout -5-pF

Drive Current FOUT, E1, E2, NEG (Note 10) IDR -50-mA

CS5466

8DS659F2

SWITCHING CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all operating conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.

Notes: 11. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

12. Oscillator start-up time varies with crystal parameters. This specification does not app ly when using an external

clock source.

13. Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. See

”Energy Pulse Outputs” on page 11. for more information on pulse output pins.

14. Timing is proportional to the frequency of MCLK.

15. When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 s at MCLK = 4.096 M Hz.

Parameter Symbol Min Typ Max Unit

Rise Times Digital Output (Note 11) trise -50-ns

Fall Times Digital Output (Note 11) tfall -50-ns

Start-up

Oscillator Start-up Time XTAL = 4.096 MHz (Note 12) tost -60-ms

E1 and E2 Timing (Note 13 and 14)

Period t1500 - - ms

Pulse Width t2250 - - ms

Rising Edge to Falling Edge t3250 - - ms

E1 Falling Edge to E2 Falling Edge t4250 - - ms

FOUT Timing (Note 13 and 14)

Period t50.10 1 / fFOUT ms

Pulse Width (Note 15) t6-0.5*t

590 ms

FOUT Low t7-0.5*t

5-ms

FOUT

t2t3

Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale)

CS5466

DS659F2 9

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in perm anent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 16. VA+ and AGND must satisfy {(VA+) - (AGND)}  + 6.0 V.

17. VD+ and AGND must satisfy {(VD+) - (AGND)}  + 6.0 V.

18. Applies to all pins including continuous over-voltage conditions at the analog input pins.

19. Transient current of up to 100 mA will not cause SCR latch-up.

20. Maximum DC input current for a power supply pin is ±50 mA.

21. Total power dissipation, including all input currents and output currents.

Parameter Symbol Min Typ Max Unit

DC Power Supplies (Notes 16 and 17)

Positive Digital

Positive Analog VD+

VA+ -0.3

-0.3 -

-+6.0

+6.0 V

Input Current, Any Pin Except Supplies (Notes 18, 19, 20) IIN --±10mA

Output Current, Any Pin Except VREFOUT IOUT --100mA

Power Dissipation (Note 21) PD--500mW

Analog Input Voltage All Analog Pins VINA - 0.3 - (VA+) + 0.3 V

Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V

Ambient Operating Temperature TA-40 - 85 °C

Storage Temperature Tstg -65 - 150 °C

CS5466

10 DS659F2

4. THEORY OF OPERATION

The CS5466 is a dual-channel analog-to-digital convert-

er (ADC) followed by a computation engine that per-

forms an energy-to-pulse conversion . The flow diagram

for the two data paths is depicted in Figure 2. The ana-

log inputs are structured with two dedicated channels,

voltage and current, then optimized to simplify interfac-

ing to sensing elements.

The voltage-sensing element introduces a voltage

waveform on the voltage channel inpu t VIN and is sub-

ject to a fixed 10x gain amplifier. A second-order delta-

sigma modulator samples the amplified signal for digiti-

zation.

Simultaneously, the curr ent sensing element introduces

a voltage waveform on the current channel input IIN

and is subject to four programmable gains. The ampli-

fied signal is sampled by a fourth-order delta-sigma

modulator for digitization. Both converters sample at a

rate of MCLK / 8. The over-sampling provides a wide

dynamic range and simplified anti-alias filter design.

4.1 Digital Filters

The decimating dig ital filters on both chann els are Sinc3

filters followed by fourth-order IIR filters. The single-bit

data is passed to the low-pass decimation filte r and out-

put at a fixed word rate. The output word is passed to

the IIR filter to compensate for the magnitude roll-off of

the low-pass filtering operation.

An optional digital high-pass filter (HPF in Figure 2) re-

moves any DC component from the selected signal

path. By removing the DC component from the voltage

or current channel, any DC content will also be removed

from the calculated averag e active (real) power as well.

4.2 Active Power Computation

The instantaneous voltage and current data samples

are multiplied to obtain the instantaneous power. The

product is then avera ged over 400 con version s to com-

pute the active power value used to drive pul se outputs

E1, E2, and FOUT. Output pulse rate of E1 and E2 can

be set to one of four frequencies to directly drive a step-

per motor or a e lectromechanical counter or interface to

a microcontroller or infrared LED. The alternating output

pulses of E1 and E2 allows for use with low-cost elec-

tromechanical counters.

Output FOUT provides a uniform pulse stream that is

proportional to the active power and is designed for sys-

tem calibration. The FREQ[2:0] inputs set the output

pulse rate of E1, E2, and FOUT. See ”Energy Pulse

Outputs” on page 11. for more details.

2nd Order



Modulator

4th Order



Modulator

VIN±

IIN±

Energy-to-

Pulse Rate

Converter

FOUT

Sinc3

PGA

10x

HPF

NEG

IGAIN[1:0]

FREQ[2:0]

IIR

Sinc3

Current Channel

Voltage C h anne l

Digital F ilter

HPF

N=400



HPF

Config

Digital Filter

Figure 2. Data Flow

CS5466

DS659F2 11

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5466 is equipped with two fully differential input

channels. The in puts VIN and IIN are designated as

the voltage and current channel inputs, respectively.

The full-scale differential input voltage for the current

and voltage channel is 250 mVP.

5.1.1 Voltage Channel

The output of the line-voltage resistive divider or trans-

former is connected to the VIN+ and VIN- input pins of

the CS5466. The voltage channel is equipped with a

10x, fixed-gain amplifier. The full-scale signal level that

can be applied to the voltage channel is 250 mV. If the

input signal is a sine wave, the maximum RMS voltage

is:

which is approximately 70.7% of maximum peak volt-

age.

5.1.2 Current Channel

The output of the current-sense resistor or transformer

is connected to the IIN+ and IIN- input pins of the

CS5466. To accommodate different current-sensing de-

vices, the current channel incorporates programmable

gains which can be set to one of four input ra nges. Input

pins IGAIN1 and IGAIN0 (See Table 1) define the four

gain selections an d corresponding maximum input sig-

nal level.

For example, if IGAIN1=IGAIN0=0, the current chan-

nel’s gain is set to 10x. If the input signals are pu re sinu-

soids with zero phase shift, the maximum peak

differential signal on the current or voltage channel is

250 mVP. The input signal levels are approximately

70.7% of maximum peak voltage producing a full-scale

energy pulse registration eq ual to 50% of absolute max-

imum energy pulse registration. This will be discussed

further in Section 5.3 Energy Pulse Outputs on page 11.

5.2 High-pass Filter

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. Input pin HPF defines the th re e op tio ns :

– High-pass Filter (HPF) is disabled when pin HPF is

connected high.

– HPF is enabled in the voltage channel when pin HPF is

connected low.

– HPF is enabled in the current channel when pin HPF is

connected to pin FOUT.

5.3 Energy Pul s e Outputs

The CS5466 provides three output pins for energy reg-

istration. The E1 and E2 pins provide a simple interface

from which energy can be registered. These pins are

designed to directly connect to a stepper motor or elec-

tromechanical counter. The pulse rate on the E1 and E2

pins are in the range of 0 to 4 Hz and all frequency set-

tings are optimize d to be used with standard mete r con-

stants. The FOUT pin is designated for system

calibration and the pulse rate can be selected to reach

a frequency of 8000 Hz.

5.3.1 Pulse Output Format.

The CS5466 produ ces alternating pulses on E1 and E2.

This pulse format is designed to drive a stepper motor.

Each pin produces active-low pulses with a minimum

pulse width of 250 ms when MCLK = 4.096 MHz. Refer

to “Switching Characteristics” on page 8 for timing pa-

rameters.

The FOUT pin issues active-high pulses. The pulse

width is equal to 90 ms (typical), unless the period falls

below 180 ms. At this time the pulses will be equal to

half the period. In mode 3 (FREQ[2:0] = 3), the pulse

width of all FOUT pulses is typically 20 s regardless of

the pulse rate (MCLK = 4.096 MHz).

5.3.2 Selecting Frequency of E1 and E2

The pulse rate on E1 and E2 can be set to one of four

frequency ranges. Input pins FREQ1 and FREQ0 (See

Table 2) determine the maximum frequency on E1 and

E2 for pure sinusoidal inputs with zero phase shift. As

shown in Figure 1 on page 8, the frequency of E2 is

equal to the frequency of E1 with active-low alternating

pulses.

As discussed in Section 5.1.2 Current Channel on page

11, the maximum frequency on the E1 and E2 output

pins is equal to the selected frequency in Table 2 if the

maximum peak differential signal applied to both chan-

nels is a sine wave with zero phase shift.

IGAIN1 IGAIN0 Maximum Input

Range

0 0 ±250mV 10x

01±50mV50x

1 0 ±25mV 100x

1 1 ±16.67mV 150x

Table 1. Current Channel PGA Setting

250mVP

----------------- 176.78mVRMS



CS5466

12 DS659F2

5.3.3 Selecting Frequency of FOUT

The pulse output FOUT is designed to assist with meter

calibration. Using the FREQ[2:0] pin s, FOUT can be set

to frequencies higher than that of E1 and E2. The FOUT

frequency is directly proportional to the E1 and E2 fre-

quencies. Table 2 defines the maximum frequencies for

FOUT and the dependency of FOUT on E1 and E2.

5.3.4 Absolute Max Frequency on E1

and E2

The CS5466 supports input signals on the voltage and

current channels that may not be a sine wave. A typical

situation of achieving the absolute maximu m frequency

on E1 and E2 would be if a 250 mV dc signal is applied

to the VIN and IIN input pins. The digital high-pass filter

should be disengaged by selecting HPF = 1.

The absolute maximum pulse rate observed on E1 and

E2, determined by the FREQ[2:0] selection is defined

below in Table 3.

Frequency Select Maximum Frequency for a Sine Wave (Notes 1, 2 and 3)

FREQ2 FREQ1 FREQ0 E1 or E2 E1+E2 FOUT

0 0 0 0. 12 5 Hz 0 .2 5 Hz 64x(E1+E2)16 Hz

0 0 1 0.25 Hz 0.5 Hz 32x(E1+E2)16 Hz

0 1 0 0.5Hz 1.0 Hz 16x(E1+E2)16 Hz

0 1 1 1.0 Hz 2.0 Hz 2048x(E1+E2) 4,096 Hz

1 0 0 0.125 Hz 0.25 Hz 128x (E1 +E2)32 Hz

1 0 1 0.25 Hz 0.5 Hz 64x(E1+E2)32 Hz

1 1 0 0.5 Hz 1.0 Hz 32x(E1+E2)32 Hz

1 1 1 1.0 Hz 2.0 Hz 16x(E1+E2)32 Hz

Notes: 1 A pure sinusoidal input with zero phase shift is applied to the voltage and current channel.

2 MCLK = 4.096 MHz

3 See Figure 1 on page 8 for E1 and E2 timing diagram.

Table 2. Maximum Frequency for E1, E2, and FOUT

Frequency Select Absolute Max Fre quency

FREQ2 FREQ1 FREQ0 E1 or E2 E1+E2

x 0 0 0.25 Hz 0.5 Hz

x 0 1 0.5 Hz 1.0 Hz

x 1 0 1.0 Hz 2.0 Hz

x 1 1 2.0 Hz 4.0 Hz

Table 3. Absolute Max Frequency on E1 and E2

CS5466

DS659F2 13

5.3.5 E1 and E2 Frequency Calculation

The pulse output fr equency of E1 and E2 is directly pro-

portional to the active power calculated from the input

signals. To calculate the output frequency on E1 and

E2, use the following transfer function:

Example:

For a given application, assume a 50 Hz line frequency

and a purely resistive load (unity power factor), the fol-

lowing configuration is used:

– FREQ[2:0] = 3 FREQmax = 2 Hz

– IGAIN[1:0] = 2 IGAIN = 100

– VREFIN = VREFOUT = 2.5 V

In this configuration, the maximum sine wave that can

be applied is 250 mVp on the voltage channel and

25 mVp on the current channel. Using the above equa-

tion, the output frequency of energy pulse E1 or E2 is

calculated:

With maximum pure sinusoidal input signals, the fre-

quency of E1 or E2 is half the absolute maximum fre-

quency set with FREQ[2:0].

To calculate the frequency of FOUT for the example

above, assume FREQ2 = 0.

5.4 Energy Direction Indicator

The NEG pin indicates the sign of the calculated active

power. If negative active power is detected, the NEG

output pin will become active-high and will remain ac-

tive-high until positive active power is detected. The

NEG pin is valid at least 250ns prior to any assertion of

E1 or E2, and FOUT, to indicate the sign of a given en-

ergy output. The NEG pin is updated at a rate of 10 Hz

at MCLK = 4.096 MHz.

5.5 Power-on Reset

Upon powering up, the digital circuitry is held in reset

until the analog voltage reaches 4.0 V. At that time, an

eight-XIN-clock-period delay is enabled to allow the os-

cillator to stabilize. The CS5466 w ill then initialize. The

device reads the control pins IGAIN[1:0], FREQ[2:0]

and HPF, and begins performing energy measure-

ments.

5.6 Oscillator Characteristics

XIN and XOUT are the input and output of an inverting

amplifier which can be configured as an on-chip oscilla-

tor, as shown in Figure 3. The oscillator circuit is de-

signed to work with a quartz crystal. To reduce circuit

cost, two load capacitors C1 and C2 are integrated in

the device, one between XIN and DGND and the other

between XOUT and DGND. Lead lengths to/from the

crystal should be minimized to reduce stray capaci-

tance. To drive the device from an external clock

source, XOUT should be left unconnected while XIN is

driven by the external circuitr y. There is an amplifier be-

tween XIN and the digital section which provides

CMOS-level signals. This amplifier works with sinusoi-

dal inputs so there are no problems with slow edge

times.

FREQE1,E2 = Actual frequency of E1 and E2 pulses [Hz]

VIN = rms voltage across VIN+ and VIN- [V]

IIN = rms vo ltage across IIN+ and IIN- [V]

IGAIN = Current channel gain selection (10, 50, 100, 150)

PF = Power Factor

FREQmax = Absolute Max Frequency for E1 and E2 [Hz]

VREFIN = Voltage at VREFIN pin [V]

FREQE1,E2 VIN 10IINIGAINPFFREQmax



VREFIN2

------------------------------------------------------------------------------------------------------------------

0.25Vp100.025Vp

10012Hz

222.5V2



--------------------------------------------------------------------------------------------------------- 1Hz=

FOUT 2048 E1 E2+2048 2Hz4096Hz===

Oscillator

Circuit

DGND

XIN

XOUT

C1 = 22 pF

C2 =

Figure 3. Oscillator Connection

CS5466

14 DS659F2

5.7 Basic Application Circuit

Figure 4 shows the CS5466 configured to measure

power in a singl e-pha se, 2- wire sys tem wh ile oper ating

in a single-supply co nfiguration. In this diagram, a shunt

resistor is used to sense the line current and a voltage

divider is use d to sense the line voltage. In t his type of

shunt resistor configuration, the common-mode level of

the CS5466 must be referenced to the line side of the

power line. This means that the common-mode poten-

tial of the CS5466 will track the high voltage levels, as

well as low voltage levels , with respect to earth ground

potential.

ED IR / P4

VD+

FOUT

XOUT

XIN

CPUCLK

DGNDVA-

VREFOUT

VREFIN

IIN+

IIN-

VIN-

VIN+

AGND

13 4

120 VAC

10500500 

470 nF 470F0.1

F0.1F

RSHUNT

0.1 F

AGND

VA+

RI+

RI-

RV-

CIdiff

CVdiff

CV-

CV+

CI+

CI-

FREQ2 17

FREQ1 20

FREQ0 23

IGAIN1 7

IGAIN0 5

NEG 6

IHPF 8

Stepper

Motor

5466

Config.

Settings

4.096 MHz

10 k1F

RESET

Calibratio

Resistor

Note:

Indicates commo n (floating) return.



Figure 4. Typical Connection Diagram

CS5466

DS659F2 15

6. PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting li ne, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13

A1 0.002 0.006 0.010 0.05 0.13 0.25

A2 0.064 0.068 0.074 1.62 1.73 1.88

b 0.009 -- 0.015 0.22 -- 0.38 2,3

D 0.311 0.323 0.335 7.90 8.20 8.50 1

E 0.291 0.307 0.323 7.40 7.80 8.20

E1 0.197 0.209 0.220 5.00 5.30 5.60 1

e 0.022 0.026 0.030 0.55 0.65 0.75

L 0.025 0.03 0.041 0.63 0.75 1.03

0° 4° 8° 0° 4° 8°

JEDEC #: MO-150

Controlling Dimension is Millimeters.

24L SSOP PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW



CS5466

16 DS659F2

7. ORDERING INFORMATION

8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

9. REVISION HISTORY

Model Temperature Package

CS5466-ISZ (lead free) -40 to +85 °C 24-pin SSOP

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS5466-ISZ (lead free) 260 °C 3 7 Days

Revision Date Changes

PP1 SEP 2004 Initial Release

PP2 OCT 2004 Corrected table heading on Page 6.

PP3 J UN 20 05 M ino r ed its

F1 AUG 2005 Updated with most-current characterization data. corrected energy pulse output

rate equation on p13. Added MSL data.

F2 APR 2011 Removed lead-containing (Pb) device ordering information.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

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