MC33167TVG - ON SEMICONDUCTOR - Datasheet.Directory

November, 2005 − Rev. 7 1Publication Order Number:

MC34167/D

MC34167, MC33167

5.0 A, Step−Up/Down/

Inverting Switching

Regulators

The MC34167, MC33167 series are high performance fixed

frequency power switching regulators that contain the primary

functions required for dc−to−dc converters. This series was

specifically designed to be incorporated in step−down and

voltage−inverting configurations with a minimum number of external

components and can also be used cost effectively in step−up

applications.

These devices consist of an internal temperature compensated

reference, fixed frequency oscillator with on−chip timing components,

latching pulse width modulator for single pulse metering, high gain

error amplifier, and a high current output switch.

Protective features consist of cycle−by−cycle current limiting,

undervoltage lockout, and thermal shutdown. Also included is a low

power standby mode that reduces power supply current to 36 mA.

Features

•Output Switch Current in Excess of 5.0 A

•Fixed Frequency Oscillator (72 kHz) with On−Chip Timing

•Provides 5.05 V Output without External Resistor Divider

•Precision 2% Reference

•0% to 95% Output Duty Cycle

•Cycle−by−Cycle Current Limiting

•Undervoltage Lockout with Hysteresis

•Internal Thermal Shutdown

•Operation from 7.5 V to 40 V

•Standby Mode Reduces Power Supply Current to 36 mA

•Economical 5−Lead TO−220 Package with Two Optional Leadforms

•Also Available in Surface Mount D2PAK Package

•Moisture Sensitivity Level (MSL) Equals 1

•Pb−Free Packages are Available

Figure 1. Simplified Block Diagram

(Step Down Application)

ILIMIT

Vin

UVLO

5.05 V/

5.0 A

Reference

Thermal

PWM

Oscillator

This device contains 143 active transistors.

TO−220

TH SUFFIX

CASE 314A

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

TO−220

TV SUFFIX

CASE 314B

Heatsink surface connected to Pin 3

TO−220

T SUFFIX

CASE 314D

Pin 1. Voltage Feedback Input

2. Switch Output

3. Ground

4. Input Voltage/VCC

5. Compensation/Standby

D2PAK

D2T SUFFIX

CASE 936A

Heatsink surface (shown as

terminal 6 in case outline

drawing) is connected to Pin 3

x = 3 or 4

A = Assembly Location

WL = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

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3x167T

AWLYWWG

3x167T

AWLYWWG

3x167T

AWLYWWG

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MAXIMUM RATINGS (Note 1 and 2)

Rating Symbol Value Unit

Power Supply Input Voltage VCC 40 V

Switch Output Voltage Range VO(switch) −2.0 to + Vin V

Voltage Feedback and Compensation Input Voltage Range VFB, VComp −1.0 to + 7.0 V

Power Dissipation

Case 314A, 314B and 314D (TA = +25°C) PDInternally Limited W

Thermal Resistance, Junction−to−Ambient qJA 65 °C/W

Thermal Resistance, Junction−to−Case qJC 5.0 °C/W

Case 936A (D2PAK) (TA = +25°C) PDInternally Limited W

Thermal Resistance, Junction−to−Ambient qJA 70 °C/W

Thermal Resistance, Junction−to−Case qJC 5.0 °C/W

Operating Junction Temperature TJ+150 °C

Operating Ambient Temperature (Note 3)

MC34167

MC33167

TA0 to + 70

− 40 to + 85

°C

Storage Temperature Range Tstg − 65 to +150 °C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

1. Maximum package power dissipation limits must be observed to prevent thermal shutdown activation.

2. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per MIL−STD−883, Method 3015.

Machine Model Method 200 V.

3. Tlow =0°C for MC34167 Thigh = + 70°C for MC34167

=−40°C for MC33167 = + 85°C for MC33167

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ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = +25°C, for min/max values TA is the operating ambient

temperature range that applies (Notes 4, 5), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

OSCILLATOR

Frequency (VCC = 7.5 V to 40 V) TA = +25°C

TA = Tlow to Thigh fOSC 65

62 72

−79

81 kHz

ERROR AMPLIFIER

Voltage Feedback Input Threshold TA =+ 25°C

TA = Tlow to Thigh VFB(th) 4.95

4.85 5.05

−5.15

5.20 V

Line Regulation (VCC = 7.5 V to 40 V, TA = +25°C) Regline − 0.03 0.078 %/V

Input Bias Current (VFB = VFB(th) + 0.15 V) IIB − 0.15 1.0 mA

Power Supply Rejection Ratio (VCC = 10 V to 20 V, f = 120 Hz) PSRR 60 80 − dB

Output Voltage Swing High State (ISource = 75 mA, VFB = 4.5 V)

Low State (ISink = 0.4 mA, VFB = 5.5 V) VOH

VOL 4.2

−4.9

1.6 −

1.9 V

PWM COMPARATOR

Duty Cycle (VCC = 20 V) Maximum (VFB = 0 V)

Minimum (VComp = 1.9 V) DC(max)

DC(min) 92

095

0100

SWITCH OUTPUT

Output Voltage Source Saturation (VCC = 7.5 V, ISource = 5.0 A) Vsat − (VCC −1.5) (VCC −1.8) V

Off−State Leakage (VCC = 40 V, Pin 2 = GND) Isw(off) − 0 100 mA

Current Limit Threshold (VCC = 7.5 V) Ipk(switch) 5.5 6.5 8.0 A

Switching Times (VCC = 40 V, Ipk = 5.0 A, L = 225 mH, TA = +25°C)

Output Voltage Rise Time

Output Voltage Fall Time tr

tf−

−100

50 200

100

UNDERVOLTAGE LOCKOUT

Startup Threshold (VCC Increasing, TA = +25°C) Vth(UVLO) 5.5 5.9 6.3 V

Hysteresis (VCC Decreasing, TA = +25°C) VH(UVLO) 0.6 0.9 1.2 V

TOTAL DEVICE

Power Supply Current (TA = +25°C )

Standby (VCC = 12 V, VComp < 0.15 V)

Operating (VCC = 40 V, Pin 1 = GND for maximum duty cycle)

ICC −

−36

40 100

60 mA

4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

5. Tlow =0°C for MC34167 Thigh = + 70°C for MC34167

=−40°C for MC33167 = + 85°C for MC33167

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Figure 2. Voltage Feedback Input Threshold

versus Temperature Figure 3. Voltage Feedback Input Bias

Current versus Temperature

Figure 4. Error Amp Open Loop Gain and

Phase versus Frequency Figure 5. Error Amp Output Saturation

versus Sink Current

Figure 6. Oscillator Frequency Change

versus Temperature Figure 7. Switch Output Duty Cycle

versus Compensation Voltage

−20

AVOL , OPEN LOOP VOLTAGE GAIN (dB)

10 M10

f, FREQUENCY (Hz)

120

150

180

100 1.0 k 10 k 100 k 1.0 M

100

, EXCESS PHASE (DEGREES)

Gain

Phase

−12

−55

TA, AMBIENT TEMPERATURE (°C)

−25 0 25 50 75 100 125

−8.0

−4.0

4.0

VCC = 12 V

, OSCILLATOR FREQUENCY CHANGE (%)

OSC

fΔ

4.85

VFB(th), VOLTAGE FEEDBACK INPUT THRESHOLD (V

)

TA, AMBIENT TEMPERATURE (°C)

4.93

5.01

5.09

5.17

5.25

−55 −25 0 25 50 75 100 125

VCC = 12 V

IIB, INPUT BIAS CURRENT (nA)

TA, AMBIENT TEMPERATURE (°C)

100

−55 −25 0 25 50 75 100 125

Vsat, OUTPUT SATURATION VOLTAGE (V)

2.00

ISink, OUTPUT SINK CURRENT (mA)

0.4 0.8 1.2 1.6

0.4

0.8

1.2

1.6

2.0

VCC = 12 V

VFB = 5.5 V

TA = +25°C

DC, SWITCH OUTPUT DUTY CYCLE (%)

1.5

VComp, COMPENSATION VOLTAGE (V)

2.0 2.5 3.0 3.5 4.0

100

VCC = 12 V

TA = +25°C

4.5

VCC = 12 V

VComp = 3.25 V

RL = 100 k

TA = +25°C

VFB(th) Max = 5.15 V

VFB(th) Min = 4.95 V

VFB(th) Typ = 5.05 V

VCC = 12 V

VFB = VFB(th)

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Figure 8. Switch Output Source Saturation

versus Source Current Figure 9. Negative Switch Output Voltage

versus Temperature

Figure 10. Switch Output Current Limit

Threshold versus Temperature Figure 11. Standby Supply Current

versus Supply Voltage

Figure 12. Undervoltage Lockout

Thresholds versus Temperature Figure 13. Operating Supply Current

versus Supply Voltage

4.5

−55

TA, AMBIENT TEMPERATURE (°C)

−25 0 25 50 75 100 125

5.0

5.5

6.0

6.5

, UNDERVOLTAGE LOCKOUT THRESHOLD (V)

th(UVLO)

−2.5

ISource, SWITCH OUTPUT SOURCE CURRENT (A)

−2.0

−1.5

−1.0

−0.5

0 2.0 4.0 6.0 8.0

TA, AMBIENT TEMPERATURE (°C)

−55 −25 0 25 50 75 100 125

−3.0

Vsat, SWITCH OUTPUT SOURCE SATURATION (V)

−1.0

−0.8

−0.6

−0.4

−0.2

−1.2

Vsw, SWITCH OUTPUT VOLTAGE (V)

VCC = 12 V

Pin 5 = 2.0 V

Pins 1, 3 = GND

Pin 2 Driven Negative

GND

5.6

6.0

6.4

6.8

7.2

, CURRENT LIMIT THRESHOLD (A)

pk(switch)

−55 −25 0 25 50 75 100 125

VCC = 12 V

Pins 1, 2, 3 = GND

120

160

, SUPPLY CURRENT (

VCC, SUPPLY VOLTAGE (V)

10 20 30 40

Pin 4 = VCC

Pins 1, 3, 5 = GND

Pin 2 Open

TA = +25°C

μA)

4.0

, SUPPLY CURRENT (mA)

VCC, SUPPLY VOLTAGE (V)

10 20 30 40

Pin 4 = VCC

Pins 1, 3 = GND

Pins 2, 5 Open

TA = +25°C

TA, AMBIENT TEMPERATURE (°C)

Startup Threshold

VCC Increasing

TA = +25°C

VCC

Isw = 10 mA

Isw = 100 mA

Turn−Off Threshold

VCC Decreasing

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Figure 14. MC34167 Representative Block Diagram

CFRF

120

Error

Amp

5.05 V

Reference

Thermal

Shutdown

Oscillator S

Pulse Width

Modulator

PWM Latch

GND Compensation

100 mA

Undervoltage

Lockout

Voltage

Feedback

Input

Switch

Output

Current

Sense

Vin

Cin

Input Voltage/VCC

Sink Only

Positive True Logic

Figure 15. Timing Diagram

4.1 V

Timing Capacitor CT

Compensation

2.3 V

OFF

Switch Output

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INTRODUCTION

The MC34167, MC33167 series are monolithic power

switching regulators that are optimized for dc−to−dc

converter applications. These devices operate as fixed

frequency, voltage mode regulators containing all the active

functions required to directly implement step−down and

voltage−inverting converters with a minimum number of

external components. They can al s o be us ed cost effectively

in step−up converter applications. Potential markets include

automotive, computer, industrial, and cost sensitive

consumer products. A description of each section of the

device i s given below with the representative block diagram

shown in Figure 14.

Oscillator

The oscillator frequency is internally programmed to

72 kHz by capacitor CT and a trimmed current source. The

charge to discharge ratio is controlled to yield a 95%

maximum duty cycle at the Switch Output. During the

discharge o f C T, the oscillator generates an internal blanking

pulse that holds the inverting input of the AND gate high,

disabling the output switch transistor. The nominal

oscillator peak and valley thresholds are 4.1 V and 2.3 V

respectively.

Pulse Width Modulator

The Pulse Width Modulator consists of a comparator with

the oscillator ramp voltage applied to the noninverting input,

while the error amplifier output is applied into the inverting

input. Output switch conduction is initiated when CT is

discharged to the oscillator valley voltage. As CT charges to

a voltage that exceeds the error amplifier output, the latch

resets, terminating output transistor conduction for the

duration of the oscillator ramp−up period. This PWM/Latch

combination prevents multiple output pulses during a given

oscillator clock cycle. Figures 7 and 15 illustrate the switch

output duty cycle versus the compensation voltage.

Current Sense

The MC34167 series utilizes cycle−by−cycle current

limiting as a means of protecting the output switch t ransistor

from overstress. Each on cycle is treated as a separate

situation. C urrent l imiting i s i mplemented by monitoring the

output switch transistor current buildup during conduction,

and upon sensing an overcurrent condition, immediately

turning off the switch for the duration of the oscillator

ramp−u p period.

The collector current is converted to a voltage by an

internal trimmed resistor and compared against a reference

by the Current Sense comparator. When the current limit

threshold is reached, the comparator resets the PWM latch.

The current limit threshold is typically set at 6.5 A.

Figure 10 illustrates switch output current limit threshold

versus temperature.

Error Amplifier and Reference

A high gain Error Amplifier is provided with access to the

inverting input and output. This amplifier features a typical

dc voltage gain of 80 dB, and a unity gain bandwidth of

600 kHz with 70 degrees of phase margin (Figure 4). The

noninverting input is biased to the internal 5.05 V reference

and is not pinned out. The reference has an accuracy of

±2.0% at room temperature. To provide 5.0 V at the load,

the reference is programmed 50 mV above 5.0 V to

compensate for a 1.0% voltage drop in the cable and

connector from the converter output. If the converter design

requires an output voltage greater than 5.05 V, resistor R1

must be added to form a divider network at the feedback

input as shown in Figures 14 and 19. The equation for

determining the output voltage with the divider network is:

Vout +5.05 ǒR2

R1)1Ǔ

External loop compensation is required for converter

stability. A simple low−pass filter is formed by connecting

a resistor (R2) from the regulated output to the inverting

input, and a series resistor−capacitor (RF, CF) between Pins

1 and 5. The compensation network component values

shown in each of the applications circuits were selected to

provide stability over the tested operating conditions. The

step−down converter (Figure 19) is the easiest to

compensate for stability. The step−up (Figure 21) and

voltage−inverting (Figure 23) configurations operate as

continuous conduction flyback converters, and are more

difficult to compensate. The simplest way to optimize the

compensation network is to observe the response of the

output voltage to a step load change, while adjusting RF and

CF for critical damping. The final circuit should be verified

for stability under four boundary conditions. These

conditions are minimum and maximum input voltages, with

minimum and maximum loads.

By clamping the voltage on the error amplifier output

(Pin 5) to less than 150 mV, the internal circuitry will be

placed into a low power standby mode, reducing the

power s upply current t o 3 6 mA w ith a 1 2 V supply voltage.

Figure 11 illustrates the standby supply current versus

supply voltage.

The Error Amplifier output has a 100 mA current source

pull−up that can be used to implement soft−start. Figure 18

shows the current source charging capacitor CSS through a

series diode. The diode disconnects CSS from the feedback

loop when the 1.0 M resistor charges it above the operating

range of Pin 5.

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Switch Output

The output transistor is designed to switch a maximum of

40 V, wi th a m ini mum p eak c oll ector c urrent o f 5 .5 A . W hen

configured for step−down or volt age−inverting a ppli cati ons ,

as in Figures 19 and 23, the inductor will forward bias the

output rectifier when the switch turns off. Rectifiers with a

high forward vol t age drop or long turn on del a y t i me should

not be used. If the emitter is allowed to go sufficiently

negative, collector current will flow, causing additional

device heating and reduced conversion efficiency. Figure 9

shows that by clamping the emitter to 0.5 V, the collector

current will be in the range of 100 mA over temperature. A

1N5825 or equivalent Schottky barrier rectifier is

recommended to fulfill these requirements.

Undervoltage Lockout

An Undervoltage Lockout comparator has been

incorporated to guarantee that the integrated circuit is fully

functional before the output stage is enabled. The internal

reference voltage is monitored by the comparator which

enables t he output stage when V CC e xceeds 5.9 V. To p revent

erratic output switching as the threshold is crossed, 0.9 V of

hysteresis is provided.

Thermal Protection

Internal Thermal S hutdown c ircuitry i s p rovided t o p rotect

the i ntegrated c ircuit in the event that t he maxi mum j uncti on

temperature i s exceeded. W hen activated, t ypically at 1 70°C,

the latch is forced into a ‘reset’ state, disabling the output

switch. This feature is provided to prevent catastrophic

failures from accidental device overheating. It is not

intended t o b e u sed a s a s ubstitute f or p roper h eatsinking.

The MC34167 i s contained i n a 5 − l ead TO− 220 t ype p ackage.

The tab of the package is c ommon with the c enter pin (Pin 3)

and is normally connected to ground.

DESIGN CONSIDERATIONS

Do not attempt to construct a converter on wir e−wrap

or plug−in prototype boards. Special care should be taken

to separate ground paths from signal currents and ground

paths from load currents. All high current loops should be

kept as short as possible using heavy copper runs to

minimize ringing and radiated EMI. For best operation, a

tight component layout is recommended. Capacitors Cin,

CO, and all feedback components should be placed as close

to the IC as physically possible. It is also imperative that the

Schottky diode connected to the Switch Output be located as

close to the IC as possible.

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Figure 16. Low Power Standby Circuit Figure 17. Over Voltage Shutdown Circuit

Figure 18. Soft−Start Circuit

120

Error

Amp

Compensation

100 mA

I = Standby Mode VShutdown = VZener + 0.7

tSoft−Start ≈ 35,000 Css

Css

1.0 M

Vin

120

Error

Amp

Compensation

100 mA

120

Error

Amp

Compensation

100 mA

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CFRF

4700

5.05 V/5.0 A

Reference

Thermal

Oscillator S

PWM UVLO

ILIMIT

Vin

12 V

Cin

330

6.8 k

68 k0.1

1N5825

190 mH

Test Conditions Results

Line Regulation Vin = 10 V to 36 V, IO = 5.0 A 4.0 mV = ±0.039%

Load Regulation Vin = 12 V, IO = 0.25 A to 5.0 A 1.0 mV = ±0.01%

Output Ripple Vin = 12 V, IO = 5.0 A 20 mVpp

Short Circuit Current Vin = 12 V, RL = 0.1 W6.5 A

Efficiency Vin = 12 V, IO = 5.0 A

Vin = 24 V, IO = 5.0 A 78.9%

82.6%

L = Coilcraft M1496−A or General Magnetics Technology GMT−0223, 42 turns of #16 AWG

on Magnetics Inc. 58350−A2 core. Heatsink = AAVID Engineering Inc. 5903B, or 5930B.

The Step−Down Converter application is shown in Figure 19. The output switch transistor Q1 interrupts the input voltage, generating a

squarewave at the LCO filter input. The filter averages the squarewaves, producing a dc output voltage that can be set to any level between

Vin and V ref by controlling the percent conduction time of Q1 to that of the total oscillator cycle time. If the converter design requires an output

voltage greater than 5.05 V, resistor R1 must be added to form a divider network at the feedback input.

Figure 19. Step−Down Converter

ÉÉÉ

ÉÉÉÉÉ

(Top View)

Vin

Cin

+−

Figure 20. Step−Down Converter Printed Circuit Board and Component Layout

(Bottom View)

3.0″

″

1.9

MC34167 STEP−DOWN

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CFRF

1.5 k

2200

28 V/0.9 A

Reference

Thermal

Oscillator S

PWM UVLO

ILIMIT

Vin

12 V

Cin

330

6.8 k

4.7 k0.47

Q1D1

1N5825

*Gate resistor RG, zener diode D3, and diode D4 are required only when Vin is greater than 20 V.

190 mH

*RG

620

1N967A

1N5822

MTP3055EL

1N4148

Test Conditions Results

Line Regulation Vin = 10 V to 24 V, IO = 0.9 A 10 mV = ±0.017%

Load Regulation Vin = 12 V, IO = 0.1 A to 0.9 A 30 mV = ±0.053%

Output Ripple Vin = 12 V, IO = 0.9 A 140 mVpp

Short Circuit Current Vin = 12 V, RL = 0.1 W6.0 A

Efficiency Vin = 12 V, IO = 0.9 A

Vin = 24 V, IO = 0.9 A 80.1%

87.8%

L = Coilcraft M1496−A or General Magnetics Technology GMT−0223, 42 turns of #16 AWG on

Magnetics Inc. 58350−A2 core.

Heatsink = AAVID Engineering Inc. MC34167: 5903B, or 5930B MTP3055EL: 5925B

Figure 21 shows that the MC34167 can be configured as a step−up/down converter with the addition of an external power MOSFET. Energy

is stored in the inductor during the ON time of transistors Q1 and Q2. During the OFF time, the energy is transferred, with respect to ground,

to the output filter capacitor and load. This circuit configuration has two significant advantages over the basic step−up converter circuit. The first

advantage is that output short circuit protection is provided by the MC34167, since Q1 is directly in series with Vin and the load. Second, the

output voltage can be programmed to be less than Vin. Notice that during the OFF time, the inductor forward biases diodes D1 and D2, transferring

its energy with respect to ground rather than with respect to Vin. When operating with Vin greater than 20 V, a gate protection network is required

for the MOSFET. The network consists of components RG, D3, and D4.

Figure 21. Step−Up/Down Converter

ÎÎ

ÎÎÎÎÎ

ÎÎÎ

(Top View)

Vin

Cin

+−

(Bottom View)

Figure 22. Step−Up/Down Converter Printed Circuit Board and Component Layout

3.45

″

1.9

MC34167 STEP UP-DOWN

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CFRF

3.3 k

Reference

Thermal

Oscillator S

PWM UVLO

ILIMIT

Vin

12 V

Cin

330

2.4 k

4.7 k0.47

4700

−12 V/1.7 A

1N5825

190 mH

0.047

Test Conditions Results

Line Regulation Vin = 10 V to 24 V, IO = 1.7 A 15 mV = ±0.61%

Load Regulation Vin = 12 V, IO = 0.1 A to 1.7 A 4.0 mV = ±0.020%

Output Ripple Vin = 12 V, IO = 1.7 A 78 mVpp

Short Circuit Current Vin = 12 V, RL = 0.1 W5.7 A

Efficiency Vin = 12 V, IO = 1.7 A

Vin = 24 V, IO = 1.7 A 79.5%

86.2%

L = Coilcraft M1496−A or General Magnetics Technology GMT−0223, 42 turns of #16 AWG on

Magnetics Inc. 58350−A2 core. Heatsink = AAVID Engineering Inc. 5903B, or 5930B.

Two potential problems arise when designing the standard voltage−inverting converter with the MC34167. First, the Switch Output emitter is

limited to −1.5 V with respect to the ground pin and second, the Error Amplifier’s noninverting input is internally committed to the reference and

is not pinned out. Both of these problems are resolved by connecting the IC ground pin to the converter’s negative output as shown in Figure 23.

This keeps the emitter of Q1 positive with respect to the ground pin and has the effect of reversing the Error Amplifier inputs. Note that the voltage

drop across R1 is equal to 5.05 V when the output is in regulation.

Figure 23. Voltage−Inverting Converter

ÎÎÎ

ÎÎÎÎÎÎ

(Top View)

Vin

Cin

+−

Figure 24. Voltage−Inverting Converter Printed Circuit Board and Component Layout

(Bottom View)

3.0″

″

1.9

MC34167

VOLTAGE-INVERTING

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Figure 25. Triple Output Converter

VO1

5.0 V/3.0 A

Reference

Thermal

Oscillator S

PWM UVLO

ILIMIT

Vin

24 V

1000

6.8 k

68 k0.1

1N5825

1000

MUR110

VO3

−12 V/200 mA

VO2

12 V/250 mA

Tests Conditions Results

Line Regulation 5.0 V

12 V

−12 V

Vin = 15 V to 30 V, IO1 = 3.0 A, IO2 = 250 mA, IO3 = 200 mA 3.0 mV = ±0.029%

572 mV = ±2.4%

711 mV = ±2.9%

Load Regulation 5.0 V

12 V

−12 V

Vin = 24 V, IO1 = 30 mA to 3.0 A, IO2 = 250 mA, IO3 = 200 mA

Vin = 24 V, IO1 = 3.0 A, IO2 = 100 mA to 250 mA, IO3 = 200 mA

Vin = 24 V, IO1 = 3.0 A, IO2 = 250 mA, IO3 = 75 mA to 200 mA

1.0 mV = ±0.009%

409 mV = ±1.5%

528 mV = ±2.0%

Output Ripple 5.0 V

12 V

−12 V

Vin = 24 V, IO1 = 3.0 A, IO2 = 250 mA, IO3 = 200 mA 75 mVpp

20 mVpp

Short Circuit Current 5.0 V

12 V

−12 V

Vin = 24 V, RL = 0.1 W6.5 A

2.7 A

2.2 A

Efficiency TOTAL Vin = 24 V, IO1 = 3.0 A, IO2 = 250 mA, IO3 = 200 mA 84.2%

# TURNS(SEC) +VO(SEC) )VF(SEC)

ǒVO(PRI))VF(PRI)

#TURNS(PRI) Ǔ

Multiple auxiliary outputs can easily be derived by winding secondaries on the main output inductor to form a transformer. The secondarie

must be connected so that the energy is delivered to the auxiliary outputs when the Switch Output turns off. During the OFF time, the voltage

across the primary winding is regulated by the feedback loop, yielding a constant Volts/Turn ratio. The number of turns for any given secondar

voltage can be calculated by the following equation:

T1 = Primary: Coilcraft M1496−A or General Magnetics Technology GMT−0223, 42 turns of #16 AWG on Magnetics Inc. 58350−A2 core.

T1 = Secondary: VO2 − 69 turns of #26 AWG

T1 = Secondary: VO3 − 104 turns of #28 AWG

Heatsink = AAVID Engineering Inc. 5903B, or 5930B.

Note that the 12 V winding is stacked on top of the 5.0 V output. This reduces the number of secondary turns and improves lead regulation. For

best auxiliary regulation, the auxiliary outputs should be less than 33% of the total output power.

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+36 V/0.3 A

R1MUR415

0.01

1N5825

MTP

3055E

2N3906

36 k

5.1 k

+1000

VO+ǒR1

R2Ǔ)

0.22 470 k

Reference

Thermal

Oscillator S

PWM UVLO

ILIMIT

6.8 k

*Gate resistor RG, zener diode D3, and diode D4 are required only when Vin is greater than 20 V.

Vin

−12 V 1000

0.002

5.05 0.7

Test Conditions Results

Line Regulation Vin = −10 V to − 20 V, IO = 0.3 A 266 mV = ±0.38%

Load Regulation Vin = −12 V, IO = 0.03 A to 0.3 A 7.90 mV = ±1.1%

Output Ripple Vin = −12 V, IO = 0.3 A 100 mVpp

Efficiency Vin = −12 V, IO = 0.3 A 78.4%

L = General Magnetics Technology GMT−0223, 42 turns of #16 AWG on Magnetics Inc.

58350−A2 core. Heatsink = AAVID Engineering Inc. 5903B or 5930B

Figure 26. Negative Input/Positive Output Regulator

50 k

Faster

Brush

Motor

Reference

Thermal

Oscillator S

PWM

UVLO

ILIMIT

Vin

18 V

1000

5.6 k

56 k0.1

1N5825

1.0 k

Test Conditions Results

Low Speed Line Regulation Vin = 12 V to 24 V 1760 RPM ±1%

High Speed Line Regulation Vin = 12 V to 24 V 3260 RPM ±6%

Figure 27. Variable Motor Speed Control with EMF Feedback Sensing

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1000

+ +

MC34167

Step−Down

Converter

0.001

Output 1

MBR20100CT

1000+ +

MC34167

Step−Down

Converter

0.001

Output 2

MBR20100CT

1000+ +

MC34167

Step−Down

Converter

0.001

Output 3

MBR20100CT

0.01

RFI

Filter

100

3.3

1N4003

MJE13005

220

0.047

1N4937

100k T2

1N5404

115 VAC

T1 = Core and Bobbin − Coilcraft PT3595

T1 = Primary − 104 turns #26 AWG

T1 = Base Drive − 3 turns #26 AWG

T1 = Secondaries − 16 turns #16 AWG

T1 = Total Gap − 0.002,

T2 = Core − TDK T6 x 1.5 x 3 H5C2

T2 = 14 turns center tapped #30 AWG

T2 = Heatsink = AAVID Engineering Inc.

T2 = MC34167 and MJE13005 − 5903B

T2 = MBR20100CT − 5925B

The MC34167 can be used cost effectively in of f−line applications even though it is limited to a maximum input voltage of 40 V. Figure 28 shows

a simple and efficient method for converting the AC line voltage down to 24 V. This preconverter has a total power rating of 125 W with a

conversion efficiency of 90%. Transformer T1 provides output isolation from the AC line and isolation between each of the secondaries. The

circuit self−oscillates at 50 kHz and is controlled by the saturation characteristics of T2. Multiple MC34167 post regulators can be used to provide

accurate independently regulated outputs for a distributed power system.

Figure 28. Off−Line Preconverter

R , THERMAL RESISTANCE

JAθ

JUNCTION-TO-AIR ( C/W)°

1.0

1.5

2.0

2.5

3.0

3.5

010203025155.0

L, LENGTH OF COPPER (mm)

PD(max) for TA = +50°C

Minimum

Size Pad

2.0 oz. Copper

ÎÎÎÎ

Free Air

Mounted

Vertically

PD, MAXIMUM POWER DISSIPATION (W)

RqJA

Figure 29. D2PAK Thermal Resistance and Maximum

Power Dissipation versus P.C.B. Copper Length

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Table 1. Design Equations

Calculation

Step−Down Step−Up/Down Voltage−Inverting

toff

(Notes 1, 2)

Vout )VF

Vin *Vsat *Vout Vout )VF1)VF2

Vin *VsatQ1 *VsatQ2 |Vout|)VF

Vin*Vsat

ton

toff

foscǒton

toff )1Ǔ

ton

toff

foscǒton

toff )1Ǔ

ton

toff

foscǒton

toff )1Ǔ

Duty Cycle

(Note 3) ton fosc ton fosc ton fosc

L avg

out Ioutǒton

toff )1ǓIoutǒton

toff )1Ǔ

pk(switch) ILavg )DIL

2ILavg )DIL

LǒVin *Vsat *Vout

DILǓton ǒVin *VsatQ1 *VsatQ2

DILǓton ǒVin *Vsat

DILǓton

Vripple(pp) DILǒ1

8foscCoǓ2)(ESR)2

Ǹǒton

toff )1Ǔǒ1

foscCoǓ2)(ESR)2

Ǹǒton

toff )1Ǔǒ1

foscCoǓ2)(ESR)2

out VrefǒR2

R1)1ǓVrefǒR2

R1)1Ǔ

1. Vsat − Switch Output source saturation voltage, refer to Figure 8.

2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.35 V.

3. Duty cycle is calculated at the minimum operating input voltage and must not exceed the guaranteed minimum DC(max) specification of 0.92.

The following converter characteristics must be chosen:

Vout −

Iout −

DIL −

Vripple(pp) −

Desired output voltage.

Desired output current.

Desired peak−to−peak inductor ripple current. For maximum output current especially when the duty cycle is greater than 0.5

it is suggested that DIL be chosen minimum current limit threshold of 5.5 A. If the design goal is to use a minimum inductanc

value, let DIL = 2 (IL avg). This will proportionally reduce the converter’s output current capability.

Desired peak−to−peak output ripple voltage. For best performance, the ripple voltage should be kept to less than 2% of Vout

Capacitor C

should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications.

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ORDERING INFORMATION

Device Operating

Temperature Range Package Shipping†

MC33167D2T

TA= −40° to +85°C

D2PAK (Surface Mount) 50 Units / Rail

MC33167D2TG D2PAK (Surface Mount)

(Pb−Free) 50 Units / Rail

MC33167D2TR4 D2PAK (Surface Mount) 800 / Tape & Reel

MC33167D2TR4G D2PAK (Surface Mount)

(Pb−Free) 800 / Tape & Reel

MC33167T TO−220 (Straight Lead) 50 Units / Rail

MC33167TG TO−220 (Straight Lead)

(Pb−Free) 50 Units / Rail

MC33167TH TO−220 (Horizontal Mount) 50 Units / Rail

MC33167THG TO−220 (Horizontal Mount)

(Pb−Free) 50 Units / Rail

MC33167TV TO−220 (Vertical Mount) 50 Units / Rail

MC33167TVG TO−220 (Vertical Mount)

(Pb−Free) 50 Units / Rail

MC34167D2T

TA= 0° to +70°C

D2PAK (Surface Mount) 50 Units / Rail

MC34167D2TG D2PAK (Surface Mount)

(Pb−Free) 50 Units / Rail

MC34167D2TR4 D2PAK (Surface Mount) 800 / Tape & Reel

MC34167D2TR4G D2PAK (Surface Mount)

(Pb−Free) 800 / Tape & Reel

MC34167T TO−220 (Straight Lead) 50 Units / Rail

MC34167TG TO−220 (Straight Lead)

(Pb−Free) 50 Units / Rail

MC34167TH TO−220 (Horizontal Mount) 50 Units / Rail

MC34167THG TO−220 (Horizontal Mount)

(Pb−Free) 50 Units / Rail

MC34167TV TO−220 (Vertical Mount) 50 Units / Rail

MC34167TVG TO−220 (Vertical Mount)

(Pb−Free) 50 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

TO−220

TH SUFFIX

CASE 314A−03

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION D DOES NOT INCLUDE

INTERCONNECT BAR (DAMBAR) PROTRUSION.

DIMENSION D INCLUDING PROTRUSION SHALL

NOT EXCEED 0.043 (1.092) MAXIMUM.

DIM

MIN MAX MIN MAX

MILLIMETERS

0.572 0.613 14.529 15.570

INCHES

B0.390 0.415 9.906 10.541

C0.170 0.180 4.318 4.572

D0.025 0.038 0.635 0.965

E0.048 0.055 1.219 1.397

F0.570 0.585 14.478 14.859

G0.067 BSC 1.702 BSC

J0.015 0.025 0.381 0.635

K0.730 0.745 18.542 18.923

L0.320 0.365 8.128 9.271

Q0.140 0.153 3.556 3.886

S0.210 0.260 5.334 6.604

U0.468 0.505 11.888 12.827

−T− SEATING

PLANE

OPTIONAL

CHAMFER

D5X

0.014 (0.356) T

Q−P−

TO−220

TV SUFFIX

CASE 314B−05

ISSUE L

−P−

0.10 (0.254) P M

5X J

0.24 (0.610) T

OPTIONAL

CHAMFER

SLW

−T− SEATING

PLANE

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION D DOES NOT INCLUDE

INTERCONNECT BAR (DAMBAR) PROTRUSION.

DIMENSION D INCLUDING PROTRUSION SHALL

NOT EXCEED 0.043 (1.092) MAXIMUM.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.572 0.613 14.529 15.570

B0.390 0.415 9.906 10.541

C0.170 0.180 4.318 4.572

D0.025 0.038 0.635 0.965

E0.048 0.055 1.219 1.397

F0.850 0.935 21.590 23.749

G0.067 BSC 1.702 BSC

H0.166 BSC 4.216 BSC

J0.015 0.025 0.381 0.635

K0.900 1.100 22.860 27.940

L0.320 0.365 8.128 9.271

N0.320 BSC 8.128 BSC

Q0.140 0.153 3.556 3.886

S−−− 0.620 −−− 15.748

U0.468 0.505 11.888 12.827

V−−− 0.735 −−− 18.669

W0.090 0.110 2.286 2.794

5X D

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PACKAGE DIMENSIONS

TO−220

T SUFFIX

CASE 314D−04

ISSUE F

−Q−

12345

5 PL

0.356 (0.014) T

SEATING

PLANE

−T−

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.572 0.613 14.529 15.570

B0.390 0.415 9.906 10.541

C0.170 0.180 4.318 4.572

D0.025 0.038 0.635 0.965

E0.048 0.055 1.219 1.397

G0.067 BSC 1.702 BSC

H0.087 0.112 2.210 2.845

J0.015 0.025 0.381 0.635

K0.977 1.045 24.810 26.543

L0.320 0.365 8.128 9.271

Q0.140 0.153 3.556 3.886

U0.105 0.117 2.667 2.972

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION D DOES NOT INCLUDE

INTERCONNECT BAR (DAMBAR) PROTRUSION.

DIMENSION D INCLUDING PROTRUSION SHALL

NOT EXCEED 10.92 (0.043) MAXIMUM.

B1 0.375 0.415 9.525 10.541

DETAIL A−A

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D2PAK

D2T SUFFIX

CASE 936A−02

ISSUE C

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

5 REF

123

TERMINAL 6 NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A

AND K.

4. DIMENSIONS U AND V ESTABLISH A MINIMUM

MOUNTING SURFACE FOR TERMINAL 6.

5. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH OR GATE PROTRUSIONS. MOLD FLASH

AND GATE PROTRUSIONS NOT TO EXCEED 0.025

(0.635) MAXIMUM.

DIM

AMIN MAX MIN MAX

MILLIMETERS

0.386 0.403 9.804 10.236

INCHES

B0.356 0.368 9.042 9.347

C0.170 0.180 4.318 4.572

D0.026 0.036 0.660 0.914

E0.045 0.055 1.143 1.397

G0.067 BSC 1.702 BSC

H0.539 0.579 13.691 14.707

K0.050 REF 1.270 REF

L0.000 0.010 0.000 0.254

M0.088 0.102 2.235 2.591

N0.018 0.026 0.457 0.660

P0.058 0.078 1.473 1.981

R5 REF

S0.116 REF 2.946 REF

U0.200 MIN 5.080 MIN

V0.250 MIN 6.350 MIN

0.010 (0.254) T

−T−

OPTIONAL

CHAMFER

8.38

0.33

1.016

0.04

16.02

0.63

10.66

0.42

3.05

0.12

1.702

0.067

SCALE 3:1 ǒmm

inchesǓ

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its of ficers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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Phone: 81−3−5773−3850

MC34167/D

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