3 MHz, 600 mA, Low Quiescent Current Buck with 300 mA LDO Regulator ADP2140 FEATURES TYPICAL APPLICATION CIRCUITS VIN1 = 3.6V 100k CIN 10F + ADP2140 10 9 PG 8 EN1 7 VOUT2 = 1.8V COUT2 1F 6 + PG PGND SW EN1 AGND EN2 FB VOUT2 VIN2 1 1H VOUT = 1.2V 2 3 + 4 COUT 10F 5 07932-001 EN2 VIN1 Figure 1. ADP2140 with LDO Connected to VIN1 VIN1 = 3.3V 100k CIN 10F + ADP2140 10 9 PG 8 EN1 EN2 7 VOUT2 = 1.2V COUT2 1F 6 + VIN1 PG EN1 EN2 VOUT2 PGND SW AGND FB VIN2 1 1H VOUT = 1.8V 2 3 4 + COUT 10F 5 07932-002 Input voltage range: 2.3 V to 5.5 V LDO input (VIN2) 1.65 V to 5.5 V Buck output voltage range: 1.0 V to 3.3 V LDO output voltage range: 0.8 V to 3.3 V Buck output current: 600 mA LDO output current: 300 mA LDO quiescent current: 22 A with zero load Buck quiescent current: 20 A in PSM mode Low shutdown current: <0.3 A Low LDO dropout 110 mV @ 300 mA load High LDO PSRR 65 dB @ 10 kHz at VOUT2 = 1.2 V 55 dB @ 100 kHz at VOUT2 = 1.2 V Low noise LDO: 40 V rms at VOUT2 = 1.2 V Initial accuracy: 1% Current-limit and thermal overload protection Power-good indicator Optional enable sequencing 10-lead 0.75 mm x 3 mm x 3 mm LFCSP package Figure 2. ADP2140 with LDO Connected to Buck Output APPLICATIONS Mobile phones Personal media players Digital camera and audio devices Portable and battery-powered equipment GENERAL DESCRIPTION The ADP2140 includes a high efficiency, low quiescent 600 mA stepdown dc-to-dc converter and a 300 mA LDO packaged in a small 10-lead 3 mm x 3 mm LFCSP. The total solution requires only four tiny external components. The buck regulator uses a proprietary high speed current-mode, constant frequency, pulse-width modulation (PWM) control scheme for excellent stability and transient response. To ensure the longest battery life in portable applications, the ADP2140 has a power saving variable frequency mode to reduce switching frequency under light loads. The LDO is a low quiescent current, low dropout linear regulator designed to operate in a split supply mode with VIN2 as low as 1.65 V. The low input voltage minimum allows the LDO to be powered from the output of the buck regulator increasing efficiency and reducing power dissipation. The ADP2140 runs from input voltages of 2.3 V to 5.5 V allowing single Li+/Li- polymer cell, multiple alkaline/NiMH cell, PCMCIA, and other standard power sources. ADP2140 includes a power-good pin, soft start, and internal compensation. Numerous power sequencing options are userselectable through two enable inputs. In autosequencing mode, the highest voltage output enables on the rising edge of EN1. During logic controlled shutdown, the input disconnects from the output and draws less than 300 nA from the input source. Other key features include: undervoltage lockout to prevent deep battery discharge, soft start to prevent input current overshoot at startup, and both short-circuit protection and thermal overload protection circuits to prevent damage in adverse conditions. When the ADP2140 is used with two 0603 capacitors, one 0402 capacitor, one 0402 resistor, and one 0805 chip inductor, the total solution size is approximately 90 mm2 resulting in the smallest footprint solution to meet a variety of portable applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. ADP2140 TABLE OF CONTENTS Features .............................................................................................. 1 Short-Circuit Protection............................................................ 20 Applications ....................................................................................... 1 Undervoltage Lockout ............................................................... 20 General Description ......................................................................... 1 Thermal Protection .................................................................... 20 Typical Application Circuits............................................................ 1 Soft Start ...................................................................................... 20 Revision History ............................................................................... 2 Current Limit .............................................................................. 20 Specifications..................................................................................... 3 Power-Good Pin ......................................................................... 20 Recommended Specifications: Capacitors and Inductor ........ 4 LDO Section ............................................................................... 20 Absolute Maximum Ratings............................................................ 5 Applications Information .............................................................. 21 Thermal Data ................................................................................ 5 Power Sequencing ...................................................................... 21 Thermal Resistance ...................................................................... 5 Power-Good Function ............................................................... 24 ESD Caution .................................................................................. 5 External Component Selection ................................................ 24 Pin Configuration and Function Descriptions ............................. 6 Selecting the Inductor ................................................................ 24 Typical Performance Characteristics ............................................. 7 Output Capacitor........................................................................ 24 Buck Output .................................................................................. 7 Input Capacitor ........................................................................... 24 LDO Output ................................................................................ 14 Efficiency ..................................................................................... 25 Theory of Operation ...................................................................... 19 Recommended Buck External Components .......................... 25 Buck Section ................................................................................ 19 LDO Capacitor Selection .......................................................... 26 Control Scheme .......................................................................... 19 LDO as a Postregulator to Reduce Buck Output Noise ........ 26 PWM Operation ......................................................................... 19 Thermal Considerations ................................................................ 28 PSM Operation ........................................................................... 19 PCB Layout Considerations ...................................................... 29 Pulse Skipping Threshold .......................................................... 19 Outline Dimensions ....................................................................... 30 Selected Features ............................................................................. 20 Ordering Guide .......................................................................... 30 REVISION HISTORY 6/10--Revision 0: Initial Version Rev. 0 | Page 2 of 32 ADP2140 SPECIFICATIONS VIN1 = 3.6 V, VIN2 = VOUT2 + 0.3 V or 1.65 V, whichever is greater; 5 V EN1 = EN2 = VIN1; IOUT = 200 mA, IOUT2 = 10 mA, CIN = 10 F, COUT = 10 F, COUT2 = 1 F, LOUT = 1 H; TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameter BUCK SECTION Input Voltage Range Buck Output Accuracy Transient Load Regulation Transient Line Regulation PWM To PSM Threshold Output Current Current Limit Switch On Resistance PFET NFET Switch Leakage Current Quiescent Current Minimum On Time Oscillator Frequency Frequency Foldback Threshold Start-Up Time 1 Soft Start Time 2 LDO SECTION Input Voltage Range LDO Output Accuracy Symbol VIN1 VOUT VTR-LOAD VTR-LINE IOUT ILIM RPFET RNFET ILEAK-SW IQ ON-TIMEMIN FREQ VFOLD tSTART-UP SSTIME VIN2 VOUT2 Line Regulation Load Regulation 3 Dropout Voltage 4 VOUT2/VIN2 VOUT2/IOUT2 VDROPOUT Ground Current IAGND Power Supply Rejection Ratio PSRR on VIN2 PSRR Test Conditions/Comments IOUT = 10 mA VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V, IOUT = 1 mA to 600 mA VOUT = 1.8 V Load = 50 mA to 250 mA, rise/fall time = 200 ns Load = 200 mA to 600 mA, rise/fall time = 200 ns Line transient = 4 V to 5 V, 4 s rise time VOUT = 1.0 V VOUT = 1.8 V VOUT = 3.3 V VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V Min Typ 2.3 -1.5 -2.5 mV mV mV mA mA mA 250 250 Rev. 0 | Page 3 of 32 V % % 40 25 25 100 VIN1 = 2.3 V to 5.5 V VIN1 = 2.3 V to 5.5 V EN1 = GND, VIN1 = 5.5 V, and SW = 0 V No load, device not switching IOUT2 = 10 mA, TJ = 25C 1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V, TJ = 25C 1 mA < IOUT2 < 300 mA, VIN2 = (VOUT2 + 0.3 V) to 5.5 V VIN2 = (VOUT2 + 0.3 V) to 5.5 V, IOUT2 = 10 mA IOUT2 = 1 mA to 300 mA IOUT2 = 10 mA, VOUT2 = 1.8 V IOUT2 = 300 mA, VOUT2 = 1.8 V No load, buck disabled IOUT2 = 10 mA IOUT2 = 300 mA VIN2 = VOUT2 + 1 V, VIN1 = 5 V, IOUT2 = 10 mA 10 kHz, VOUT2 = 1.2 V, 1.8 V, 3.3 V 100 kHz, VOUT2 = 3.3 V 100 kHz, VOUT2 = 1.8 V 100 kHz, VOUT2 = 1.2 V 5.5 +1.5 +2.5 mV mV 1100 2.55 Unit 75 75 VIN1 = 2.3 V or (VOUT + 0.5 V) to 5.5 V Output voltage where fSW 50% of nominal frequency VOUT = 1.8 V, 600 mA load VOUT = 1.8 V, 600 mA load Max 20 70 3.0 50 70 150 600 1300 -1 30 3.15 m m A A ns MHz % s s 1.65 -1 -1.5 5.5 +1 +1.5 V % % -3 -0.05 +3 +0.05 0.005 7 200 35 90 220 % %/V %/mA mV mV A A A 0.001 4 110 22 65 150 65 53 54 55 dB dB dB dB ADP2140 Parameter Output Noise Current Limit Input Leakage Current Start-Up Time1 Soft Start Time2 ADDITIONAL FUNCTIONS Undervoltage Lockout Input Voltage Rising Input Voltage Falling EN Input EN1, EN2 Input Logic High EN1, EN2 Input Logic Low EN1, EN2 Input Leakage Shutdown Current Thermal Shutdown Threshold Hysteresis Power Good Rising Threshold Falling Threshold Power-Good Hysteresis Output Low Leakage Current Buck to LDO Delay Power-Good Delay Symbol OUTNOISE ILIM ILEAK-LDO tSTART-UP SSTIME Test Conditions/Comments VIN2 = VIN1 = 5 V, IOUT2 = 10 mA 10 Hz to 100 kHz, VOUT2 = 0.8 V 10 Hz to 100 kHz, VOUT2 = 1.2 V 10 Hz to 100 kHz, VOUT2 = 1.8 V 10 Hz to 100 kHz, VOUT2 = 2.5 V 10 Hz to 100 kHz, VOUT2 = 3.3 V TJ = 25C EN2 = GND, VIN2 = 5.5 V and VOUT2 = 0 V VOUT2 = 3.3 V, 300 mA load VOUT2 = 3.3 V, 300 mA load UVLO UVLORISE UVLOFALL VIH VIL IEN-LKG ISHUT TSSD TSSD-HYS PGRISE PGFALL PGHYS VOL IOH tDELAY tRESET Min Typ 360 29 40 50 66 88 500 Unit 760 1 70 130 2.05 2.3 V VIN1 5.5 V 2.3 V VIN1 5.5 V EN1, EN2 = VIN1 or GND EN1, EN2 = VIN1 or GND VIN1 = 5.5 V, EN1, EN2 = GND, TJ = -40C to +85C Max 2.23 2.16 2.3 1.0 0.27 0.05 0.3 TJ rising ISINK = 4 mA Power-good pin pull-up voltage = 5.5 V PWM mode only PWM mode only 1 1.2 V rms V rms V rms V rms V rms mA A s s V V V V A A A 150 20 C C 92 86 6 %VOUT %VOUT %VOUT V A ms ms 0.2 1 5 5 1 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 10% of the VOUTx nominal value. Soft start time is defined as the time between VOUTx being at 10% to VOUTx being at 90% of the VOUTx nominal value. Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 2 3 RECOMMENDED SPECIFICATIONS: CAPACITORS AND INDUCTOR Table 2. Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 Buck LDO CAPACITOR ESR Buck LDO MINIMUM INDUCTOR 1 Symbol Test Conditions/Comments Min Typ 7.5 0.7 10 1.0 Max Unit TA = -40C to +125C CMIN CMIN TA = -40C to +125C RESR RESR INDMIN 0.001 0.001 0.7 0.01 1 1 F F H The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. 0 | Page 4 of 32 ADP2140 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN1, VIN2 to PGND, AGND VOUT2 to PGND, AGND SW to PGND, AGND FB to PGND, AGND PG to PGND, AGND EN1, EN2 to PGND, AGND Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to VIN2 -0.3 V to VIN1 -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +6.5 V -65C to +150C -40C to +85C -40C to +125C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP2140 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 in. x 3 in. circuit board. Refer to JESD 51-7 for detailed information on the board construction. For more information, see AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) Refer to JESD51-8 and JESD51-12 for more detailed information about JB. THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 10-Lead 3 mm x 3 mm LFCSP ESD CAUTION TJ = TA + (PD x JA) Rev. 0 | Page 5 of 32 JA 35.3 JB 16.9 Unit C/W ADP2140 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 SW 2 AGND 3 FB VIN2 ADP2140 10 VIN1 9 PG TOP VIEW 8 (Not to Scale) 7 4 5 6 EN1 EN2 VOUT2 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GROUND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD. 07932-003 PGND Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin 1 2 3 4 5 6 7 8 Mnemonic PGND SW AGND FB VIN2 VOUT2 EN2 EN1 9 PG 10 VIN1 EP Description Power Ground. Connection from Power MOSFETs to Inductor. Analog Ground. Feedback from Buck Output. LDO Input Voltage. LDO Output Voltage. Logic 1 to Enable LDO or No Connect for Autosequencing. Logic 1 to Enable Buck or Initiate Sequencing. This is a dual function pin and the state of EN2 determines which function is operational. Power Good. Open-drain output. PG is held low until both output voltages (which includes the external inductor and capacitor sensed by the FB pin) rise above 92% of nominal value. PG is held high until both outputs fall below 85% of nominal value. Analog Power Input. Exposed Pad. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the circuit board. Rev. 0 | Page 6 of 32 ADP2140 TYPICAL PERFORMANCE CHARACTERISTICS BUCK OUTPUT 1.82 25 1.81 20 15 10 -40C -5C +25C +85C +125C 0 2.3 2.8 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 1.79 1.78 LOAD CURRENT = 1mA LOAD CURRENT = 10mA LOAD CURRENT = 50mA LOAD CURRENT = 100mA LOAD CURRENT = 300mA LOAD CURRENT = 600mA 1.77 1.76 -40 -5 25 85 125 JUNCTION TEMPERATURE (C) Figure 4. Quiescent Supply Current vs. Input Voltage, Different Temperatures Figure 7. Output Voltage vs. Temperature, VIN1 = 2.3 V, Different Loads 3.1 1200 2.3V 3.0V 4.0V 5.0V 5.5V 1150 CURRENT LIMIT (mA) 1100 2.9 2.8 2.7 +25C -40C -5C +85C +125C 2.6 2.5 2.3 2.8 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 900 850 -40 -20 0 20 40 60 80 100 140 Figure 8. Current Limit vs. Temperature, Different Input Voltages 140 120 100 2.90 2.85 2.80 2.75 80 60 40 -40C -5C +25C +85C +125C 2.70 20 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 140 07932-006 2.65 Figure 6. Switching Frequency vs. Temperature, Different Input Voltages Rev. 0 | Page 7 of 32 0 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 INPUT VOLTAGE (V) Figure 9. PSM to PWM Mode Transition vs. Input Voltage, Different Temperatures 07932-009 2.95 2.60 -60 120 JUNCTION TEMPERATURE (C) CURRENT (mA) FREQUENCY (MHz) 3.00 950 700 -60 5.5V 4.6V 3.1V 2.3V 3.05 1000 750 Figure 5. Switching Frequency vs. Input Voltage, Different Temperatures 3.10 1050 800 07932-005 FREQUENCY (MHz) 3.0 07932-008 5 1.80 07932-007 OUTPUT VOLTAGE (V) 30 07932-004 QUIESCENT CURRENT (A) VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. 1.82 3.350 OUTPUT VOLTAGE (V) 1.80 1.79 LOAD CURRENT LOAD CURRENT LOAD CURRENT LOAD CURRENT LOAD CURRENT LOAD CURRENT 1.77 1.76 2.3 2.7 3.1 3.5 3.9 = 1mA = 10mA = 50mA = 100mA = 300mA = 600mA 4.3 4.7 3.325 3.300 3.275 5.1 5.5 INPUT VOLTAGE (V) 3.250 1 10 100 1000 LOAD CURRENT (mA) Figure 10. Line Regulation, VOUT = 1.8 V, Different Loads 07932-013 1.78 07932-010 OUTPUT VOLTAGE (V) 1.81 Figure 13. Load Regulation, VOUT = 3.3 V 1.82 100 90 80 70 1.80 EFFICIENCY (%) 1.79 1.78 60 50 40 30 2.5V 3.0V 4.0V 5.0V 5.5V 20 1.77 10 1 10 100 1000 LOAD CURRENT (mA) 0 07932-011 1.76 Figure 11. Load Regulation, VOUT = 1.8 V, VIN1 = 2.3 V 1 10 100 1000 LOAD CURRENT (mA) 07932-014 OUTPUT VOLTAGE (V) 1.81 Figure 14. Efficiency vs. Load Current, VOUT = 1.8 V, Different Input Voltages 1.22 100 90 80 EFFICIENCY (%) 70 1.20 1.19 60 50 40 30 -40C -5C +25C +85C +125C 20 10 1.17 1 10 100 LOAD CURRENT (mA) Figure 12. Load Regulation, VOUT = 1.2 V, VIN1 = 2.3 V 1000 0 1 10 100 LOAD CURRENT (mA) 1000 07932-015 1.18 07932-012 OUTPUT VOLTAGE (V) 1.21 Figure 15. Efficiency vs. Load Current, VOUT = 1.8 V, Different Temperatures Rev. 0 | Page 8 of 32 ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 60 50 40 30 2.5V 3.0V 4.0V 5.0V 5.5V 10 0 1 10 100 10 1000 LOAD CURRENT (mA) Figure 16. Efficiency vs. Load Current, VOUT = 1.2 V, Different Input Voltages 0 1 90 80 80 70 70 EFFICIENCY (%) 100 50 40 100 1000 Figure 19. Efficiency vs. Load Current, VOUT = 3.3 V, Different Temperatures 90 60 10 LOAD CURRENT (mA) 100 60 50 40 30 30 -40C -5C +25C +85C +125C 10 0 1 10 100 20 1000 LOAD CURRENT (mA) Figure 17. Efficiency vs. Load Current, VOUT = 1.2 V, Different Temperatures T 4.0V 5.0V 5.5V 10 0 07932-017 20 1 10 100 1000 LOAD CURRENT (mA) 07932-018 EFFICIENCY (%) -40C -5C +25C +85C +125C 20 07932-016 20 07932-019 30 Figure 20. Efficiency vs. Load Current, VOUT = 3.3 V, Different Input Voltages T INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE 2 2 1 1 SWITCH NODE SWITCH NODE CH1 1.00V CH3 5.00V CH2 50.0mV M20.0s T 11.60% A CH1 4.68V 3 07932-020 3 Figure 18. Line Transient, VOUT = 1.8 V, Power Save Mode, 50 mA, VIN1 = 4 V to 5 V, 4 s Rise Time CH1 1.00V CH3 5.00V CH2 20.0mV M20.0s T 11.60% A CH1 4.68V 07932-021 EFFICIENCY (%) 100 Figure 21. Line Transient, VOUT = 1.8 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V, 4 s Rise Time Rev. 0 | Page 9 of 32 ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. T T INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE 2 2 1 1 SWITCH NODE CH1 1.00V CH3 5.00V CH2 50.0mV M20.0s T 11.60% A CH1 4.68V 3 07932-022 3 CH1 1.00V CH3 5.00V Figure 22. Line Transient, VOUT = 1.2 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V, 4 s Rise Time T CH2 20.0mV M20.0s T 11.60% A CH1 4.68V 07932-025 SWITCH NODE Figure 25. Line Transient, VOUT = 3.3 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V, 4 s Rise Time T INPUT VOLTAGE SWITCH NODE 3 LOAD CURRENT 2 OUTPUT VOLTAGE 1 1 2 SWITCH NODE CH1 1.00V CH3 5.00V CH2 20.0mV M20.0s T 10.80% A CH1 4.32V CH1 200mA CH3 5.00V Figure 23. Line Transient, VOUT = 1.2 V, PWM Mode, 600 mA, VIN1 = 4 V to 5 V, 4 s Rise Time T CH2 50.0mV M20.0s T 10.40% A CH1 288mA 07932-026 3 07932-023 OUTPUT VOLTAGE Figure 26. Load Transient, VOUT = 1.8 V, 200 mA to 600 mA, Load Current Rise Time = 200 ns T INPUT VOLTAGE SWITCH NODE 3 OUTPUT VOLTAGE LOAD OUTPUT 2 1 1 2 SWITCH NODE CH1 1.00V CH3 5.00V CH2 50.0mV M20.0s T 11.60% A CH1 4.68V CH1 100mA CH3 5.00V Figure 24. Line Transient, VOUT = 3.3 V, PSM Mode, 50 mA, VIN1 = 4 V to 5 V, 4 s Rise Time CH2 50.0mV M20.0s T 10.40% A CH1 136mA 07932-027 3 07932-024 OUTPUT VOLTAGE Figure 27. Load Transient, VOUT = 1.8 V, 50 mA to 250 mA, Load Current Rise Time = 200 ns Rev. 0 | Page 10 of 32 ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. T T SWITCH NODE SWITCH NODE 3 3 LOAD CURRENT LOAD CURRENT 1 1 2 2 CH2 50.0mV M20.0s T 10.40% A CH1 51.0mA 07932-028 CH1 50.0mA CH3 5.00V CH1 50.0mA CH3 5.00V Figure 28. Load Transient, VOUT = 1.8 V,10 mA to 110 mA, Load Current Rise Time = 200 ns CH2 100.0mV M20.0s T 10.40% A CH1 50.0mA 07932-031 OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 31. Load Transient, VOUT = 3.3 V,10 mA to 110 mA, Load Current Rise Time = 200 ns T T SWITCH NODE SWITCH NODE 3 3 LOAD CURRENT LOAD CURRENT 1 1 2 2 CH2 100.0mV M20.0s T 10.40% A CH1 292mA 07932-029 CH1 200mA CH3 5.00V CH1 200.0mA CH2 50.0mV CH3 5.00V Figure 29. Load Transient, VOUT = 3.3 V, 200 mA to 600 mA, Load Current Rise Time = 200 ns M20.0s T 10.40% A CH1 376mA 07932-032 OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 32. Load Transient, VOUT = 1.2 V, 200 mA to 600 mA, Load Current Rise Time = 200 ns T T SWITCH NODE 3 SWITCH NODE 3 LOAD CURRENT LOAD CURRENT 1 1 2 2 CH2 100.0mV M20.0s T 10.40% A CH1 80.0mA 07932-030 CH1 100mA CH3 5.00V CH1 100.0mA CH2 50.0mV CH3 5.00V Figure 30. Load Transient, VOUT = 3.3 V, 50 mA to 250 mA, Load Current Rise Time = 200 ns M20.0s T 10.40% A CH1 154mA 07932-033 OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 33. Load Transient, VOUT = 1.2 V, 50 mA to 250 mA, Load Current Rise Time = 200 ns Rev. 0 | Page 11 of 32 ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. T T 3 3 SWITCH NODE SWITCH NODE INDUCTOR CURRENT LOAD CURRENT 1 1 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE CH2 50.0mV M20.0s T 10.40% A CH1 48.0mA 4 07932-034 CH1 50.0mA CH3 5.00V CH1 500mA CH3 5.00V Figure 34. Load Transient, VOUT = 1.2 V,10 mA to 110 mA, Load Current Rise Time = 200 ns T CH2 2.00V CH4 5.00V M40.0s T 10.40% A CH4 2.70V 07932-037 ENABLE 1 2 Figure 37. Startup, VOUT = 3.3 V, 10 mA T SWITCH NODE 3 SWITCH NODE 3 INDUCTOR CURRENT INDUCTOR CURRENT 1 1 OUTPUT VOLTAGE OUTPUT VOLTAGE CH2 1.00V CH4 5.00V M100s T 10.40% A CH4 2.70V 4 07932-035 4 CH1 500mA CH3 5.00V ENABLE 1 2 CH1 500mA CH3 5.00V Figure 35. Startup, VOUT = 1.8 V, 10 mA CH2 2.00V CH4 5.00V M40.0s T 10.40% A CH4 2.70V 07932-100 ENABLE 1 2 Figure 38. Startup, VOUT = 3.3 V, 600 mA T T SWITCH NODE 3 SWITCH NODE 3 INDUCTOR CURRENT INDUCTOR CURRENT 1 1 OUTPUT VOLTAGE OUTPUT VOLTAGE ENABLE 1 2 2 CH2 1.00V CH4 5.00V M40.0s T 10.40% A CH4 2.70V 4 07932-036 CH1 500mA CH3 5.00V CH1 200mA CH3 5.00V Figure 36. Startup, VOUT = 1.8 V, 600 mA CH2 1.00V CH4 5.00V M100s T 10.40% A CH4 Figure 39. Startup, VOUT = 1.2 V, 10 mA Rev. 0 | Page 12 of 32 2.30V 07932-039 ENABLE 1 4 ADP2140 VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 F, TA = 25C, unless otherwise noted. T T BUCK OUTPUT 3 SWITCH NODE 1 LDO OUTPUT 2 1 INDUCTOR CURRENT OUTPUT VOLTAGE PG SIGNAL 3 ENABLE 1 CH1 500mA CH3 5.00V CH2 1.00V CH4 5.00V M40.0s T 10.00% A CH4 2.30V 4 07932-040 4 CH1 1.00V CH3 5.00V Figure 40. Startup, VOUT = 1.2 V, 600 mA CH2 1.00V CH4 5.00V M2.00ms T 10.00% A CH4 2.30V 07932-041 ENABLE 1 2 Figure 41. Startup, Autosequence Mode, VOUT = 1.8 V, VOUT2 = 1.2 V Rev. 0 | Page 13 of 32 ADP2140 LDO OUTPUT VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 F, TA = 25C, unless otherwise noted. 1.83 180 160 LOAD CURRENT = 1mA LOAD CURRENT = 5mA LOAD CURRENT = 10mA 1.82 GROUND CURRENT (A) 1.81 1.80 LOAD CURRENT = 1mA LOAD CURRENT = 5mA LOAD CURRENT = 10mA LOAD CURRENT = 50mA LOAD CURRENT = 100mA LOAD CURRENT = 300mA 1.78 1.77 -40 -5 25 100 80 60 40 85 125 Figure 42. Output Voltage vs. Junction Temperature, Different Loads 0 -40 140 1.810 120 GROUND CURRENT (A) 1.815 1.800 1.795 1.790 25 85 125 Figure 45. Ground Current vs. Junction Temperature, Different Loads 160 1.805 -5 JUNCTION TEMPERATURE (C) 1.820 100 80 60 40 10 100 1000 LOAD CURRENT (mA) 0 1 1.815 140 1.810 120 GROUND CURRENT (A) 160 1.805 1.800 1.795 LOAD CURRENT = 1mA LOAD CURRENT = 5mA LOAD CURRENT = 10mA LOAD CURRENT = 50mA LOAD CURRENT = 100mA LOAD CURRENT = 300mA 2.6 3.0 3.4 3.8 4.2 4.6 100 80 60 40 LOAD CURRENT = 1mA LOAD CURRENT = 5mA LOAD CURRENT = 10mA LOAD CURRENT = 50mA LOAD CURRENT = 100mA LOAD CURRENT = 300mA 20 5.0 5.4 INPUT VOLTAGE (V) 07932-244 1.780 2.2 1000 Figure 46. Ground Current vs. Load Current 1.820 1.785 100 LOAD CURRENT (mA) Figure 43. Output Voltage vs. Load Current 1.790 10 Figure 44. Output Voltage vs. Input Voltage, Different Loads 0 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 INPUT VOLTAGE (V) Figure 47. Ground Current vs. Input Voltage, Different Loads Rev. 0 | Page 14 of 32 07932-247 1 07932-243 1.780 07932-246 20 1.785 OUTPUT VOLTAGE (V) LOAD CURRENT = 50mA LOAD CURRENT = 100mA LOAD CURRENT = 300mA 20 JUNCTION TEMPERATURE (C) OUTPUT VOLTAGE (V) 120 07932-245 1.79 07932-242 OUTPUT VOLTAGE (V) 140 ADP2140 VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 F, TA = 25C, unless otherwise noted. 0.7 160 0.6 0.5 0.4 0.3 140 120 100 80 60 0.2 40 0.1 20 0 -50 -25 0 25 50 75 100 0 1.6 07932-048 SHUTDOWN CURRENT (A) 0.8 180 125 TEMPERATURE (C) 1.7 1.8 1.9 2.0 INPUT VOLTAGE (V) Figure 48. Shutdown Current vs. Temperature at Various Input Voltages Figure 51. Ground Current vs. Input Voltage (in Dropout) 150 0 -10 125 -20 300mA 100mA 10mA 1mA -30 100 PSRR (dB) DROPOUT VOLTAGE (mV) IGND = 1mA IGND = 5mA IGND = 10mA IGND = 50mA IGND = 100mA IGND = 300mA 07932-251 0.9 200 2.2V 2.6V 3.4V 3.8V 4.6V 5.5V GROUND CURRENT (A) 1.0 75 50 -40 -50 -60 -70 -80 25 10 100 1000 LOAD CURRENT (mA) 07932-249 1 -100 10 Figure 49. Dropout Voltage vs. Load Current 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 52. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.2 V, VIN1 = 5 V, VIN2 = 2.2 V 0 1.85 -10 1.80 -20 1.75 300mA 200mA 100mA 10mA 1mA -30 PSRR (dB) 1.70 1.65 1.60 1.55 1.50 1.45 1.60 1.65 1.70 1.75 1.80 1.85 1.90 = 1mA = 5mA = 10mA = 50mA = 100mA = 300mA 1.95 INPUT VOLTAGE (V) Figure 50. Output Voltage vs. Input Voltage (in Dropout) 2.00 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 07932-253 VDROP VDROP VDROP VDROP VDROP VDROP 07932-250 OUTPUT VOLTAGE (V) 100 07932-252 -90 0 Figure 53. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.2 V, VIN1 = 5 V, VIN2 = 1.7 V Rev. 0 | Page 15 of 32 ADP2140 VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 F, TA = 25C, unless otherwise noted. -20 -30 -40 -40 PSRR (dB) -30 -50 -60 -80 -80 -90 -90 -100 10 -100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 -10 -20 0 300mA 100mA 10mA 1mA -10 -20 -40 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -90 100k 1M 10M FREQUENCY (Hz) -100 10 07932-255 10k 1M 10M 300mA 200mA 100mA 10mA 1mA 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 55. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 1.8 V, VIN1 = 5 V, VIN2 = 2.8 V 10 100k -60 -80 1k 10k -50 -70 100 1k Figure 57. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 3.3 V, VIN1 = 5 V, VIN2 = 3.8 V -30 -100 10 100 FREQUENCY (Hz) Figure 54. Power Supply Rejection Ratio vs. Frequency, VOUT2 = 3.3 V, VIN1 = 5 V, VIN2 = 4.3 V PSRR (dB) -60 -70 100 300mA 200mA 100mA 10mA 1mA -50 -70 07932-254 PSRR (dB) -20 -10 07932-256 -10 0 300mA 100mA 10mA 1mA 07932-257 0 Figure 58. Power Supply Rejection Ratio vs. Frequency VOUT2 = 1.8 V, VIN1 = 5 V, VIN2 = 2.3 V 100 1.2V 1.8V 2.5V 3.3V 90 80 1.2V 1.8V 2.5V 3.3V 70 (V/ Hz) NOISE (V rms) 1 0.1 60 50 40 30 20 1k 10k 100k FREQUENCY (Hz) Figure 56. Output Noise Spectrum, VIN2 = 5 V, Load Current = 10 mA 0 100n 1 10 100 1m 10m 100m 1 LOAD CURRENT (A) Figure 59. Output Noise vs. Load Current and Output Voltage VIN2 = 5 V Rev. 0 | Page 16 of 32 07932-261 100 07932-055 10 0.01 10 ADP2140 VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 F, TA = 25C, unless otherwise noted. T T LOAD CURRENT VIN2 1 VOUT2 2 VOUT2 CH2 100mV M40.0s T 10.40% A CH1 68mA Figure 60. Load Transient Response, VIN2 = 4 V, VOUT2 = 1.2 V, 1 mA to 300 mA, Load Current Rise Time = 200 ns T CH1 1.00V CH2 5.00mV M2.00s T 10.20% A CH4 12mV 07932-263 CH1 100mA 1 07932-259 2 Figure 63. Line Transient Response, VOUT2 = 1.8 V, Load Current = 1 mA, VIN2 = 4 V to 5 V, 1 s Rise Time T LOAD CURRENT VIN2 1 VOUT2 2 VOUT2 CH2 100mV M40.0s T 10.40% A CH1 68mA 07932-260 CH1 100mA Figure 61. Load Transient Response, VIN2 = 4 V, VOUT2 = 1.8 V, 1 mA to 300 mA, Load Current Rise Time = 200 ns T CH1 1.00V CH2 5.00mV M2.00s T 10.20% A CH4 12mV 07932-264 1 2 Figure 64. Line Transient Response, VOUT2 = 1.2 V, Load Current = 1 mA, VIN2 = 4 V to 5 V, 1 s Rise Time T LOAD CURRENT VIN2 1 VOUT2 2 VOUT2 CH2 100mV M40.0s T 10.40% A CH1 68mA Figure 62. Load Transient Response, VIN2 = 4 V, VOUT2 = 3.3 V, 1 mA to 300 mA, Load Current Rise Time = 200 ns CH1 1.00V CH2 5.00mV M2.00s T 10.20% A CH4 12mV 07932-265 CH1 100mA 1 07932-262 2 Figure 65. Line Transient Response, VOUT2 = 3.3 V, Load Current = 1 mA, VIN2 = 4 V to 5 V, 1 s Rise Time Rev. 0 | Page 17 of 32 ADP2140 VIN1 = 5 V, VIN2 = 2.3 V, VOUT2 = 1.8 V, IOUT2 = 10 mA, CIN2 = COUT2 = 1 F, TA = 25C, unless otherwise noted. T T VIN2 VOUT2 2 VIN2 VOUT2 2 CH1 1.00V CH2 5.00mV M2.00s T 10.20% A CH4 12mV CH1 1.00V Figure 66. Line Transient Response, VOUT2 = 1.8 V, Load Current = 300 mA, VIN2 = 4 V to 5 V, 1 s Rise Time T VOUT2 CH2 5.00mV M2.00s T 10.20% A CH4 12mV 07932-267 1 CH1 1.00V M2.00s T 10.20% A CH4 12mV Figure 68. Line Transient Response, VOUT2 = 3.3 V, Load Current = 300 mA, VIN2 = 4 V to 5 V, 1 s Rise Time VIN2 2 CH2 5.00mV 07932-268 1 07932-266 1 Figure 67. Line Transient Response, VOUT2 = 1.2 V, Load Current = 300 mA, VIN2 = 4 V to 5 V, 1 s Rise Time Rev. 0 | Page 18 of 32 ADP2140 THEORY OF OPERATION SOFT START UVLO VIN1 CURRENT SENSE AMP FB Gm ERROR AMP REFERENCE 0.5V PWM/ PSM CONTROL 3MHz OSCILLATOR THERMAL SHUTDOWN VIN2 CURRENT LIMIT DRIVER AND ANTISHOOT THROUGH R1 ZERO-CROSS COMPARATOR R2 EN2 POWER GOOD EPAD ENABLE/ SEQUENCING 07932-068 EN1 PGND PG FB AGND SW Figure 69. Internal Block Diagram BUCK SECTION The ADP2140 contains a step-down dc-to-dc converter that uses a fixed frequency, high speed current-mode architecture. The high 3 MHz switching frequency and tiny 10-lead, 3 mm x 3 mm LFCSP package allow for a small step-down dc-to-dc converter solution. The ADP2140 operates with an input voltage from 2.3 V to 5.5 V. Output voltage options are 1.0 V, 1.1 V, 1.2 V, 1.5 V, 1.8 V, 1.875 V, 2.5 V, and 3.3 V. CONTROL SCHEME The ADP2140 operates with a fixed frequency, current-mode PWM control architecture at medium to high loads for high efficiency, but shifts to a variable frequency control scheme at light loads for lower quiescent current. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches adjust to regulate the output voltage, but when operating in power saving mode (PSM) at light loads, the switching frequency adjusts to regulate the output voltage. The ADP2140 operates in the PWM mode only when the load current is greater than the pulse skipping threshold current. At load currents below this value, the converter smoothly transitions to the PSM mode of operation. PWM OPERATION In PWM mode, the ADP2140 operates at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the P-channel MOSFET switch is turned on, putting a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the P-channel MOSFET switch and turns on the N-channel MOSFET synchronous rectifier. This puts a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the remainder of the cycle, unless the inductor current reaches zero, which causes the zero-crossing comparator to turn off the N-channel MOSFET. PSM OPERATION The ADP2140 has a smooth transition to the variable frequency PSM mode of operation when the load current decreases below the pulse skipping threshold current, switching only as necessary to maintain the output voltage within regulation. When the output voltage dips below regulation, the ADP2140 enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies the entire load current. Because the output voltage occasionally dips and recovers, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. PULSE SKIPPING THRESHOLD The output current at which the ADP2140 transitions from variable frequency PSM control to fixed frequency PWM control is called the pulse skipping threshold. The pulse skipping threshold has been optimized for excellent efficiency over all load currents. Rev. 0 | Page 19 of 32 ADP2140 SELECTED FEATURES SHORT-CIRCUIT PROTECTION The ADP2140 includes frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below 50% of the nominal output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/2 of the internal oscillator frequency. The reduction in the switching frequency gives more time for the inductor to discharge, preventing a runaway of output current. UNDERVOLTAGE LOCKOUT To protect against battery discharge, undervoltage lockout circuitry is integrated on the ADP2140. If the input voltage drops below the 2.15 V UVLO threshold, the ADP2140 shuts down and both the power switch and synchronous rectifier turn off. When the voltage rises again above the UVLO threshold, the soft start period initiates and the part is enabled. THERMAL PROTECTION In the event that the ADP2140 junction temperatures rises above 150C, the thermal shutdown circuit turns off the converter. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 20C hysteresis is included; thus, when thermal shutdown occurs, the ADP2140 does not return to operation until the on-chip temperature drops below 130C. When emerging from a thermal shutdown, soft start initiates. SOFT START The ADP2140 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. CURRENT LIMIT The ADP2140 has protection circuitry to limit the direction and amount of current to 1000 mA flowing through the power switch and synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output, and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. The ADP2140 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode. Under negative current limit conditions, both the highside and low-side switches are disabled. POWER-GOOD PIN The ADP2140 has a dedicated pin (PG) to signal the state of the monitored output voltages. The voltage monitor circuit has an active high, open-drain output requiring an external pull-up resistor typically supplied from the I/O supply rail, as shown in Figure 1. The voltage monitor circuit has a small amount of hysteresis and is deglitched to ensure that noise or external perturbations do not trigger the PG line. LDO SECTION The ADP2140 low dropout linear regulator uses an advanced proprietary architecture to achieve low quiescent current, and high efficiency regulation. It also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small 1 F ceramic output capacitor. The wide input voltage range of 1.65 V to 5.5 V allows it to operate from either the input or output of the buck. Supply current in shutdown mode is typically 0.3 A. Internally, the LDO consists of a reference, an error amplifier, a feedback voltage divider, and a pass device. The output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system ideally driving the feedback voltage to be equal to the reference voltage. If the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. If the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. The positive supply for all circuitry, except the pass device, is the VIN1 pin. The LDO has an internal soft start that limits the output voltage ramp period to approximately 130 s. The LDO is available in 0.8 V, 1.0 V, 1.1 V, 1.2 V, 1.3 V, 1.5 V, 2.5 V, 2.8 V, 3.0 V, and 3.3 V output voltage options. Rev. 0 | Page 20 of 32 ADP2140 APPLICATIONS INFORMATION POWER SEQUENCING Table 6. Power Sequencing Modes The ADP2140 has a flexible power sequencing system supporting two distinct activation modes: EN21 0 0 1 1 NC EN1 0 1 0 1 Rising edge NC Rising edge NC Rising edge NC Falling edge * Individual activation control is where EN1 controls only the buck regulator and EN2 controls only the LDO. A high level on Pin EN1 turns on the buck and a high level on Pin EN2 turns on the LDO. A logic low level turns off the respective regulator. Autosequencing is where the two regulators turn on in a specified order and delay after a low-to-high transition on the EN1 pin. Select the activation mode (individual or autosequence) by decoding the state of Pin EN2. The individual activation mode is selected when the EN2 pin is driven externally or hardwired to a voltage level (VIN1 or PGND). The autosequencing mode is selected when the EN2 pin remains unconnected (floating). To minimize quiescent current consumption, the mode selection executes one time only during the rising edge of VIN1. The detection circuit then activates for the time needed to assess the EN2 state, after which time the circuit is disabled until VIN1 falls below 0.5 V. When EN2 is unconnected, the internal control circuit provides a termination resistance to ground. The 100 k termination resistance is low enough to guarantee insensitivity to noise and transients. The termination resistor is disabled in the event that the EN2 pin is driven externally to a logic level high (individual activation mode assumed) to reduce the quiescent current consumption. When the autosequencing mode is selected, the EN1 pin is used to start the on/off sequence of the regulators. A logic high sequences the regulators on whereas a logic low sequences the regulators off. The regulator activation order is associated with the voltage selected for the buck regulator and the LDO. When the turn on or turn off autosequence starts, the start-up delay between the first and the second regulator is fixed to 5 ms in PWM mode (tREG12, as shown in Figure 71 and Figure 72). When the application requires activating and deactivating the regulators at the same time, use the individual activation mode, which connects the EN1 and EN2 pins together, as shown in Figure 75. 1 NC means not connected. Figure 70 to Figure 75 use the following symbols, as described in Table 7. Table 7. Timing Symbols Symbol tSTART tSS tRESET tREG12 Description Time needed for the internal circuitry to activate the first regulator Regulator soft start time Time delay from power-good condition to the release of PG Delay time between buck and LDO activation Typical Value 60 s 330 s 5 ms 5 ms V EN1 92% VBUCK VBUCK tSS EN2 92% V LDO 85% V LDO VLDO tSS PG tRESET Figure 70. Individual Activation Mode Rev. 0 | Page 21 of 32 TIME 07932-069 * Description Individual mode: both regulators are off. Individual mode: buck regulator is on. Individual mode: LDO regulator is on. Individual mode: both regulators are on. Autosequence: Buck regulator turns on, then the LDO regulator turns on. The LDO voltage is less than the buck voltage. Autosequence: LDO regulator turns on, then the buck regulator turns on. The LDO voltage is greater than the buck voltage. Autosequence: If the buck voltage is 1.875 V, then the LDO regulator always turns on first. Autosequence: The LDO and buck regulators turn off at the same time. ADP2140 V EN1 EN2 = UNCONNECTED 92% V BUCK 85% V BUCK VBUCK EN1 EN2 92% V BUCK 92% V LDO 85% VLDO VLDO VBUCK 92% VLDO tSS 85% VLDO PG 07932-073 tSTART VLDO tRESET tREG12 PG tRESET TIME 07932-111 tSS Figure 74. Individual Activation Mode, One Regulator Only (Buck) Sensed EN1 Figure 71. Autosequencing Mode, Buck First Then LDO EN2 V 92% VBUCK 85% V BUCK VBUCK EN2 = UNCONNECTED 92% V LDO 85% V LDO VLDO EN1 VLDO 07932-075 PG 92% V LDO tRESET tSTART 92% VBUCK tSS Figure 75. Individual Activation Mode, No Activation/Deactivation Delay Between Regulators, EN1 and EN2 Pins Tied Together 85% V BUCK VBUCK tREG12 T tSS tRESET TIME 07932-112 BUCK OUTPUT PG Figure 72. Autosequencing Mode, LDO First Then Buck 1 LDO OUTPUT 2 EN1 3 CH1 500mV CH3 2.00V CH2 500mV M1.00ms T 10.00% A CH3 1.16V 07932-101 The PG responds to the last activated regulator. As described in the Power Sequencing section, the regulator order in the autosequencing mode is defined by the voltage option combination. Therefore, if the sequence is buck first, the LDO and the PG signal are active low for tRESET after VLDO reaches 92% of the rated output voltage, at which time PG goes high and remains high for as long as VLDO is above 86% of the rated output voltage. When the sequencing is LDO first then buck, VBUCK controls PG. This control scheme also applies when the individual activation mode is selected. Figure 76. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V, LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA As soon as either regulator output voltage drops below 86% of the respective nominal level, the PG pin is forced low. T BUCK OUTPUT EN1 92% VBUCK 85% VBUCK VBUCK 95% 85% VBUCK VBUCK 1 LDO OUTPUT EN2 2 92% V LDO 85% VLDO VLDO EN1 tRESET 3 CH1 500mV CH3 2.00V Figure 73. Individual Activation Mode, Both Regulators Sensed CH2 500mV M40.0s T 10.00% A CH3 1.16V 07932-102 tRESET 07932-072 PG Figure 77. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V, LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA Rev. 0 | Page 22 of 32 ADP2140 T T LDO OUTPUT BUCK OUTPUT 1 2 BUCK OUTPUT LDO OUTPUT 1 2 EN1 CH2 500mV M40.0s T 10.00% A CH3 1.16V 3 07932-103 CH1 500mV CH3 2.00V CH1 500mV CH3 2.00V Figure 78. Autosequence Mode Turn On Behavior, Buck Voltage = 1.8 V, LDO Voltage = 1.2 V, Buck Load = 500 mA, LDO Load = 100 mA CH2 1.00V M40.0s T 10.00% A CH3 2.04V 07932-106 EN1 3 Figure 81. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V, LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA (Expanded Version of Figure 80) T BUCK OUTPUT LDO OUTPUT 1 2 BUCK OUTPUT LDO OUTPUT 1 2 EN1 CH2 1.00V M100ms A CH3 3.04V 07932-104 CH1 1.00V CH3 2.00V 3 CH1 500mV CH3 2.00V Figure 79. Autosequence Mode Turn On Behavior, Buck Voltage =1.8 V, LDO Voltage = 1.2 V, Buck Load = 1 mA, LDO Load = 100 mA T 2 CH2 1.00V M40.0s T 10.00% A CH3 2.04V 07932-107 EN1 3 Figure 82. Autosequence Mode Turn Off Behavior, Buck Voltage = 1.0 V, LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA LDO OUTPUT T 2 BUCK OUTPUT 1 LDO OUTPUT BUCK OUTPUT 1 EN1 CH1 500mV CH3 2.00V CH2 1.00V M2.00ms T 10.00% A CH3 2.04V 3 07932-105 3 Figure 80. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V, LDO Voltage = 3.3 V, Buck Load = 500 mA, LDO Load = 100 mA CH1 500mV CH3 2.00V CH2 1.00V M2.00ms T 10.00% A CH3 3.04V 07932-108 EN1 Figure 83. Autosequence Mode Turn On Behavior, Buck Voltage = 1.0 V, LDO Voltage = 3.3 V, Buck Load = 1 mA, LDO Load = 100 mA Rev. 0 | Page 23 of 32 ADP2140 T SELECTING THE INDUCTOR BUCK OUTPUT The high frequency switching of the ADP2140 allows the selection of small chip inductors. The inductor value affects the transition between CFM to PSM, efficiency, output ripple, and current limit values. Use the following equation to calculate the inductor ripple current: LDO OUTPUT 1 2 I L = EN1 CH1 500mV CH3 2.00V CH2 500mV M40.0s T 10.00% A CH3 1.16V where: fSW is the switching frequency (3 MHz typical). L is the inductor value. 07932-109 3 VOUT x (VIN - VOUT ) VIN x f sw x L Figure 84. Individual Activation Mode, EN1 and EN2 Pins Tied Together POWER-GOOD FUNCTION The ADP2140 power-good (PG) pin indicates the state of the monitored output voltages. The PG function is the logical AND of the state of both outputs. The PG function is an active high, open-drain output, requiring an external pull-up resistor typically supplied from the I/O supply rail, as shown in Figure 1. When the sensed output voltages are below 92% of their nominal value, the PG pin is held low. When the sensed output voltages rise above 92% of the nominal levels, the PG line is pulled high after tRESET. The PG pin remains high as long as the sensed output voltages are above 86% of the nominal output voltage levels. The typical PG delay when the buck is in PWM mode is 5 ms. When the part is in PSM mode, the PG delay is load dependent because the internal clock is disabled to reduce quiescent current during the sleep stage. PG delay varies from hundreds of microseconds at 10 mA, up to seconds at current loads of less than 10 A. The dc resistance (DCR) value of the selected inductor affects efficiency, but a decrease in this value typically means an increase in root mean square (rms) losses in the core and skin. As a minimum requirement, the dc current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple, as shown by the following equation: I PK = I LOAD ( MAX ) + ( I L ) 2 OUTPUT CAPACITOR Output capacitance is required to minimize the voltage overshoot and ripple present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple; therefore, use capacitors such as the X5R dielectric. Do not use the Y5V and Z5U capacitors; they are not suitable for this application because of their large variation in capacitance over temperature and dc bias voltage. Because ESR is important, select the capacitor using the following equation: ESRCOUT T EN1 VRIPPLE I L where: ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. 1 BUCK 2 Use the following equations to determine the output capacitance: LDO 3 C OUT VIN (2 x f SW )2 x L x VRIPPLE C OUT I L 8 x f SW x VOUT CH1 2.00V CH3 2.00V CH2 2.00V CH4 2.00V M2.00ms T 10.20% A CH1 2.20V 07932-285 PG 4 Figure 85. Typical PG Timing EXTERNAL COMPONENT SELECTION The external component selection for the ADP2140 application circuit that is shown in Table 8, Table 9, and Figure 86 is dependent on input voltage, output voltage, and load current requirements. Additionally, trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components. Increasing the output capacitor has no effect on stability and increasing the output capacitance may further reduce output ripple and enhance load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. INPUT CAPACITOR Input capacitance is required to reduce input voltage ripple; therefore, place the input capacitor as close as possible to the VINx pins. As with the output capacitor, a low ESR X7R- or X5R-type Rev. 0 | Page 24 of 32 ADP2140 capacitor is recommended to help minimize the input voltage ripple. Use the following equation to determine the minimum input capacitance: I CIN I LOAD ( MAX ) VOUT (VIN - VOUT ) VIN EFFICIENCY Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge, Q, from the input supply to the gate, and then from the gate to ground. Estimate switching losses using the following equation: Efficiency is defined as the ratio of output power to input power. The high efficiency of the ADP2140 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package, which in turn, reduces thermal constraints. In addition, high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. PSW = (CGATE_P + CGATE_N) x VIN2 x fSW where: CGATE_P is the gate capacitance of the internal high-side switch. CGATE_N is the gate capacitance of the internal low-side switch. fSW is the switching frequency. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of an SW node transition, the power switch provides all of the inductor current. The source-to-drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with both load current and input voltage and occur twice for each switching cycle. Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (RDS(ON)) associated with them. The amount of power loss can be approximated by PSW _ COND = (RDS(ON ) _ P x D + RDS(ON ) _ N x (1 - D)) x I OUT 2 Use the following equation to estimate transition losses: V where D = OUT VIN PTRAN = VIN/2 x IOUT x (tr + tf) x fSW The internal resistance of the power switches increases with temperature but decreases with higher input voltage. where: tr is the rise time of the SW node. tf is the fall time of the SW node. Inductor Losses RECOMMENDED BUCK EXTERNAL COMPONENTS Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger size inductors have smaller DCR, which can decrease inductor conduction losses. Inductor core losses relate to the magnetic permeability of the core material. Because the ADP2140 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. The recommended buck external components for use with the ADP2140 are listed in Table 8 (inductors) and Table 9 (capacitors). VIN1 = 3.6V ADP2140 10 9 PG 8 EN1 EN2 To estimate the total amount of power lost in the inductor, use the following equation: PL = DCR x IOUT2 + Core Losses + 7 VOUT2 = 1.8V COUT2 1F 6 + VIN1 PG PGND SW EN1 AGND EN2 FB VOUT2 VIN2 1 1H VOUT = 1.2V 2 3 4 + COUT 10F 5 07932-076 CIN 10F 100k Figure 86. Typical Application Circuit with LDO Connected to Input Voltage Table 8. 1.0 H Inductors Vendor Murata Murata Murata FDK Model LQM21PN1R0MC0D LQM31PN1R0M00L LQM2HPN1R0MJ0 MIPSA2520D1R0 Case Size 0805 1206 1008 Dimensions 2.0 mm x 1.25 mm x 0.5 mm 3.2 mm x 1.6 mm x 0.95 mm 2.5 mm x 2.0 mm x 0.95 mm 2.5 mm x 2.0 mm x 1.0 mm ISAT (mA) 800 1200 1500 1200 Table 9. 10 F Capacitors Vendor Murata Taiyo Yuden TDK Type X5R X5R X5R Model GRM219R60J106 JMK212BJ106 C1608X5R0J106 Rev. 0 | Page 25 of 32 Case Size 0805 0805 0603 Voltage Rating 6.3 V 6.3 V 6.3 V DCR (m) 190 120 90 90 ADP2140 Output Capacitor The ADP2140 LDO is designed for operation with small, spacesaving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken about the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP2140. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP2140 to large changes in load current. Figure 87 shows the transient response for an output capacitance value of 1 F. 1.2 MURATA PART NUMBER: GRM155R61A105KE15 1.0 0.8 0.6 0.4 0.2 LOAD CURRENT 0 0 2 4 6 VOLTAGE (V) 8 10 07932-077 T rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating. CAPACITANCE (F) LDO CAPACITOR SELECTION Figure 88. Capacitance vs. Voltage Characteristic Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. 1 CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) VOUT2 2 CH2 100mV M40.0s T 10.40% A CH1 68mA where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. 07932-286 CH1 100mA (1) Figure 87. Output Transient Response, VOUT2 = 1.8 V, COUT = 1 F, 1 mA to 300 mA, Load Current Rise Time = 200 ns Input Bypass Capacitor Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP2140, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 88 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V as shown in Figure 88. Substituting these values in Equation 1 yields CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP2140, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. LDO AS A POSTREGULATOR TO REDUCE BUCK OUTPUT NOISE The output of the buck regulator may not be suitable for many noise sensitive applications because of its inherent switching noise. This is particularly true when the buck is operating in PSM mode because the switching noise may be in the audio range. The ADP2140 LDO can greatly reduce the noise at the output of the buck at high efficiency because of the load dropout voltage of the LDO and the high PSRR of the LDO. Figure 89 and Figure 90 show the noise reduction that is possible when the LDO is used as a post regulator. Rev. 0 | Page 26 of 32 ADP2140 T T BUCK OUTPUT VOLTAGE BUCK OUTPUT VOLTAGE 1 1 LDO OUTPUT VOLTAGE LDO OUTPUT VOLTAGE CH1 50.0mV CH2 10.0mV M40.0s T 48.00% A CH1 -27.0mV CH1 10.0mV Figure 89. LDO as a Postregulator (see Figure 2), VOUT = 1.8 V, Load Current = 50 mA, VOUT2 = 1.2 V, Load Current = 50 mA CH2 10.0mV M2.00s T 48.00% A CH1 800V Figure 90. LDO as a Postregulator (see Figure 2), VOUT = 1.8 V, Load Current = 500 mA, VOUT2 = 1.2 V, Load Current = 50 mA Rev. 0 | Page 27 of 32 07932-067 2 07932-066 2 ADP2140 THERMAL CONSIDERATIONS In most applications, the ADP2140 does not dissipate much heat due to its high efficiency. However, in applications with high ambient temperature and high supply voltage-to-output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125C. where: ILOAD is the LDO load current. IAGND is the analog ground current. VIN and VOUT are the LDO input and output voltages, respectively. PSW, PTRAN, and PSW_COND are defined in the Efficiency section. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 130C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. For a given ambient temperature and total power dissipation, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125C. The following figures show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. 135 105 95 85 75 65 55 500mm 2 50mm 2 0mm2 TJ MAX 35 25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 TOTAL POWER DISSIPATION (W) Figure 91. Junction Temperature vs. Power Dissipation, TA = 25C 140 JA (C/W) 42.5 40.0 38.8 37.2 36.2 130 The device is soldered to minimum size pin traces. The junction temperature of the ADP2140 can be calculated from the following equation: TJ = TA + (PD x JA) (2) where: TA is the ambient temperature. PD is the total power dissipation in the die, given by 120 110 100 90 80 70 500mm 2 50mm 2 0mm2 TJ MAX 60 50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 TOTAL POWER DISSIPATION (W) Figure 92. Junction Temperature vs. Power Dissipation, TA = 50C PD = PLDO + PBUCK where: PLDO = [(VIN - VOUT) x ILOAD] + (VIN x IAGND) (3) PBUCK = PSW + PTRAN + PSW_COND (4) Rev. 0 | Page 28 of 32 07932-079 JUNCTION TEMPERATURE (C) 1 115 45 Table 10. Typical JA Values Copper Size (mm2) 01 50 100 300 500 125 07932-078 JUNCTION TEMPERATURE (C) To guarantee reliable operation, the junction temperature of the ADP2140 must not exceed 125C. To ensure the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. Table 10 shows typical JA values of the 10-lead, 3 mm x 3 mm LFCSP for various PCB copper sizes. 145 JUNCTION TEMPERATURE (C) ADP2140 145 PCB LAYOUT CONSIDERATIONS 135 Improve heat dissipation from the package by increasing the amount of copper attached to the pins of the ADP2140. However, as listed in Table 10, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 125 115 105 Poor layout can affect the ADP2140 buck performance causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance, ground bounce, and voltage losses; thus, regulation and stability can be affected. Implement a good layout using the following rules: 95 85 500mm 2 50mm 2 0mm 2 TJ MAX 65 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TOTAL POWER DISSIPATION (W) * 07932-080 75 Figure 93. Junction Temperature vs. Power Dissipation, TA = 65C 135 * JUNCTION TEMPERATURE (C) 125 * 115 * 105 Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies and long, large tracks act like antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Use a ground plane with several vias connected to the component-side ground to reduce noise interference on sensitive circuit nodes. Use of 0402- or 0603-size capacitors achieves the smallest possible footprint solution on boards where area is limited. 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 TOTAL POWER DISSIPATION (W) 07932-081 500mm 2 50mm 2 0mm 2 TJ MAX 95 Figure 94. Junction Temperature vs. Power Dissipation, TA = 85C TJ = TB + (PD x JB) (5) 07932-083 In cases where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula Figure 96. PCB Layout, Top The typical JB value for the 10-lead, 3 mm x 3 mm LFCSP is 16.9C/W. 120 100 80 07932-084 60 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TOTAL POWER DISSIPATION (W) Figure 97. PCB Layout, Bottom 07932-082 JUNCTION TEMPERATURE (C) 140 Figure 95. Junction Temperature vs. Power Dissipation Rev. 0 | Page 29 of 32 ADP2140 OUTLINE DIMENSIONS 0.30 0.23 0.18 3.00 BSC SQ 0.50 BSC 10 6 PIN 1 INDEX AREA 0.50 0.40 0.30 5 TOP VIEW 0.80 MAX 0.55 NOM SEATING PLANE 1 2.48 2.38 2.23 PIN 1 INDICATOR (R 0.20) 0.05 MAX 0.02 NOM 0.20 REF *FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 031208-B 0.80 0.75 0.70 1.74 1.64 1.49 *EXPOSED PAD (BOTTOM VIEW) Figure 98. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP2140ACPZ1218R7 ADP2140ACPZ1228R7 ADP2140ACPZ1233R7 ADP2140ACPZ1528R7 ADP2140ACPZ1533R7 ADP2140ACPZ1812R7 ADP2140ACPZ1815R7 ADP2140ACPZ1833R7 ADP2140ACPZ18812R7 ADP2140ACPZ2518R7 ADP2140ACPZ3312R7 ADP2140ACPZ3315R7 ADP2140ACPZ3318R7 ADP2140ACPZ3325R7 ADP2140ACPZ3328R7 ADP2140CP-EVALZ Buck Output Voltage (V) 1.2 1.2 1.2 1.5 1.5 1.8 1.8 1.8 1.875 2.5 3.3 3.3 3.3 3.3 3.3 LDO Output Voltage (V) 1.8 2.8 3.3 2.8 3.3 1.2 1.5 3.3 1.2 1.8 1.2 1.5 1.8 2.5 2.8 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C ADP2140CPZ-REDYKIT 1 Z = RoHS Compliant Part. Rev. 0 | Page 30 of 32 Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD Evaluation Board Evaluation Board Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 Branding LET LEQ LER LES LEX LEU LEY LEZ LH8 LGE LF0 LF1 LF2 LF4 LF3 ADP2140 NOTES Rev. 0 | Page 31 of 32 ADP2140 NOTES (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07932-0-6/10(0) Rev. 0 | Page 32 of 32