BURR-BROWN CORP WLE D WM 1731365 00159069 4 MMBUB BURR-BROWN 1 FEATURES @ COMPLETE 12-BIT DATA ACQUISITION SYTEM IN A MINIATURE PACKAGE @ INPUT RANGES SELECTABLE FOR UNIPOLAR OR BIPOLAR OPERATION @ THROUGHPUT RATES: 862/3 9872/3 8-BIT ACCURACY: 45kHz 67kHz 12-BIT ACCURACY: 33kHz 50kHz @ SELECTABLE GAINS OF 1, 10, AND 100 @ FULL MICROPROCESSOR COMPATIBLE INTERFACE @ GUARANTEED NO MISSING CODES OVER TEMPERATURE @ SURFACE-MOUNT OR PIN GRID ARRAY PACKAGE OPTIONS @ HIGH RELIABILITY SCREENED VERSIONS AVAILABLE @ FULL SPECIFICATION OVER THREE TEMPERATURE RANGES: 0 to +70C, 25 to +85C, 55 to +125C @ EVERY UNIT SUPPLIED WITH ELECTRICAL TEST DATA APPLICATIONS @ INDUSTRIAL PROCESS MONITORING @ AIRBORNE SYSTEMS MONITORING @ ENGINE MONITORING T-St-O7-Ol SDM862 SDM863 SDM872 SDM873 ee 6 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS @ POWER PLANT MONITORING @ SECURITY SYSTEMS MONITORING @ AUTOMATIC TEST EQUIPMENT DESCRIPTION 16 SDM862 8 SDM863 SDM872 SDM873 SD Rate: SD The SDM components are complete, pin-compatible, data acquisition systems housed in ahermetically sealed 1"-square leadless chip carrier or a 1.1"-square pin grid array. The small package outlines and low power con- sumption provide an ideal data acquisition solution when space is at a premium. The devices comprise of an input multiplexer, instru- mentation amplifier with selectable gains, sample/hold amplifier and A/D converter with microprocessor inter- face and three-state buffers. The SDM family will accept unipolar or bipolar voltage inputs in the range 0 to +10V, 5V and 10V. For low- level signals, jumper-selectable gains of 10 or 100 can be applied. The number of input channels can be ex- panded by the addition of multiplexers. System integra- tion is simplified by the microprocessor interface and the facility of the sample/hold amplifier being controlled directly by the A/D converter. Tel: (602) 746-1191 | Twx: 910-952-1111 ANALOG 3 DIGITAL MUX : = = ADC 12 Bits 862/872 863/873 international Airport Industrial Park + Malling Address: PO Box 11400 + Tucson, AZ 65734 + Street Address: 6790 S, Tucson Blvd. + Tucson, AZ 85706 + Cable:BBRCORP + Telex:066-6491 FAX: (602)669-1510 + immediate Product info: (800) 548-6192 1988 Burr-Brown Corporation ( PDS-686D Printed in U.S.A. July, 1991T-51-07-01 BURR-BROWN CORP YLE D MM 1731365 001959070 S MEBUB be 5 o ~~ 3 ou o Se 8 5 > 820 i Ss - 2 2 2 sf, 22 282 2588 a a BS 8 So Of 3 3S sam Q an a Zao 5 2 q= 935 a2 069 2 a oo 6 2 OH B05 EL Ts5Et 833 3 S en en a ~Aaooec = = oO 00 5 _o +|-|- CHO CHO + 16 Single-Ended + CH7 8 Differential as S CHO Input P - Multiplexer - CH 15 CH7 see hh, , 2 9 0 9, (Output MUX Minus) 9 Q 3% 3 Only on SDM863/873 8 5 8 S18 als 3 a2 c 8 E eee & 8 ~ 8 8 glo'a o = ase 23 a = 205 & ac SPECIFICATIONS ELECTRICAL At +25C, V._= t15V, V,, = 5V, external sample/hold capacitor of 4700pF. All grades are burned-In at +125C for 48 hours min. SDM862/863/872/873 J, A, R SDM862/853/872/873 K, B, S PARAMETER MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 BITS INPUT ANALOG I Voltage Ranges: Bipolar 5, 10 Vv Unipolar 0-10 Vv Input Impedance: On Channe! 10 Q Off Channel 10 Q Input Capacitance: On Channel 20 pF Off Channel 20 * pF CMRR (20VDC to 1kHz) 80 85 . * dB Crosstalk (20Vp-p, 1kHz) -85 -80 , dB Feedthrough (at 1kHz) | -85 -80 . . dB Offset (channel to channel) G = 1 @ 30 100 . . Vv Input Bias Current/Channel 1 5 . . nA Input Voltage Range +10 +1 * * Vv -10 -15 . * Vv DIGITAL MUX input Channel Select: Logic 1' 5 30 . . pA Logic 0 5 30 . pA MUX Input; Logic High 4.0 Vv Logic Low 0.8 * v S/H Command: Logic 1 0.2 . nA Logic 0 30 . . pA ADC Section: Logic 1 10 , pA Lagic o' 10 * pA TRANSFER CHARACTERISTICS ACCURACY integral Linearity 0.024 0,012 %FSR Differential Linearity +0,024 * %FSR No Missing Codes Over Operating Temperature Range Gain Error ): G = 1 0.5 . % G=100 0.9 . % Unipolar Offset Error 16 * mV Bipolar Offset Error ) 50 mV Noise Error (Measured at S/H Output) G = 1 0.5 1 * * mVp-p Droop Rate 50 500 * * pV/ms Temperature Coefficients: Unipolar Offset 20 15 ppm of FSAPC Bipolar Offset 30 25 ppm of FSA/C Full-Scale Calibration 60 35 ppm of FSALCBURR-BROWN CORP SPECIFICATIONS ELECTRICAL ULE D MM 1732365 0019071 7 ME BUB At +25C, V.,. = +15V, V,, = SV, external sampleshold capacitor of 4700pF. T-51-07-01 SDM&62/653/872/673 J, A, R SDM&62/863/872/873 K, B, S PARAMETERS MIN | TYP MAX MIN TYP MAX UNITS SYSTEM TIMINGS ADC Conversion Time: SDM862/SDM863 9 20 25 . . . ps SDM872/SDM873 9 12 15 * ps S/H Aperture Delay 50 . ns S/H Aperture Uncertainty 2 . ns TIMING Throughput (Serial Mode) SDM862/SDM863 22 kHz $DM872/SDM873 28 kHz (Overlap Mode): SDM862/SDM863 33 kHz SDM872/SDM873 50 kHz MULTIPLEXER ) Switching Time (between channels) +15 . pS Settling Time (10V step to 0.02%) 2.5 . ps Enable Time ON' 1 2 * ps OFF' 0.25 05 us INSTRUMENTATION AMPLIFIER Settling Time (20V step to 0.01%) G=1 5 12.5 . ps Gu=10 3 75 . . ps G=100 4 7.5 ys Slew Rate 12 17 . . Vips S/H AMPLIFIER Acquisition (10V step to 0.01%) 5 * ps Aperture Delay 50 . ns Hold Mode Settling Time 1.5 . us Slew Rate 10 VinS OUTPUT DIGITAL DATA Output Codes: Unipolar Unipolar Straight Binary (USB) Bipolar Bipolar Offset Binary (BOB) Logic Levels: Logic 0 (Sink = 1.6mA) +0.4 . Vv Logic 1 (Source = 500A) +2.4 . Vv Leakage (Data Bits Only), High-Z State +5 0.1 +5 * pA POWER SUPPLY REQUIREMENTS Rated Voltage: Analog (V,.) 14.25 15 15.75 . . vbc Digital (V,,,) 45 5 5.5 * . vpc Supply Drain: +15V 28 40 mA -15V 36 45 . . mA +5V 8 15 . . mA Power Dissipation 1 1.4 . Ww TEMPERATURE RANGE Operating Temperature Range JH, KH/JL, KL 0 70 . C AH, BH/AL, BL 25 +85 . C RH, SH/RL, SL -55 4125 . C Storage Temperature Range -65 +150 * * i) * Specification same as SDM862/863/872/8734, A, R grades. NOTES: (1) Measured at the same and hold output. (2) Measured with all input channels grounded. (3) The range of voltage on any input with respect to common over whichaccuracy and leakage current is guaranteed. (4) Applicable over full operating temperature range. NOMISSING CODES GUARANTEED OVER TEMPERATURE RANGE. (5) Adjustable to zero using external potentiometer or select-on-test resistor. (6) Specifications are at +25C and measured at 50% level of transition. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibllity for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circults described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.BURR=BROWN CORP ULE D MM 1731365 6019072 9 MBUB 4 T-51-07~01 DIGITAL TIMING ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER MIN | TYP | MAX |UNITS +V,, to ACOM 0,5V to +16V ~V,, to ACOM +0.5 to-16V CONVERT MODE +V,, to DCOM ~0.5V to +7.0V tdse Status Delay from CE 100 | 200 | ns Analog Input Signal RANGG .....scssssssccssssssssssresees 1 #V eq +20V to V,,, -20V thec CE Pulse Width 50 | 30 ns Digital Input Signal -0.5V to +V,, } {sso CS to CE Setup 50 20 ns ACOM to DCOM +1V thse GS Low During CE High 50 | 20 ns . tsrc RIG to CE Setup 50 0 ns NOTE: (1) Absolute maximum ratings are {imiting values applied individually, thre R/C Low During CE High 50 20 ns beyond which the serviceability of the circuit may be impaired. Functions tsac Byte Select to CE Setup 0 0 ns operation under any of these conditions is not necessarily implied. thac Byte Selected Valid During CE High 50 20 ns tc 86X Conversion Time: 12 Bit Cycle | 9 20 25 ps 8 Bit Cycle 6 | 13 | 17 | ps /QM HIGH RELIABILITY SCREENING te 87X Conversion Time: 12 Bit Cycle 9 12 15 ps . 8 Bit Cycle 6 8 10 ps High Power Intema! Visual Inspection ....c.ss0 tasssesecasesscececceesenesne Burr-Brown Spec. QC2010 READ MODE Nentt tdd Access Time from CE 75 150 ns Stabilization Bake 24Hr at +150C : Temperature CyClng cesses sesencoeeanans 10 Cycles -65C to +150C thd Data Valid after CE Low 25 35 ns : . Constant ACCELOrAation ..cssscscsssssrssserssscssescssessserasserese teseesses 30kG, Y1 axis thi Output Float Delay 100 | 150 ns . =, Hermeticity Fine Leak ..... Helium 5 x 10-*cc/s tssr CS to CE Setup 50 0 ns ~ Hermeticity Gross Leak .. evonseserees PLUOFOCAIDON tsrr R/C to CE Setup 0 0 ns Burn {60Hr at +125C tsar Byte Select to CE Setup 50 | 25 ns urn-in Fatt ther CS Valid after CE Low 0 0 ns ther R/C High after CE Low 0 0 ns thar Byte Select Valid after CE Low | 50 25 ns ths 86X Status Delay after Data Valid | 100 | 500 | 1000] ns 5 ths 87X Status Delay after Data Valid | 100 | 300 | 600 ns CONVERSION CYCLE TIMING READ CYCLE TIMING | CE A. thee | CE tesco cs Gs A FG | | Byte Byte | Select Select | STS STS DBti- DB1i- DBO DBOoom BURR-BROWN CORP MECHANICAL (P.G.A.) ULE D MM 1731365 0019073 0 MIBUB _T-51-07-01 H Package TOP VIEW Bottom VIEW th | Pint | Identifier Q@OOHHOO QQGOOOOOOOO NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. TERMINATION: Gold plated KOVAR. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross feak test. WEIGHT: 9 grms (0.32 oz) NOTE: Leads in true within 0,01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. TERMINATION: Gold plated nickel on refractory metalliza- tion. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 4.37 grms (0.124 02) ODERING INFORMATION Model LCC, PGA input | Package Accuracy (% FSR) Throughput Temperature Range (C) Modei input Accuracy (% FSR) Throughput Temperature _Range (C) SDM862J SDM862K SDM862A SDM&862B SDM862R SDM&862S 16SE LH 16SE LH 16SE 16SE 16SE 16SE LH LH LH LH 0.024 0.012 +0.024 +0.012 0.024 0.012 33kHz 33kHz 33kHz 33kHz 33kHz 38kHz 0 to +70 0to +70 =25 to +85 -25 to +85 55 to +125 ~65 to +125 SDM863J SDM863K SDM863A SDM&63B SDM&63R SDM&63S 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 0.024 0,012 40.024 +0.012 0.024 0.012 0 to +70 Oto +70 25 to +85 ~25 to +85 -55 to +125 55 to +125 SDM872J SDM872K SDM872A SDM872B SDM872R SDM872S 16SE 16SE 16SE 16SE 16SE 16SE LH LH LH LH LH LH 0.024 40.012 0.024 0.012 0.024 +0.012 S0kHz 50kHz 50kHz 50kHz S50kHz 50kHz 0 to +70 0 to +70 25 to +85 -25 to +85 ~5 to +125 -55 to +125 SDM873J SDM873K SDM873A SDM873B SDM873R SDM873S 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF +0.024 0.012 40.024 0.012 0,024 +0.012 50kHz S50kHz 50kHz 0 to +70 Oto +70 ~25 to +85 ~25 to +85 -5 10 +125 -55 to +125 MODEL DESCRIPTION PC862/863-1 LCC (Socketed) Evaluation PCB* PC862/863-2 PGA Evaluation PCB * Switches socket is MCO068. NOTE: 16 single-ended inputs, LCC package, with accuracy of 0.24% FSR. Temp Range of 0C to +70C and throughput of 33kHz = SDM862JL.BURR=BROWN CORP 4QE D MM 1731365 0019074 2 MEBUB PIN CONFIGURATIONS z a 2 + a es 32 8 orano yr WH a SOP TET TET a SEES OSs saqao0oo0oo0o 0 go oo ogtgogoosaatazc (52}[s3][54}{55][s6][57]|[58|[59][eo|[61}{62|[63}[e4] [s5)[esl|e7|{e8] MUX ADD2 [51] MUX INA [4] AMP OUT mux ADD1 [50 [2] AMP REF mux ADDO [49 [3] +15v(1) MUXENABLE [4s}f fs [4] ~15v (1) CHo [47] PIN [5] +5V (2) CHi [ae] GROUPING Gl STATUS cH2 [a5] BY [7] pit CH3 [44] FUNCTION | [3] D10 TOP VIEW cua [43] DOTTED [9] b9 = SDM862/SDM872 LINE fal 08 cHs [42 | SHOWS o cHe [ai SUPPLY fii] D7 cH fol} | SEPARATION 2] 06 S/HIN [B39] [13] D5 no [3a 14] D4 sHouT |p7] z ji5] D3 HOLD CAP [B6| jie] 2 S/HOUT [35 AD 7] D1 {24][e3][22][31][s0)29]l26) 27) [2625] 24][23][22|[21] [20] L19] 16) ti ee te tee : Sz = 7HB"EZ273 & 5 & * 88 = 5 x a aq - 1B a _ > = 5 ! 5 io Bot dd ddd dt oBXake SESESESESESEEEELTEEZZSFZ {52]{53]|54][55]|56|[57|[58}}59}|60||6+ |{62}|63}|64)[65]|66)|67]|68) MUX ADD2 [51] MUX INA MUX ADD1 [50] MUX ADDO MUXENABLE [48}f [ - b~+ CHO+ | PIN CHi+ GROUPING =| CH2+ BY cas FUNCTION | TOP VIEW Chas ! DOTTED SDM863/SDM873 CHS+ | SHOWS CH6+ SUPPLY CH7+ | SEPARATION S/H IN = NC S/H OUT z HOLD CAP [36] S/H OUT [35] AD T-51-07-01 _~ AMP OUT AMP REF +15V (1) ~16V (1) +5V (2) STATUS Dit Dio D9 D8 D7 D6 DS D4 D3 D2 {34][33]|321/31|[30}|29]|28]|27}|26][25}|24]|23]|22)[21|}20]|19|]18] @eEekr Ww wak a re ge x S5BRARSES5S2ZESFN88 sQur gt zoshO2ke es om = Su stares ora < +o o50 CB a a9 fo Slslallsisiisietsieletstclelseie ic] D1 aBURR=BROWN CORP 4LE D MM 17313365 0019075 4 MBUB T-51-07-01 DEFINITION Byte address, short cycle PIN DESIGNATION COMMENTS SDM8X2 = SDM862 OR SDM872 CHO to CH15 Channel Inputs Analog Inputs (Total 16) for single-ended and differential operation. Unused CHO to CH7 (+, -) inputs must be connected to analog common. (PINS 40 to 47, 54 to 61) MUX OUT+/AMP IN+ MULTIPLEXER HI" OUTPUT On the SDM8X2 this {s the multiplexer output. On the SDM8X3 It is the output of the positive selected inputs. it is connected internally to the (PIN 65) positive input of the instrumentation amplifier. MUXOUT (Pin 67) MULTIPLEXER *LO" OUTPUT This pin is used on the SDM8X8 only. It should be connected to the negative input of the instrumentation amplifier. AMP IN (Pin 66) Negative input of instrumentation On the SDM8X2 this should be connected to analog common. On the amplifier SDM8xX3 it should be connected to Muxout{Pin 67). AMP OUT (Pin 1) Output of instrumentation amplifier This pin should be connected to the Input of the S/H amplifier (Pin 39). AMP SENSE (Pin 68) Output sense line of instrumentation This pin will normally be connected direct to AMP OUT (Pin 1). amplifier AMP REF (Pin 2) Reference for amplifier output This pin will normally be connected to analog common. Care should be taken to minimize tracking and contact resistance to analog common to optimize system accuracy. S/H OUT (Pins 35/37) Output of sample/hold amplifier Two pins are provided to facilitate a guard ring around the hold capacitor pin. These pins should be connected to either ADC in (20V) or ADC in (10V) depending on the desired range. HOLD CAP (Pin 36) Connection for hold capacitor on The tracking to the hold capacitor should be as short as possible and a S/H amplifier guard ring employed using Pins 35 and 37, ADG IN (20V); ADC IN (10V) | Inputs to A/D converter Connect to S/H amplifier output. Use appropriate pin for desired range. (Pins 21, 22) RG, G10, G100 Gain settling pins on instrumentation For Gain = 1, no connections. For Gain = 10, connect G10 to AG. (Pins 62, 63, 64) amplifer For Gain = 100, connect Gi00 to RG. REF OUT (PIN 26) 10V Reference voltage This is the reference voltage for the A/D converter. REF IN, BIP OFF Reference input and offset input to Connect trim potentiometers (or sefect-on-test resistors) to these pins for (Pins 24, 23) A/D converter unipolar or bipolar operation as shown in Figures 12, 13. S/H IN (Pin 39) Input to sample/hold amplifier Connect to amp out (Pin 1). MUX ENABLE (Pin 48) Multiplex enable/disable Logic 1 on this pin will enable a selected channel on the intemal multiplexer. Logic 0 de-selects all channels. MUX ADDO to MUX ADDS Address inputs for channel! selection These address lines select a particular channel as specified in Figure 24. (Pins 49 to 52) S/H CONT (Pin 33) Track/Hold control on S/H amplifer Logic 1 holds an analog value for conversion by the A/D converter. This line may be controlled by the status (Pin 6) of the converter to simplify extemal timing control, S/H COM (Pin 34) Reference for S/H logic control Connect to digital common. DO to D11 (Pins 7 to 18) 3-state digital outputs The 12- or 8-bit result of a conversion is available as output on these pins (DO-LSB, D11-MSB). STATUS (Pin 6) Status of A/D conversion This output is at logic.1' while the internal A/D converter is carrying out a ; conversion. This pin may be used to directly control the S/H amplifier. CE (Pin 28) Chip enable This input must be at logic 1 to either Initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). CS (Pin 31) Chip select This input must be at logic 0 to either Initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). RIG (Pin 29) Read/convert Data can be read when this pin is logic 1 or a conversion can be initiated when this pin is logic 0. This pin is typically connected to the R/W control line of a microprocessor-based system (see Figures 10, 17, 18, 19, 20). DATA MODE (Pin 30) Select 12 or 8 Bit Data When data mode Is at logic 1 all 12 output data bits are enabled simuftaneously. When data mode is at logic '0' MSBs and LSBs are controlled by byte select (Pin 32). . BYTE SELECT (Pin 32) When reading output data, byte select at logic '0' enables the 8 MSBs. Byte select at logic 1 enables the 4 LSBs. The 4 LSBs can therefore be connected to four of the MSB lines for inter-connection to an 8-bit bus. In start convert mode, logic '0 enables a 12-bit conversion while logic 1 will short cycle the conversion to 8 bits (see Figure 10). +15V(1), +15V(2)(Pins 3,27) | Power Supply Connect to +15V supply using decoupling as indicated in Figures 15, 16. ~15V(1), -15V(2)(Pins 4,20) | Power Supply Connect to 15V supply using decoupling as indicated in Figures 15, 16. ACOM(2) (Pin 25) Anatog Common Analog common connection. Note that a common (including digital common) should be connected together at one point close to the device. DCOM (1) (Pin 53) Reference for MUX logic control. Connect fo digital common. +5V (Pin 5) Logic power supply Connect to +5V digital supply line with decoupling as in Figures 15, 16. DCOM(2) (Pin 19) Reference for A/D converter control Connect to S/H common at one point close to device. lines NG (Pin38) No internal connectionBURR=BROWN CORP 4ZE D MM 1731365 0019076 & MEBUB .T-51-07-01 SYSTEM DESCRIPTION The SDM comprises four circuit elementsan input-pro- tected multiplexer, an instrumentation amplifier, a sample/ hold amplifier, and an analog-to-digital converter. INSTALLATION MULTIPLEXER The SDM family has a choice of input multiplexers (MUX). SDM862 and SDM872: 16 single-ended inputs SDM863 and SDM873: 8 differential inputs The select inputs are designed for use with TTL and CMOS logic levels and do not require pull-up resistors to ensure break-before-make operation. On all models, the analog inputs may be expanded using the enable control. See Figure 1. When the enable is at a logic 0, the internal MUX is disabled, allowing additional mul- tiplexers to be connected in paralle]. The limiting factor for the number of additional multiplexers is the cumulative effect of leakage current flowing in the signal source imped- ance, causing offset errors. Differential inputs will generally eliminate the noise associ- - ated with common system grounds, but care must be taken to ensure that neither of the differential inputs exceed the maximum input range. Otherwise, signal distortion will result. A return path for the input bias currents must always be provided. This prevents the charging of stray capacitances in applications using floating sources, such as transformers and thermocouples. Multiplexer inputs are protected from overvoltage, as indicated in the electrical specifications, and should be current limited to 20mA. To avoid signal distor- tion on the selected channel, MUX inputs that are not selected should have their input voltages limited to be- tweenV,,, and +V,,-4V, as voltages outside of these values can turn on the non-selected channel. A graph of this characteristic is shown in Figure 2 with a possible circuit solution where it is known that the input voltages will exceed the above values. Where high-speed operation is required and channels require rapid sampling, then it is important to buffer the inputs MUX Extern BB2zS SDM8X3 MUX Intern v, Ouro Viv CH7 Alt MUX [, > ADC Other INA S/H Inputs V ; @ input Current (mA) 6 5 4 3 2 1 15 10 11 12 13 14 15 Input Voltage (V) P Mux Inputs = SDM q : | Ref Out OPAI21K 10V FIGURE 1. External Multiplexer Connections for Differen- tial and Single-Ended Operation. FIGURE 2. MUX Inputs With Limited Input Voltages and Possible Circuit Solution for Non-limited Cases.BURR-BROWN CORP against the effect of current sharing between the MUX output capacitance and the input filter capacitance. See Figure 3. MUX FIGURE 3. Filter and MUX Capacitance. All data acquisition systems using a MUX require consider- ation of the errors that may be introduced by MUX output capacitance. The applications information explains this more fully in the input filtering section, Shown in Figure 4 is an application that demonstrates the flexibility of signal conditioning and gives the opportunity to use a higher bandwidth filter. Diodes shown are low nak UN _ mf i ot Pa il. ht _s~o4 ce R = x oWet$P rr a Ly ee oT KLE D MM 17313b5 0019077 & MEBUB T-51-07-9] leakage types (ina). The low output impedance of the amplifiers reduces the time taken to charge MUX capacitance Cy INSTRUMENT AMPLIFIER The instrument amplifier (INA) presents a very high input impedance to the signal source, eliminating gain errors introduced by voltage divider action between the source output impedance and SDM input impedance. Where the differential models are used, the INA performs the differen- tial to single-ended conversion required to drive the sample/ hold amplifier. Gains may be set by using external jumpers,to values of 1 (no jumper), 10 and 100. For gains other than these presets, the following formula may be used to find an external resistor value to add in series with the G = 10 or G = 100 jumpers. R = 40kQ Ri Where Ri = 4444Q, G = 10 input. G-1 404Q, G = 100 input. It should be noted that the internal gain set resistors have a +20% tolerance and +20ppm/C drift. -ino FET Input +n O_ FET Input z FIGURE 5. Use External Gain Set Resistor. Where it is necessary to keep the input amplifiers from saturating or increasing the overall gain, then the gain of the output amplifier can be increased from unity by using the circuit in Figure 6. o-FET inp 10k2 10K: rie \\-o-=4 4.44k0 | ate | Ry oY WH 20k0 O 4040 \W J Rg oO - 10k A2 AM 10k2 FET input [> Re FIGURE 4. Example Application Hlustrating Flexible Signal Conditioning. FIGURE 6. Increasing Output Amplifier Gain.BURR=BROWN CORP 4LE D MM 1731365 0019078 T MEBUB T-51-07-0] The values of the resistors in Figure 6 are in the following table. Some applications may require programmable gains. This may be realized with Figure 8. O/P GAIN R, & R,Q R,Q 2 1200 2740 5 1000 511 10 1500 340 Matching of R, and R, is required to maintain high common- mode rejection (CMR), R, sets the gain and may be varied without effect on CMR. To ensure that the effects of temperature are minimized when altering the gain with external components, it is very important to. use low tempco resistors. When connecting the output sense, ensure that series resistance is minimized because resistance present will degrade CMR. SETTLING TIME VS GAIN (0.01%, 20V STEP) 10 Settling Time (1s) a J 0 1 10 100 Gain (V/V) . CMR VS FREQUENCY 120 3 100 S 8 80 oO oS 60 a 3 = 5 40 E & 8 20 0 1 10 100 1k 10k 100k 1M Frequency (Hz) FIGURE 7. Typical INA Settling Time and CMR. 10 SDM8X3 MUX INA FIGURE 8. Setting Programmable Gains. SAMPLE/HOLD AMPLIFIER The Sample/Hold amplifier (S/H) is used to track the incom- ing signal and hold the required instantaneous value so that it does not change while the ADC is carrying out its conversion. Timing for the S/H may be derived from the STATUS output of the ADC, with care being taken to comply with the SDM timing considerations. Capacitors with high insulation resistance and low dielectric absorption such as Teflon, polystyrene or polypropylene should be used as storage elements. (Polystyrene should not be used above +80C.) Teflon is recommended for high temperature operation. Care should be taken in the printed circuit layout to minimize stray capacitance and leakage currents from the capacitor to minimize charge offset and droop errors. The use of a guard ring driven by the S/H output around the pin connecting to the hold capacitor is recommended, (Refer to the application board layout for an example of this.) The value of the external hold capacitor determines the droop rate, charge offset and acquisition time of the S/H, Figure 9, Droop rate for the SDM is specified with a hold capacitor value of 4700pf. There is a trade-off between acquisition time and droop rate, as the hold capacitor is increased in value it takes longer to charge, and hence there ACQUISITION TIME VS HOLD CAPACITANCE For a 10V Step to +10mvV of Final Value 10 YF, 9 7 zs 4 Q 7 5 = 6 2 va = / =z. 7 4 2 - ra 3 4 6 8 10 12 14 16 Hold Capacitance (nF) FIGURE 9. Acquisition Time vs Hold Capacitance for a 10V Step Settling to +10mV of Final Value.BURR-BROWN CORP is a corresponding increase in acquisition time and reduction in droop rate. The droop rate is determined by the amount of leakage present in the SDM, board leakage and the dielectric absorption of the hold capacitance, The hold capacitor is also a compensation element for the S/H and should not be reduced below 2nf for good stability. The offset error in sample mode is not affected by the hold capacitor. However, during the transition to hold mode there is approximately 5pC of charge injected into the hold capacitor, causing an offset error that has been nulled for use with a Snf hold capacitor. Any other value for the hold capacitor will cause a minor but fixed hold mode offset to be introduced, and is proportional to the change in value from Snf. Therefore, the SDM should be offset nulled with the S/H in hold mode. ANALOG-TO-DIGITAL CONVERTER This circuit element converts the analog voltage presented by the sample/hold amplifier to a digital number in binary format under control of the digital signals detailed in Figure 10. The converter can convert unipolar and bipolar signals in the range 10V and 20V. It can be calibrated to remove gain and offset errors from the entire system. The converter contains its own clock, voltage reference, and microproces- sor interface with 3-state outputs, The converter will normally be used to digitize signals to 12-bit resolution, but it can be short-cycled to provide 8-bit resolution at higher speed. The digital output is compatible with 8- or 16-bit data buses, the data format being selected by control signals as detailed in Figure 10. _ _ | DATA BYTE CE | CS | AIC | MODE | SELECT OPERATION 0 X xX x x None x 1 x xX x None * 0 0 x 0 Initiate 12-bit conversion 0 0 x 1 Initiate 8-bit conversion 1 . 0 x 0 {nitiate 12-bit conversion 1 v 0 x 1 Initiate 8-bit conversion i 0 . x 0 Initiate 12-bit conversion 1 0 . xX 1 Initiate 8-bit conversion i 0 1 1 xX Enable 12-bit output 1 0 1 0 0 Enable 8 MSBs only i 0 1 0 1 Enable 4 LSBs plus 4 trailing zeros FIGURE 10. Control Input Truth Table. LINEARITY ERROR Linearity error is defined as the deviation of actual code transition values from the ideal transition values, Ideal transition values lie on a line drawn through zero (or minus full scale for bipolar operation) and plus full scale. The zero value is located at an analog input value 1/2LSB before the first code transition (000,, to 001,,). The full-scale value is located at an analog value 3/2LSB beyond the last code transition (FFE,, to FFF,,) (see Figure). Thus, with the SDM connected for bipolar operation and with a full-scale range (or span) of 20V (+10V), the zero value of 10V is 2.44mV below the first code transition (000,, to 001, at 9,99756V) and the plus full-scale value of +10V is 7.32mV above the last code transition (FFE,, to FFF,, at +9.99268) (see Figure 14). 11 GLE D Ml 1732365 0019079 1 MBUB NO MISSING CODES T-51-07-01 (DIFFERENTIAL LINEARITY ERROR) A specification which guarantees no missing codes requires that every code combination appear in a monotonically- increasing sequence as the analog input is increased throughout the range. Thus, every input code width (quan- tum) must have a finite width. If an input quantum has a value of zero (a differential linearity error of -1LSB), a missing code will occur. The SDM is guaranteed to have no missing codes to 12-bit resolution over its respective specification temperature ranges. UNIPOLAR OFFSET ERROR An SDM connected for unipolar operation has an analog input range of OV to plus full scale. The first output code transition should occur at an analog input value 1/2LSB above OV. Unipolar offset error is defined as the deviation of the actual transition value from the ideal value. The unipolar offset temperature coefficient specifies the change of this transition value versus a change in ambient temperature. BIPOLAR OFFSET ERROR A/D converter specifications have historically defined bipo- lar offset as the first transition value above the minus full- scale value. The SDM specification, however, follows the terminology defined for the 574 converter several years ago. Thus, bipolar offset is located near the midscale value of OV (bipolar zero) at the output code transition 7FFH to 800H. Bipolar offset error for the SDM is defined as the deviation of the actual transition value from the ideal transition value located 1/2LSB below OV. The bipolar offset temperature coefficient specifies the maximum change of the code tran- sition value versus a change in ambient temperature. FULL SCALE CALIBRATION ERROR The last output code transition (FFE,, to FFF,,) occurs for an analog input value 3/2LSB below the nominal full-scale value, The full-scale calibration error is the deviation of the actual analog value at the last transition point from the ideal value. The full-scale calibration temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. OPERATING INSTRUCTIONS OPERATING MODES The SDM can operate in one of two modes, namely serial and overlap, as shown in Figure 11. In serial mode, control of the device is such that a multiplexer channel X is first selected, time is then allowed for the instrumentation ampli- fier to settle, the sample/hold amplifier is set to HOLD mode and finally a conversion is carried out. This procedure is then repeated for channel Y. Faster throughput can be obtained using overlap mode. While a conversion is being carried out by the ADC on a voltage from channel X held onBURR-BROWN CORP WE D MM 1732365 0019080 & MBBUB SERIAL MODE T-51-07-01 Signal Acquisition -- |. Conversion > } MUX Instrumentation Sample/ AD Data MUX Selection Amp Hold . . : (x) Settling Acquisition Conversion Valid earl Time OVERLAP MODE MUX Instrumentation Sample/ MUX instrumentation Sample/ MUX Selection Amp Hold Selection Amp Hold Selection (Xx) Settling Acquisition (Y) Settling Acquisition (2) pe. Signal Acquisition Signal Acquisition --__> }e- Conversion ; 1 A/D AD Conversion on Data Valid Conversion on Channel (X) Channel (Y) Time FIGURE 11. Serial and Overlap Modes of Operation. 1 SDM SDM Lo 1 22 23 24 28 g 21 2 23 24 26 | | 1000 | 1002 100Q | 1000S fn (Gain) (Offset) 20V. 10V V 20V. 10V Span Span +15V Span Span inputs Inputs n 100k 100k (Offset) -15V FIGURE 12. Unipolar Calibration. FIGURE 13. Bipolar Calibration.BURR-BROWN CORP 41E D MM 1731365 00190481 T MBUB FULL-SCALE 000 TO 001 FFE TO FFF 1LSB RANGE TRANSITION VOLT. | TRANSITION VOLT. EQUALS 0-10V +0,0012V +9,9963V 2.44mV +5V 4,9988V +4.9963V 2.44mV +10V ~-9,9976V +9.9927V 4.88mV FIGURE 14. Code Transition Ranges. 7 Full-Scale c FFF + Calibration F LL Error Z Fen Rotates of | FFD, + The, { 802 wR Line { my oN B01, - i Oo 800, 1 g i 7FE, \ 002, 001, 000,, Transaction) | \ tb} i 6 ' | verse! Zero vise gatspt | Full Zero = (~Fuull-Scale +Full-Scale Scale (Full Scale) Calibration Calibration Transition) Transition Analog Input FIGURE 15. SDM Transfer Characteristic Terminology. T-51~07-97 Signal-Ret F ' c us I 2 2 \ | 2 : | 9 sg : = 9 = 8 4 2 8 8 8 B 3 6 o 7% F% 6 | 8 =< + YF 66 53 4 3 2 34 25 19 27 20 5 100uH @___-O +5V _f YY O 15V O O +15V LL, LL, 100pH a, -. *10yF tantalum in parallel with 100nF ceramic. FIGURE 16. Recommended Decoupling of Power Supplies. : 13BURR-BROWN CORP OO EE eSOoOo7WOoeE |] 1/2 SDM VO AW MUX-Address T-51-07-01 7} | | | 1731365 goL908e 1 MEBUB i 1/2 SDM \. t ' t i i] ~V +V.00 4+5V 20 1/25 |27 ;19 [5 +5V MUX-Address FIGURE 17. Galvanic Isolation Between Analog and Digital Signals. the sample/hold, channel Y is selected and the multiplexer and instrumentation amplifier allowed to settle. In this way, the total throughput time is limited only by the sum of the sample/hold acquisition time and the ADC conversion time. CALIBRATION UNIPOLAR If adjustment of unipolar offset and gain are not required, then the gain set potentiometer in Figure 12 (Unipolar operation) may be replaced with a 50Q, 1% metal film resistor, and the offset network replaced with a connection from pin 23 to ground. CALIBRATION - BIPOLAR If adjustment of bipolar offset and gain are not required then the gain set and offset potentiometers in Figure 13 (Bipolar operation) may both be replaced with 50Q, 1% metal film resistors. , CALIBRATION - GENERAL The input voltage ranges of the ADC are 0-10V, +5V and +10V. Calibration in all ranges is achieved by adjusting the offset and gain potentiometers (indicated in Figures 12 and 13) such that the 000 to 00! code transition takes place at +1/2LSB from full-scale negative (-FS) and the FFE to FFF transition takes place at 3/2LSB from full-scale positive (+FS). The procedure is therefore to select the required range from Figure 14, apply the specified (-FS+1/2LSB) voltage to any selected input channel and adjust the offset potenti- ometer for the 000 to 001 transition. The (+FS-3/2LSB) voltage should then be applied to the same channel and the gain potentiometer adjusted for the FFE to FFF transition. The offset should always be made before the gain adjustment. 14 GROUNDING, DECOUPLING AND LAYOUT CONSIDERATIONS It should be noted that the multiplexer/instrumentation am- plifier section and sample/hold plus ADC section of the SDM have separate power connections. This is to enable more flexible grounding techniques to be implemented, Figures 16, 17, It also facilitates the use of independent decoupling of the analog front-end power supply, and the ADC plus associated digital circuitry power supply if de- sired. In this way, a separately decoupled analog front-end can be made to be substantially more immune to power supply noise generated by the ADC circuitry than if the power supplies to the two sections were directly connected. This feature is important where low-level signals are in use or high input signal noise immunity is desired. The output section has three grounds: Pin 25 Analog Common, A/D Converter Pin 34 S/H Amp Digital Input Reference Pin 19 Digital Common, A/D Converter The input section has one ground: Pin 53 Common for digital MUX-inputs and power supply decoupling. All grounds have to be interconnected externally to the SDM, and it is recommended that all grounds are connected via one track to a single point as close as possible to the SDM. To check that the grounding structure is correct, the ground tracking should be sketched and a grounding tree should result whereby all grounds route to a central point. In general, layout should be such that analog and digital tracks are separated as much as possible with coupling between analog and digital lines minimized by careful lay-ULE D MM 1731365 0019083 3 MEBUB BURR=BROUWN CORP T-51-07-01 (ua 21) ASt AS* ASI- ASL+ eg anoa tlagsw 46<GNDV 8d (Ao})ur oav as) 40 ve] 92) Se te] Ze 98} SE 89/79 9 co < = vi) (no) 99/S9 29 OeAOTOON OAOrAOTW rrererr Wo joy-Boreuy FIGURE 18. The SDM Connected to an Input/Output Port. 154LE D MM 21731365 0019084 5 mmBUB BURR-BROWN CORP O WU0D H/S ev ey PxXn snes (ug at) ASE+ 9 AS+ 4d S BJAG Pe Fea 85 bLG aSW old 6d 8q Spon suOTY PUBIS dig ed 00 - ev ow Lv ov | XN (Wa Sh) ASE+ ? S 02 2 6LS29 cel ve | epowR peyjoguog Ayn AS* AS= ASI* "S$ og $2neq -aned Of aNov 49 snIeIg jog big as ea pu 8d OHS 4a (aoz) Uy 199 od Ws u #4 A0H) UI 9 Lea PIOH 4+zq T1279 oa od yO ul moO dig 48H Jey 2| be] 9el eelte|ze| _ 96|Sel oc ws JOS 4 suLp HS = FIGURE 19. The SDM Connected to a 16-Bit-BUS. 16BURR=BROWN CORP KLE D Ml 1732365 0019085 ? MEBUB x At AT Ct OS FIGURE 20A. SDM on the Z80 Interface. FIGURE 20B. 68000/SDM Interface. 17BURR-BROWN CORP WLE D MM 1731365 0019084 9 MEBUB Aten Decose on CAH T-51-07-01 FIGURE 20C, IBM PC SDM Interface. 88865 a ll 00 DI D2 D3 Ww TALS 178 FIGURE 21. SDM on the 6502 BUS. 18BURR-BROWN CORP out. For instance, if the lines must cross they should do so at right angles to each other. Parallel analog and digital lines should be separated from each other by a pattern connected to common, CONTROLLING THE SDM The Burr-Brown SDM family can be easily interfaced to most microprocessor systems, as shown in Figures 18-21. The microprocessor may control each conversion, or the converter may operate in a stand-alone mode controlled only by the R/C input. STAND-ALONE OPERATION The stand-alone mode is used in systems containing dedi- cated input ports which do not require full bus interface capability. Control of the converter is accomplished by a single control line connected to R/C. In this mode CS and BYTE SELECT are connected to LOW and CE and DATA MODE are connected to HIGH. The output data are presented as 12-bit words. Conversion is initiated by a High-to-Low transition of RIC. The three-state data output buffers are enabled when R/C is high and STATUS is low. Thus, there are two possible modes of operation; conversion can be initiated with either positive or negative pulses, In each case the R/C pulse must remain low for a minimum of 50ns. Figure 22 illustrates timing when conversion is initiated by an R/C pulse which goes low and retums to the high state during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of R/ and are enabled for external access of the data after completion of the conversion. Figure 23 illustrates the tim- ing when conversion is initiated by a positive R/C pulse. In this mode the output data from the previous conversion is enabled during the positive portion of R/C. A new conver- sion is started on the falling edge of R/C, and the three-state outputs return to the high impedance state until the next occurrence of a high R/C pulse. Table I lists timing specifi- cations for stand-alone operation. SYMBOL PARAMETER MIN | TYP | MAX | UNITS tins Low A/C Pulse Width 50 ns toe STS Delay from R/C 200 | ns ton Data Valid After R/C Low 25 ns t,,86X | STS Delay After Data Valid | 300 { 500 | 1000) ns 1,,87X _ 100 | 300 ; 600 | ns High A/C Pulse Width 150 ns toon Data Access Time 150 | ns TABLE I. Stand-Alone Mode Timing. . ULE D Wl 1731365 0019087 O MBUB T-51-07-01 RE Data Valid High-Z State Data Valid Status DB1ti-DBO FIGURE 22. R/C Pulse LowOutputs Enabled After Con- version. - -N AG \ turn << tos | Status __ t, _> epee Z =| for High-Z Stat OBIT oY ata Valid FIGURE 23. R/C Pulse HighOutputs Enabled Only Where R/C is High. FULLY CONTROLLED OPERATION Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the BYTE SELECT input, which is latched upon receipt of a conversion start transition. BYTE SELECT is latched because it is also involved in enabling the output buffers. No other control inputs are latched. If BYTE SELECT is latched high, the conversion continues for 8 bits. The full 12-bit conversion will occur if BYTE SELECT is low. If all 12 bits are read following an 8-bit conversion, the 3LSBs (DBO- DB2) will be low (logic 0) and DB3 will be high (logic 1). Conversion Start A conversion is initiated by a transition on any of three logic inputs (CE, CS, and R/C)tefer to Figure 10. The last of the three to reach the required state start the conversion and thus all three may be dynamically controlled. If necessary, they may change state simultaneously, and the nominal delay time is independent of which input actually starts the con- version. If it is desired that a particular input establish the actual start of conversion, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing relationships for start of conversion timing are illustrated in Conversion Cycle Timing of the Digital Specifications. Word 1 Word 2 Processor DB7 | DBE | DBS | DB4 DB3 | DB2 DBi | DBO DB7 | DBS | DBS | DB4 | DB3 | DB2 | DBi | DBO SDM DB11 DBiO | DBO | DBS DB7 | DB6 DB5 | DB4 DB3 | OB2 } DB1 | DBO 0 0 0 0 FIGURE 24. 12-Bit Data Format for 8-Bit Systems (connected as Figures 19 and 20). 19BURR=BROWN CORP The STATUS output indicates the state of the converter by being high only during a conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore, data is not valid. During this period additional transitions of the three control inputs will be ignored, so that conversion cannot be prematurely terminated or restarted. However, if BYTE SELECT changes state after the begin- ning of conversion, any additional start conversion transition will latch the new state of BYTE SELECT, possibly result- ing in an incorrect conversion length (8 bit versus 12 bits) for that conversion. READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance state until the following four conditions are met: R/C high, STATUS low, CE high, and CS low. In this condition the data lines are enabled according to the state of the inputs DATA MODE and BYTE SELECT. See Read Cycle Timing for timing relationships and specifica- tion, In most applications the DATA MODE input will be hardwired in either the high or low condition, although it is fully TTL- and CMOS-compatible and may be actively driven if desired. When DATA MODE is high, all 12 outputs lines (DBO-DB11 ) are enabled simultaneously for full data word transfer to a 12-bit or 16-bit bus and the state of the BYTE SELECT is ignored. When DATA MODE is low, the data is presented in the form of two 8-bit bytes, with selection of each byte by the state of BYTE SELECT during the read cycle. The BYTE SELECT input is usually driven by the least significant bit of the address bus, allowing storage of the output data word in two consecutive memory locations. When BYTE SELECT is low, the byte addressed contains the 8MSBs. When BYTE SELECT is high, the byte ad- dressed contains the 4LSBs from the conversion followed by four zeros that have been forced by the control logic. The left-justified formats of the two 8-bit bytes are shown in Figure 24. The design of the SDM guarantees that the BYTE SELECT input may be toggled at any time without damage to the output buffers occuring. In the majority of applications, the read operation will be attempted only after the conversion is complete and the status output has gone low. In those situations requiring the fastest possible access to the data, the read may be started as much as (t,,, max + t,. max) before STATUS goes low. Refer to Read Cycle Timing for these timing relationships. APPLICATIONS INFORMATION ASSEMBLY OF SURFACE MOUNT PACKAGES. There are several assembly methods for the LCC versions of the SDM8XX. The associated advantages and disadvantages of three methods are outlined below. 20 1. DIRECT SURFACE MOUNT ONTO PCB ADVANTAGES DISADVANTAGES Ease of assembly Difficult to inspect solder joints Low cost Difficult to clean Low weight Choice of board material important in Small footprint size wide temperature range applications In wide temperature applications it is important to match the coefficients of thermal expansion of the board and the SDM8XXL. Below is a list of materials and their approxi- mate coefficients of linear thermal expansion. MATERIAL (ppmc) Alumina (96%) - SDM Package 6-7 Copper-clad-Invar (50% Cu) (80% Cu) (10% Cu) Epoxy-Keviar (60% Keviar) Polyimide-Keviar (40% Kevlar) Beryllia Polyimide-glass (x-axis) (y-axis) PRAMAOBOHO Keviar E.I. du Pont de Nemours & Co. _ 2. ATTACHMENT OF SURFACE MOUNT EDGE CLIPS ADVANTAGES DISADVANTAGES _ Ease of Inspection Extra cost Easy cleaning Extra assembly Therma! expansion taken up by the flexing of the edge clips ASSEMBLY The edge clips are attached to the edges of the SDM8XXL as in Figure 25 before the device is mounted on to the board. SDM EDGE CLIP FIGURE 25, Edge Clip Assembly. SUPPLIERS OF EDGE CLIPS USA USA DIE-TECH INC., NAS Electronics, R.D. 1, Sipe Road, 381 Park St., York Haven, Hackensack, PA 17370 USA NJ 07602 USA PHONE: (717) 938-6771 PHONE: (201) 343-3156 EUROPE EUROPE SEMI-DICE (UK) Ltd, NASBRIT Ltd, Buckingham House, Wester Goudi Ind. Est. Mineral Lane, Dundee DD2 4UX Chesham, UK Bucks. HP5 2AU UK PHONE: 0382 622222 PHONE: 0494 771275 pe 897 880 0 9 90 EEE EEEEEEooooooOoOOOOeeeeeeeeeeeeeee T-51~07-0] HE D MM 1731365 0019088 2 mmBuUBBURR=BROWN CORP 3. SURFACE MOUNT SOCKET Below Is the name and address of a supplier of a 68-pin surface mountable socket. T-51-07-01 WIE D MM 2732365 0019089 4 MEBUB by the circuitry and accompanying notes, the designer will 8 differential or 16 single-ended inputs. Input filtering with overvoltage protection for each chan- The part number is: Socket 212-068-012 nel. Spring cover CCS-004 Socket for quad D-type flip-flop 74175 (MUX address USA EUROPE latches). Methode Electronics INC, Lucas Methode Connectors Ltd, PHONE: (312) 392-3500 PHONE: 0535 603282 General Comments The advantages and disadvantages of all the methods men- tioned above are for general use of surface mount compo- nents. Every user will find that the importance of these factors will depend on his application and situation. EVALUATION BOARD For the engineer who wishes to evaluate the SDM family, Burr-Brown has designed printed circuit boards on a single Eurocard (shown here for LCC only). These boards enable the design engineer to experiment with various accuracy improvement techniques which are described below. Special consideration has been given to the grounding and circuit layout techniques required when dealing with 12-bit analog signals. The printed circuit board has been designed so. that the solutions to several of the problems likely to be encountered by the user can be examined. It should not be thought that every user is required to adopt all of the techniques used on the circuit board. In many applications very few external components will be required. However, in following the application guidelines illustrated 7 additional I.C. sockets for easy interfacing to various BUS systems (connection by wire wrap techniques). Interconnect Products Div. Halifax Road 1700 Hick Road, ingrow Bridge, -2 voltage regulators (15V). Roli TX 75050 Keighley, Yorkshire BD21 SHR . USAe Sacows UK sy re LC power supply decoupling. The layout pays particluar attention to the requirements when operating with precision analog signals. This requires strict separation of the analog and digital areas. Analog and digital commons are totally separated and connected to- gether only at the commons of the supply voltage. All common lines are low resistance and low inductance. SUPPLY VOLTAGES In order to avoid coupling between the external supply voltage 15V supplies, 2 voltage regulators (78M15, 79L15) are provided on the PC board. The unregulated supply voltage may vary from +17V to 25V. The MUX/INA section and SHC/ADC section of the SDM have separate supply lines which can be inductively decoupled. This is recommended in order to suppress the high frequency noise which comes from the ADC during conversion. The power supply rejection of the instrumentation amplifier reduces with increasing frequency. If high frequency noise on the supplies is not decoupled it will be injected into the signal path and cause errors. This effect can be particularly pronounced when using the overlap mode since the instru- mentation amplifier is settling to a new analog value while the ADC is still carrying out the previous conversion. I eee ADVANTAGES DISADVANTAGES be able to select and adapt the solutions most suited to their | Board thermal expansion Cost won particular application or problem area. | not so critical Extra height (if critical) Provisions for the following are made on the LCC PC board: | Ease of component . | replacement 68 pin LCC socket (Burr-Brown Part No. MC0068). | | SDM862/872 SDM863/873 Channel MUX MUX MUX MUX MUX Channel MUX MUX MUX MUX Pair ADD3 ADD2 ADD1 ADDO Enable Selected ADD2 ADD1 ADDO Enable Selected x x x x L NONE x x Xx L NONE L L L H 0 L L L H 0 L L L H H i L L H H 1 L L H L H 2 L H L H 2 L L H H H 3 L H H H 3 L H L L H 4 H L L H 4 L H L H H 5 H L H H 5 L H H L H 6 H H L H 6 L H H H H 7 H H H H 7 H L L L H 8 - H L L H A 9 - H L H L H 10 - H L H H H 11 - H H L L H 12 - H H L H H 13 - H H H L H 14 - H H H H H 15 - FIGURE 26. Channel Select Truth Table. 21BURR=-BROUN CORP The digital supply voltage is +5V and is also LC-filtered. All supply lines are bypassed with a 10uF tantalum and a 100nF ceramic capacitor situated as close as possible to the package. If the voltage regulators for the +15V are not used, small inductors for decoupling of the supply voltages are recom- mended. If inductors are not fitted a dynamic ground loop will be created from supply lines via bypass capacitors to analog common. INPUT PROTECTION The multiplexer is protected up to an input voltage which can exceed the supply voltage by a maximum of 20V. This means, that with 15V supply voltage, the input voltage can be +35V without damage. This is also the case when the supply voltages are switched off (OV). The maximum input voltage can then be +20V. For higher overvoltage protection a series resistor has to be used. The current via the multi- plexer should be limited to 20mA absolute maximum, ImA is preferred, For example, a 10kQ series resistor would give an additional 10V overprotection. For much higher overvoltages (e.g. 100V), high value series resistors cannot be used as offset errors would result. In practice, a combination of series resistors and diodes is used. The diodes are connected to 15V and will conduct when- ever the input voltage exceeds the +15V supply voltage. The diodes are selected by signal source impedance, as well as filter resistance, as the diode leakage current across the series resistor can cause offset and linearity errors. In this circuit, IN4148 together with 10kQ are used. INPUT FILTER Processor noise can be induced in the analog ground. Input filtering is therefore recommended for analog data aquisition. Such high frequency noise signals can cause dynamic over- load of the instrumentation amplifier resulting in non-linear behavior. This leads directly to digitizing errors. The design of the filter takes into account the characteristics of the SDM and of the signal source. The following points have to be considered: The stray capacitance, output capacitance of the multi- plexer and input capacitance of the instrument amplifier (up to 80pf in some cases) has to be discharged in order to minimize errors caused by charge sharing. The series resistor limits the current in the protection diodes, but it also has to be selected for the required filter time constant. The noise rejection of the filter has to be >80db in order to satisfy a 12-bit A/D conversion. As well as considering the above, different calculations have to be carried out for single and differential input signals. 22 WLE D Ml 21731365 0019090 0 MEBUB Analog In R, ot e + Ca i re} wenawkenen: IN A Ll FIGURE 27. Single-Ended Measurement R, limits the maximum input current through the protection diodes. In this case, R, has been chosen as 10kQ and together with the capacitor C,, forms the input filter time constant (C, = 0.47pF). The time constant must be chosen according to the requirements of the input signal bandwidth and noise rejection. The multiplexer capacitance (C,,) is discharged mainly by C,. This means C, has to be sufficiently large compared with C_ or charged via R, prior to re-sampling of the signal. ; =e cots Analog n AAA Rog ak a] - ft C, soothed INA Analog In TL R, =% FIGURE 28. Differential Measurement Capacitor C,, is used for limiting the input signal frequency. The bandwidth is calculated as follows: 1 F= Gere FC>>, f When selecting the value of C,, it should be noted that C,, has to be discharged when switching the multiplexer chan- nels. This means that the voltage error of C, (induced by charge sharing with C_) has to be smaller than 1LSB. Therefore, C, should have a minimum value of a 0.47). The resistors R, together with the source impedance, have to be sufficiently small i in order to recharge C, prior to signal sampling. This prevents errors in the signal value caused by the charge stored on C,, by the previously selected channel. The 2 capacitors C, form together with R, a common-mode filter. This filter greatly improves accuracy in a noisy envi- ronment (decrease of common-mode rejection of instrumen- tation amplifier with increasing frequency). For good common-mode filter operation, both time con- stants R, and C, should match each other within 2%. Addi- tional errors will be induced by a mismatch. Selected values are: C, = 0.47HF, C, = 10nF, R, = 10kQ. The filter reduces the signal slew rate $0 that the instrumentation amplifier can follow the voltage variation of the signal with the noise component eliminated. In general, all measurements which require more than a gain of 10 should be done in differential mode. Single ended T-51-07-01BURR-BROWN CORP measurements should be limited to applications where cur- rent sources are measured via shunts or where signal volt- ages in the range of some volts are available. Bus-interface As the outputs of the SDM are BUS compatible, only a few ICs are necessary to interface to various BUS systems, For such interfacing, 20-pin IC sockets are provided. Wiring is by wire wrap to the BUS connector. Setting of Various Modes Circuit Board positions are provided for the connection of jumpers as follows: J1, J2ADC analog input voltage settings. J3Set for differential (SDM8X3) or single ended (SMD8X2) operation. J4Instrumentation amplifier gain settings. (a) 16 input channels, single ended: Use SDM8X2 Consider single-ended filtering Connect J3 (pin 66) to common ULE D MM 17313565 001905 23 1, 2 MEBUB (b) Differential inputs T-51-07-01 Use SDM8X3 cConsider differential filtering Connect J3 (pin 66) to pin 67 (c) Analog input +10V Connect J1 to pin 21 Connect J2 to pot P2 (100Q) Connect J1 to pin 22 Connect J2 to pot P2 (10022) Connect J1 to pin 22 Connect J2 to junction of R/R, (d) Gain of instrumentation amplifier t5V 0 to +10V: G=1 Jumper J4 open G=10 Jumper J4 to pin 63 G = 100 Jumper J4 to pin 64 Other gains: use additional resistor between pin 62 and pin 63 (see section on Instrumentation Amplifier) as low tempco resistor is recommended in order to minimize gain drift.BURR-BROWN CORP YLE D MM 1731365 00135052 4 MEBUB INPUT FILTER AND PROTECTION CIRCUITRY T-51-07-0] SINGLE-ENDED DIFFERENTIAL 26-Pin Connector 26-Pin Connector . Channel "74 14] OR, st5v -15V.s- SDMPins ) Numbers = +IEV -15V SDM Pins pi ~ is| Fe G 47 Channel y5| FS, o Cc 47 0 6S wh +t Numbers Ta t Ci 1%] 10k2 10KQ p I 0.47pF 1 191 AAA D1. D2 46 0 17 0.47pF 10nF 1% RA L ligt x Ait | ; ce 2 23 A D304 _e 45 AAA . a 54 VV 19] A e . 46 R5 q L VV t_ 11 - - 44 4 > 3 Tw = ' i. $ Lelie = " 7 . . 43 q 4 WV 1 at A = 55 R7 i id =I tyWV 7otMAA t =a # 3 . . 42 5 7 Vea LL RS tate | Lelie x 2 ; 4 . . 41 } 6 WA I t- RS x= Ai3 q > 25 AAA 4 = 56 10 . . 40 7 TW > -Wh++ =} -# ' b iediet xo Re rete 17 D15,D16 . 54 8 TW = 3 AM q - Ri4 tet 9 211 AAA - + 55 13} | = 57 R12 i | rm rc 7 A . . 43 r A7 = } 40 25! _ AAA . - 56 q > Rts | ebiet x 4 13 57 q > 11 3A -- RIS Hef | 9 58 Ri4 | 1 +A\\h : a | ot Wah 58 SW} 2} % "| Ris f = Re q > | Lelie -r | 13 51 AAA * -- 58 R16 L ebiet =x rie | ; 5 = 59 1 6 . . 60 WV + 14 + cis 44 AAA * * A ny | let = Re | ti | = 12 61 15 sw I aa H _ 6 R18 d | +r Cci D31D32 fe 6 Ri7 | = 60 10} A . . 40 AIO ti = q > 7 < > 12 |_ 6 18 Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common * Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common 24a a a w m or a or ca o Oo Ly a m a m a e Ld am zr sol Q oo000Cc00o0000 ceo00000000 oo00000000 q ) o000000000 oo000000000 oo000000000 0000000000 yO 62/0)0/4 xy o000000000 oo0o0o0o0o0000] o+- 0010 Lr 92q0--O o000000000 eo0000000090 +O o--020 x. o00000000 0+ ecqo--0 oo00000000 old Oo C 0-069 oc00oc0000000 (3 fs ofa O Oo o 20g oo0000000 N oO 9 tao-o sido +o dido--O #2cd0 eedo---o 6go---O elqao--O ofdo---O rigo--O bao &o0 oO slyOo @ Aad |-698/2980d 6861 PFI UMoig-UNES o-0O 180 o-OS10 OO ced o-091G 6~do ve oO 890-0 9190-0 oluwO-O [o) o 33 | oO 2 ie) 2+ 3 sf OP 00 oo Od oo o-O010 oe) 00 oOo oll | OO 0 Ord oOo O-029 oo oOo O-o00ld oo OlH} OO -OS red O-09 OLLD OFby BURR=BROWN CORP PCB COMPONENT LAYOUT NOTE: (1) NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 (2) NOT DRAWN TO SCALE 25BURR=BROWN CORP 4LE D MM 14731365 0019094 & MBUB P.C.B. LAYOUT T-51-07-01 9606666000048 000500 . $O66666066000060560608 LCC PACKAGE BURR-BROWN LTD SOG F OSSCECESCES aaa otes oe ot 6S SS 2els oe RS SOT SCCCCCRECS eae e $ OO SO8660000 sss SOGG000006 SPSSCOSSSSS ,, GHEHEECERHE eannessoen * secsveces u* soscecseon | GA PACKAGE SEE PC862/863-2 26BURR-BROWN CORP WLE D MM 2732365 0019095 T mEBUB CIRCUIT DIAGRAMSDM PC BOARD 1-51-07-01 3 je By 78 Vv H|s 4 ct 3 8 8 fl H dH oH 8 | tik @ = Wirawrap Posts ACOM nhs As <{-9 0com +4 Aq P3 Ra, 4 1 ott ol8g olig 14 ote oz 11 DI 67 oX%e 32 Hola) -15 720 oy are 5 Bo EAE A Q = 8 5 a 8 LO-@ a & 86 ie H Bis, g = 1g 58-0 O-8 g o = Cs Sis 8 s sio> 8 Sing 3 8 bs rg t othe o DS [8 88 3 = oO cos sS S PEs Zoo / 3 eke 33S 3 5 4 o > 2 j + i z_3] 2 8 g 2 Ho 8/8 is 5 i gepjglle ex -L Bl : Z fz is do = ors < F918 = 6 tot * MYENArSaanonrnar of le - <}-913 T Zs BIS 64646444646 464646666466 as * SBSBRBERSBRSSSTYSTSSES P.C.B. COMPONENTS PARTS LIST Ri 100Q . C26 10nF Ceramic P3 100kQ 0-10V Range Only R2 took [ For 0-10V Settling C27, 029, C35 11.18 400pH (Decoupling) 10yF Tantalum (Decoupling) R3..R18 10kQ 1% C32, C38, C39 D1...032 1N4148 (Input Protection Diodes) C1..C16 0.474FSingle Ended Input Mode C28, C30, C31 . D33,D34 1N4007 40nF 1%Differential Input Mode c36, 037, C40} !O0NF Ceramic (Decoupling) 78 MC7EM15CG Ci7...024 0.474FDifferential Input Mode C33, C34 0.33, F Tantalum 79 MC79L15CG C25 4.700pF (Polypropylene, Polystyrene or P11 1002 74175 74L$175 Tetton) P2 1002 +5V, +10V Range Only LCC Socket MCO0068 UNLESS OTHERWISE MARKEDRESISTORS ARE 1/AW, 5%, CAPACITORS ARE 10% Teflon E.!. du Pont de Nemours & Co. 27