ICS85222-02 1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL HSTL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-toICS Differential HSTL translator and a member of the HiPerClockSTM HiPerClocksTM family of High Performance Clock Solutions from IDT. The ICS85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. * Two differential HSTL outputs * One LVCMOS/LVTTL clock input * CLK input can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 350MHz * Part-to-part skew: 250ps (maximum) * Propagation delay: 1.25ns (maximum) * VOH: 1.4V (maximum) * Output crossover voltage: 0.68V - 0.9V * Full 3.3V operating supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q0 CLK Pulldown Q0 nQ0 Q1 nQ1 nQ0 Q1 1 2 3 4 8 7 6 5 VDD CLK nc GND nQ1 ICS85222-02 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 1 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Description 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GN D Power Power supply ground. 6 nc Unused 7 CLK Input Differential output pair. HSTL interface levels. No connect. Pulldown LVCMOS / LVTTL clock input. Power Positive supply pin. 8 VDD NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 2 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 112.7C/W (0 lfpm) -65C to 150C Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical 2 VIL Input Low Voltage IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CL K VDD = 3.465, VIN = 0V -0.3 Maximum Units VDD + 0.3 V 0.8 V 150 A -5 A TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum 1.0 Typical 1.4 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage 0.68 0.9 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.4 V 1.0 NOTE 1: All outputs must be terminated with 50 to ground. TABLE 4. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical Maximum Units 350 MHz 0.85 1.05 1.25 ns t sk(o) Output Skew; NOTE 2, 3 25 ps t sk(pp) Par t-to-Par t Skew; NOTE 4 250 ps tR / tF Output Rise/Fall Time 250 500 ps odc Output Duty Cycle f 250MHz 45 55 % f > 250MHz 40 60 20% to 80% % All outputs must be terminated with 50 to ground. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 3 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 3.3V 5% PART 1 nQx VDD Qx SCOPE Qx PART 2 nQy HSTL Qy nQx tsk(pp) GND 0V NOTE: All outputs must be terminated with 50 to ground. 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW VDD nQx 2 CLK Qx nQ0, nQ1 nQy Q0, Q1 tPD Qy tsk(o) OUTPUT SKEW PROPAGATION DELAY nQ0, nQ1 80% 80% VSW I N G Q0, Q1 t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR OUTPUT RISE/FALL TIME 4 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: HSTL OUTPUT All outputs must be terminated with 50 to ground. SCHEMATIC EXAMPLE located near the power pin. For ICS85222-02, the unused output need to be terminated. Figure 2 shows a schematic example of ICS85222-02. In the example, the input is driven by a 7 ohm LVCMOS driver with a series termination. The decoupling capacitor should be physically Zo = 50 Ohm VDD=3.3V - U1 Q2 Ro ~ 7 Ohm R6 Zo = 50 Ohm 5 6 7 8 nQ1 Q1 nQ0 Q0 GND nc CLK VDD 4 3 2 1 Zo = 50 Ohm + R1 50 43 Driv er_LVCMOS R2 50 HSTL Input ICS85222-02 VDD=3.3V C1 0.1u Zo = 50 Ohm Zo = 50 Ohm + R3 50 R4 HSTL Input 50 FIGURE 2. ICS85222-02 HSTL BUFFER SCHEMATIC EXAMPLE IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 5 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85222-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 73.8mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.3mW = 164.6mW Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 164.6mW = 337.86mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total device power dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.337W * 103.3C/W = 104.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 6 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 1. VDD Q1 VOUT RL 50 FIGURE 1. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V L /R ) * (V OL_MAX L -V DD_MAX -V DD_MAX ) OH_MAX ) OL_MAX Pd_H = (1.4V/50) * (3.465V - 1.4V) = 57.8mW Pd_L = (0.4V/50) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.3mW IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 7 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85222-02 is: 411 IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 8 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 9 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Package Temperature ICS85222AM-02 85222A02 8 Lead SOIC tube 0C to 70C ICS85222AM-02T 85222A02 8 Lead SOIC 2500 tape & reel 0C to 70C ICS85222AM-02LF 5222A02L 8 Lead "Lead-Free" SOIC tube 0C to 70C ICS85222AM-02LFT 5222A02L 8 Lead "Lead-Free" SOIC 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 10 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR REVISION HISTORY SHEET Rev Table T1 Page 5 6-7 1 2 T2 T3B 2 3 A B Description of Change Added Schematic Example. Power Considerations - corrected power dissipation in calculations. Updated Block Diagram with Pulldown for CLK. Pin Description - changed pin 7 as Pulldown instead of Pullup. Changed note to reflect Pulldown. Pin Characteristics - changed Pullup Resistor to Pulldown. LVCMOS DC Characteristics Table - changed IIH from 5A max. to 150A max. and changed IIL from -150A min. to -5A min. IDT TM / ICSTM DIFFERENTIAL HSTL TRANSLATOR 11 Date 7/24/06 9/12/07 ICS85222AM-02 REV. B SEPTEMBER 12, 2007 ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA