1-TO-2, LVCMOS/LVTTL-TO-
DIFFERENTIAL HSTL TRANSLATOR
ICS85222-02
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 1 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
GENERAL DESCRIPTION
The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-
Differential HSTL translator and a member of the
HiPerClocks™ family of High Performance Clock
Solutions from IDT. The ICS85222-02 has one
single ended clock input. The single-ended clock
input accepts LVCMOS or LVTTL input levels and translates
them to HSTL levels. The small outline 8-pin SOIC package
makes this device ideal for applications where space, high
performance and low power are important.
FEATURES
•Two differential HSTL outputs
•One LVCMOS/LVTTL clock input
•CLK input can accept the following input levels:
LVCMOS or LVTTL
•Maximum output frequency: 350MHz
•Part-to-part skew: 250ps (maximum)
•Propagation delay: 1.25ns (maximum)
•VOH: 1.4V (maximum)
•Output crossover voltage: 0.68V - 0.9V
•Full 3.3V operating supply voltage
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request
•Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85222-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
ICS
VDD
CLK
nc
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
Pulldown
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 2 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 3 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
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IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 4 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
HSTL
Qx
nQx
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
CLK
nQ0, nQ1
Q0, Q1
t
PD
V
DD
2
VDD
0V
3.3V ± 5%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
nQ0, nQ1
Q0, Q1
GND
OUTPUT RISE/FALL TIME
OUTPUT SKEW
t
sk(o)
nQx
Qx
nQy
Qy
NOTE: All outputs must be terminated with 50Ω to ground.
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 5 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
OUTPUTS:
HSTL OUTPUT
All outputs must be terminated with 50Ω to ground.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
APPLICATION INFORMATION
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85222-02. In the
example, the input is driven by a 7 ohm LVCMOS driver with a
series termination. The decoupling capacitor should be physically
Zo = 50 Ohm
R3
50
R4
50
R2
50
VDD=3.3V
C1
0.1u
Zo = 50 Ohm
R6 43
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
HSTL Input
+
-
Ro ~ 7 Ohm
Q2
Driv er_LVCMOS
Zo = 50 Ohm
U1
ICS85222-02
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VDD
CLK
nc
GND
HSTL Input
+
-
VDD=3.3V
FIGURE 2. ICS85222-02 HSTL BUFFER SCHEMATIC EXAMPLE
located near the power pin. For ICS85222-02, the unused output
need to be terminated.
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 6 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85222-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85222-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
•Power (outputs)MAX = 73.8mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 82.3mW = 164.6mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 164.6mW = 337.86mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total device power dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.337W * 103.3°C/W = 104.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN SOIC, FORCED CONVECTION
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 7 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 1.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.8mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 82.3mW
FIGURE 1. HSTL DRIVER CIRCUIT AND TERMINATION
VDD
VOUT
RL
50Ω
Q1
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 8 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85222-02 is: 411
TABLE 6. θ
JAVS. AIR FLOW TABLE 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 9 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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1A01.052.0
B33.015.0
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IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 10 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered
in certain jurisdictions.
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any
other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS.
ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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IDT™ / ICS™ DIFFERENTIAL HSTL TRANSLATOR 11 ICS85222AM-02 REV. B SEPTEMBER 12, 2007
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
ICS85222-02
1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
