74VHC244MTC - FAIRCHILD SEMICONDUCTOR

November 1992

Revised April 2005

74VHC244 Octal Buffer/Line Driver with 3-STATE Outputs

74VHC244

Octal Buffer/Line Driver with 3-STATE Outputs

General Descript ion

The VHC 244 is an advanced hi gh speed CMOS octal bus

buffer fabricated with silicon gate CMOS technology. It

achieves high speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation. The VHC244 is a non-inverting 3-STATE buffer hav-

ing two active-LOW output enables. These devices are

designe d to be used as 3-STATE me mory ad dress drive rs,

clock drivers, and bus oriented transmitter/receivers.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regar d to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supp ly systems such as battery back up. This cir-

cuit preven ts device destruc tion du e to mismatch ed supply

and input voltages.

Features

■High Speed: tPD

3.9ns (typ) at VCC

■High noise immunity: VNIH

VNIL

28% VCC (min)

■Power down protection is provided on all inputs

■Low noise: VOLP

0.6V (typ)

■Low power dissipation: ICC

A (max) @ TA

■Pin and function compatible with 74HC244

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and R eel. Specify by appending th e s uffix let t er “X” to the o rdering c ode.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74VHC244M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC244SJ M20D Pb-Free 20-Lead Small Outlin e Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74VHC244

Pin Descriptions

Truth Tables

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impeda nc e

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0–I7Inputs

O0–O73-STATE Outputs

Inputs Outputs

OE1In(Pins 12, 14, 16, 18)

LL L

LH H

HX Z

Inputs Outputs

OE2In(Pins 3, 5, 7, 9)

LL L

LH H

HX Z

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74VHC244

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 2: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Noise Characteri stics

Note 3: Parameter guaranteed by design.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



0.5V to



7.0V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

20 mA

DC Output Current (IOUT)

25 mA

DC VCC/GND Current (ICC)

75 mA

Storage Temperatur e (TSTG)



C to



150

Lead Temperature (TL)

(Solde ring, 10 seconds) 260

Supply Voltage (VCC) 2.0V to 5.5V

Input Voltage (VIN)0V to



5.5V

Output Voltage (VOUT)0V to V

Operating Temperature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

3.3V

0.3V 0 ns/V

100 ns/V

VCC

5.0V

0.5V 0 ns/V

20 ns/V

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ Max Min Max

VIH HIGH Level 2.0 1.5 1.5 V

Input Voltage 3.0



5.5 0.7 VCC 0.7 VCC

VIL LOW Level 2.0 0.5 0.5 V

Input Voltage 3.0



5.5 0.3 VCC 0.3 VCC

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN

VIH IOH



Output Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH



4 mA

4.5 3.94 3.80 IOH



8 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN

VIH IOL

Output Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL

4 mA

4.5 0.36 0.44 IOL

8 mA

IOZ 3-STATE Output 5.5

0.25

2.5

VIH or VIL

Off-State Current VOUT

VCC or GND

IIN Input Leakage Current 0



5.5

0.1

1.0

5.5V or GND

ICC Quiescent Supply Current 5.5 4.0 40.0

VCC or GND

Symbol Parameter VCC TA

CUnits Conditions

(V) Typ Limits

VOLP Quiet Output Maximum 5.0 0.6 0.9 V CL

50 pF

(Note 3) Dynamic VOL

VOLV Quiet Output Minimum 5.0



0.6



0.9 V CL

50 pF

(Note 3) Dynamic VOL

VIHD Minimum HIGH Level 5.0 3.5 V C L

50 pF

(Note 3) Dynamic Input Voltage

VILD Maximum HIGH Level 5.0 1.5 V CL

50 pF

(Note 3) Dynamic Input Voltage

www.fairchildsemi.com 4

74VHC244

AC Electrical Characteristi cs

Note 4: Parameter guaranteed by design. tOSLH

|tPLHmax



tPLHmin|; tOSHL

|tPHLmax



tPHLmin|.

Note 5: CPD is defined as t he value of t he internal equivalent ca pac itan c e w hich is c alculate d f rom the o perating c urrent consum pt ion without load. Average

operating current can be obtained by the equation: ICC (OPR.)

CPD * VCC * fIN



ICC/8 (per bit).

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ Max Min Max

tPLH Propagation Delay 3.3

0.3 5.8 8.4 1.0 10.0 ns CL

15 pF

tPHL Time 8.3 11.9 1.0 13.5 CL

50 pF

5.0

0.5 3.9 5.5 1.0 6.5 ns CL

15 pF

5.4 7.5 1.0 8.5 CL

50 pF

tPZL 3-STAT E Output 3.3

0.3 6.6 10.6 1.0 12.5 ns RL

1 k

15 pF

tPZH Enable Time 9.1 14.1 1.0 16.0 CL

50 pF

5.0

0.5 4.7 7.3 1.0 8.5 ns CL

15 pF

6.2 9.3 1.0 10.5 CL

50 pF

tPLZ 3-STA T E Output 3.3

0.3 10.3 14.0 1.0 16.0 ns RL

1 k

50 pF

tPHZ Disable Time 5.0

0.5 6.7 9.2 1.0 10.5 CL

50 pF

tOSLH Output to Output 3.3

0.3 1.5 1.5 ns (Note 4) CL

50 pF

tOSHL Skew 5.0

0.5 1.0 1.0 CL

50 pF

CIN Input Capacit ance 4 10 10 pF VCC

Open

COUT Output Capacitance 6 pF VCC

5.0V

CPD Power Dissipation Capacitance 19 pF (Note 5)

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74VHC244

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

www.fairchildsemi.com 6

74VHC244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74VHC244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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74VHC244 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.