8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8432-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8432-101 has a selectable
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts
LVCMOS or LVTTL input levels and translates them to 3.3V
L VPECL levels. The CLK, nCLK pair can accept most standard
differential input levels. The VCO operates at a frequency range
of 200MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input differential or single ended
reference frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. The low phase noise characteristics of the
ICS8432-101 makes it an ideal clock source for Gigabit
Ethernet, Fiber Channel 1 and 2, and Infiniband applications.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
•Dual differential 3.3V L VPECL outputs
•Selectable CLK, nCLK or L VCMOS TEST_CLK
•TEST_CLK can accept the following input levels:
L VCMOS or L VTTL
•CLK, nCLK pair can accept the following differential input
levels: L VPECL, L VHSTL, L VDS, SSTL
•Differential input or TEST_CLK input frequency: 60MHz
•Output frequency range: 25MHz to 700MHz
•VCO range: 200MHz to 700MHz
•Accepts any single-ended input signal to L VCMOS
with resistor bias on nCLK input
•Parallel interface for programming counter and
output dividers
•RMS period jitter: 4ps (maximum)
•Cycle-to-cycle jitter: 25ps (maximum)
•3.3V supply voltage
•0°C to 70°C ambient operating temperature
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
VEE
VEE
nFOUT0
FOUT0
VCCO
nFOUT1
FOUT1
VCC
TEST
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432-101
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
PHASE DETECTOR
÷1
÷2
÷4
÷8
MR
nCLK
HiPerClockS™
,&6
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values
for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A differential clock input is used as the input to the ICS8432-101. This input is fed into the phase detector.
A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of
200MHz to 700MHz. The output of the M divider is also applied to the phase detector .
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO
control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the L VPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-101 support two input modes and programmable M divider and N output divider .
The two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is initially LOW . The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and
N output divider . On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded
until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the
M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 ≤ M ≤ 28. The frequency out is
defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW . The shift register is loaded by sampling the S_DAT A
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DA T A input is passed directly to the M divider and N output divider on each
rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as follows:
fVCO = fIN x M
T1 T0 TEST Output
0 0 LOW
0 1 S_Data
1 0 Output of M divider
1 1 CMOS Fout
FIGURE 1 - PARALLEL & SERIAL LOAD OPERATIONS
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N1
nP_LOAD
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
*NOTE: The NULL timing slot must be observed.
fOUT = fVCO = fIN x M
NN
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
15MtupnIpulluP fonoitsisnartHGIH-ot-WOLnodehctalataD.stupniredividM .slevelecafretniLTTVL/SOMCVL.tupniDAOL_Pn
4,3,2 92,82 23,13,03
,8M,7M,6M ,1M,0M 4M,3M,2M tupnInwodlluP
6,51N,0NtupnInwodlluP ,C3elbaTnidenifedsaeulavredividtuptuosenimreteD .slevelecafretniLTTVL/SOMCVL.elbaTnoitcnuF
7cndesunU.tcennocoN
61,8V
EE
rewoP.snipylppusevitageN
9TSETtuptuO .noitarepofoedomlairesehtniEVITCAsihcihwtuptuotseT .slevelecafretniSOMCVL.edomlellarapniWOLnevirdtuptuO
01V
CC
rewoP.nipylppusevitisoP
21,111TUOFn,1TUOFtuptuO .rezisehtnysehtroftuptuolaitnereffiD .slevelecafretniLCEPVLV3.3
31V
OCC
rewoP.nipylppustuptuO
51,410TUOFn,0TUOFtuptuO .rezisehtnysehtroftuptuolaitnereffiD .slevelecafretniLCEPVLV3.3
71RMtupnInwodlluP dedaoltceffetonseodtub,WOLstuptuosecroF.teserretsaM .slevelecafretniLTTVL/SOMCVL.seulavTdna,N,M
81KCOLC_StupnInwodlluP retsigertfihsehtotnitupniATAD_StatneserpatadlairesniskcolC .KCOLC_Sfoegdegnisirehtno
91ATAD_StupnInwodlluP .tupnilairesretsigertfihS .KCOLC_SfoegdegnisirehtnodelpmasataD
02DAOL_StupnInwodlluP .sredividehtotniretsigertfihsmorfatadfonoitisnartslortnoC .slevelecafretniLTTVL/SOMCVL
12V
ACC
rewoP.nipylppusgolanA
22LES_KLCtupnIpulluP
rotupnikcolclaitnereffidneewtebstceleS.tupnitceleskcolC ,HGIHnehW.ecruosecnereferLLPehtsatupniKLC_TSET .tupniKLC_TSETstceles,WOLnehW.stupniKLCn,KLCstceles .slevelecafretniLTTVL/SOMCVL
32KLC_TSETtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolctseT
42KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
52KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
62DAOL_PntupnInwodlluP si0M:8MtatneserpatadnehwsenimreteD.tupnidaollellaraP ehtstes0N:1Ntatneserpatadnehwdna,redividMotnidedaol .slevelecafretniLTTVL/SOMCVL.eulavredividtuptuoN
72LES_OCVtupnIpulluP .edomssapybroLLPnisirezisehtnysrehtehwsenimreteD .slevelecafretniLTTVL/SOMCVL
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitisiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODES FUNCTION TABLE
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
stupnI snoitidnoC
RMDAOL_PnMNDAOL_SKCOLC_SATAD_S
HX XXX X X .WOLstuptuosecroF.teseR
LL ataDataDX X X ehtotyltceriddessapstupniNdnaMnoataD tuptuoTSET.redividtuptuoNdnaredividM .WOLdecrof
L↑ataDataDL X X dedaolsniamerdnasretsigertupniotnidehctalsiataD .sruccotnevelairesalitnuronoitisnartWOLtxenlitnu
LHXXL ↑ataD noatadhtiwdedaolsiretsigertfihS.edomtupnilaireS .KCOLC_SfoegdegnisirhcaenoATAD_S
LHXX↑LataD ehtotdessaperaretsigertfihsehtfostnetnoC .redividtuptuoNdnaredividM
LHXX↓LataD.dehctaleraseulavredividtuptuoNdnaredividM
LHXXL X X .sretsigertfihstceffatonodtupnilairesrolellaraP
LHXXH ↑ataD.dekcolcsitisaredividMotyltceriddessapATAD_S
WOL=L:ETON HGIH=H eract'noD=X
↑noitisnartegdegnisiR=
↓noitisnartegdegnillaF=
stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO
1N0NmuminiMmumixaM
001002007
012001053
10405571
118525.78
ycneuqerFOCV )zHM( ediviDM 6528214623618421
8M7M6M5M4M3M2M1M0M
002 8 000001000
522 9 000001001
05201 00000 10 10
57211 000001011
• • •••••••••
• • •••••••••
05662 0000 110 10
57672 000011011
00782 000011100
ycneuqerftupniKLC_TSETrotupnilaitnereffidotdnopserrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON .zHM52fo
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VCCx 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, VO-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC
Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability .
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP531.33.3564.3V
V
ACC
egatloVylppuSgolanA531.33.3564.3V
V
OCC
egatloVylppuStuptuO531.33.3564.3V
I
EE
tnerruCylppuSrewoP 021Am
I
ACC
tnerruCylppuSgolanA 02Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
tupnI egatloVhgiH
,RM,LES_KLC,LES_OCV ,ATAD_S,DAOL_S ,DAOL_Pn,KCOLC_S 1N:0N,8M:0M
2V
CC
3.0+V
KLC_TSET2V
CC
3.0+V
V
LI
tupnI egatloVwoL
,RM,LES_KLC,LES_OCV ,ATAD_S,DAOL_S ,DAOL_Pn,KCOLC_S 1N:0N,8M:0M
3.0-8.0V
KLC_TSET3.0-3.1V
I
HI
tupnI tnerruChgiH
,RM,1N,0N,8M-6M,4M-0M ,KLC_TSET,KCOLC_S DAOL_Pn,DAOL_S,ATAD_S V
CC
V=
NI
V564.3=051Aµ
LES_OCV,LES_KLC,5MV
CC
V=
NI
V564.3=5Aµ
I
LI
tupnI tnerruCwoL
,RM,1N,0N,8M-6M,4M-0M ,KLC_TSET,KCOLC_S DAOL_Pn,DAOL_S,ATAD_S
V
CC
,V564.3=
V
NI
V0= 5-Aµ
LES_OCV,LES_KLC,5M V
CC
,V564.3=
V
NI
V0= 051-Aµ
V
HO
tuptuO egatloVhgiH TSET V
CC
,V531.3=
I
HO
Am63-= 6.2V
V
LO
tuptuO egatloVwoL TSET V
CC
,V531.3=
I
LO
Am63= 5.0V
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
6
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
NI
ycneuqerFtupnI 1ETON;KLC_TSET0105zHM
1ETON;KLCn,KLC0105zHM
KCOLC_S 05zHMnihtiwetarepootOCVehtroftesebtsumeulavMeht,egnarycneuqerfKLC_TSETdnatupnilaitnereffidehtroF:1ETON 07eraMfoseulavdilav,zHM01foycneuqerftupnimuminimehtgnisU.egnarzHM007otzHM002eht ≤M≤ehtgnisU.07
4eraMfoseulavdilav,zHM05foycneuqerfmumixam ≤M≤.41
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
0.1-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
CC
V=
NI
V564.3=051Aµ
KLCnV
CC
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCV
CC
V,V564.3=
NI
V0=5-Aµ
KLCnV
CC
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP51.03.1V
V
RMC
egatloVtupnIedoMnommoCV
EE
5.0+V
CC
58.0-V
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON
CC
.V3.0+
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
F
TUO
ycneuqerFtuptuO52007zHM
t
)cc(tij3,1ETON;rettiJelcyC-ot-elcyCzHM053>OCVf52sp
t
)rep(tij1ETON;SMR,rettiJdoirePzHM001>TUOf4sp
t
)o(ks3,2ETON;wekStuptuO 51sp
t
R
emiTesiRtuptuO%08ot%02002007sp
t
F
emiTllaFtuptuO%08ot%02002007sp
t
S
emiTputeS DAOL_PnotN,M5sn
KCOLC_SotATAD_S5sn
DAOL_SotKCOLC_S5sn
t
H
emiTdloH DAOL_PnotN,M5sn
KCOLC_SotATAD_S5sn
DAOL_SotKCOLC_S5sn
cdoelcyCytuDtuptuO1>N8425%
t
WP
htdiWesluPtuptuO1=NPtDOIRE051-2/PtDOIRE051+2/sp
t
KCOL
emiTkcoLLLP 1sm
.noitcesnoitamrofnItnemerusaeMretemaraPeeS .stupniLATXgnisuecnamrofreprettiJ:1ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON .stniopssorclaitnereffidtuptuoehttaderusaeM .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:3ETON
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
7
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL
V
CMR
Cross Points
V
PP
nCLK
CLK
VEE
VCC
3.3V OUTPUT LOAD TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VCC, VCCA, VCCO = 2V
VCC, VCCA, VCCO
VEE = -1.3V ± 0.135V
OUTPUT SKEW
tsk(o)
nFOUTx
nFOUTy
FOUTy
FOUTx
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
8
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
INPUT AND OUTPUT RISE AND FALL TIME
Clock Inputs
and Outputs
20%
80% 80%
20%
t
R
t
F
V
SWING
odc & tPERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
TEST , FOUTx
nFOUTx
Cycle-to-Cycle Jitter
FOUTx
➤
➤
➤
➤
nFOUTx
t
jit(cc) =
t
cycle n –
t
cycle n+1
t
cycle n
t
cycle n+1
Period Jitter
V
OH
V
ref
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10
-7
)% of all measurements
Histogram
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
9
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application
frequencies as well as the ICS8432-101 configurations used to generate the appropriate frequency .
Table 7. Common SANs Applications Frequencies
Table 8. Configuration Details for SANs Applications
APPLICATIONS
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-101 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2 - POWER SUPPLY FILTERING
10Ω
VCCA 10 µF
.01µF
3.3V
.01µF
VCC
ygolonhceTtcennocretnIetaRkcolC SEDRESotycneuqerFecnerefeR )zHM( ycneuqerFlatsyrC )zHM(
tenrehtEtibagiGzHG52.152.651,052,52152135.91,52
lennahCerbiF zHG5260.11CF zHG0521.22CF 5218.231,521.35,52.60152,5265106.61
dnabinifnIzHG5.2052,52152
tcennocretnI ygolonhceT tupnIKLCn,KLC )zHM(
101-2348SCI ycneuqerFtuptuO SEDRESot )zHM(
101-2348SCI sgnitteSN&M
8M7M6M5M4M3M2M1M0M1N0N
tenrehtEtibagiG
52521 00001010010
52052 00001010001
5252.651 00001100110
52135.9152.651 00010000010
1lennahCrebiF 52521.35 00001000111
5252.601 00001000110
2lennahCrebiF5265106.615218.231 00010000010
dnabinifnI 52521 00001010010
52052 00001010001
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
The schematic of the ICS8432-101 layout example used in this layout guideline is shown in
Figure 4A.
The ICS8432-101 recom-
mended PCB board layout for this example is shown in
Figure 4B
. This layout example is used as a general guideline. The layout in
the actual system will depend on the selected component types, the density of the components, the density of the traces, and the
stacking of the P.C. board.
LAYOUT GUIDELINE
FIGURE 4A - SCHEMATIC OF RECOMMENDED LAYOUT
C16
10u
Termination A
U1
8432-101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TEST
VDD
FOUT1/2
nFOUT1/2
VCCO
FOUT
nFOUT
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VDDA
nCLK_SEL
REF_IN
CLK
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
nCLK
R1
125
VCCA
TL2
Zo = 50 Ohm
TEST
IN-
IN-
VCC
S_CLOCK
VCC
R3
125
C11
0.01u
XTAL_SEL
R3
50
S_LOAD
R7
10
TL1
Zo = 50 Ohm
MR
IN+
R4
84
FOUT
R2
84
S_DATA
R1
50
C15
0.1u
nCLK
CLK
VCC
IN+
Termination B
(not shown in
the layout)
FOUTN
R2
50
C14
0.1u
VCC
The clock layout topology shown below is a typical termina-
tion for L VPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 3B - LVPECL OUTPUT TERMINATION
3.3V
FOUT FIN
52Zo
Zo
52
Zo
32Zo
32
Zo = 50Ω
Zo = 50Ω
FIGURE 3A - LVPECL OUTPUT TERMINATION
RTT = 1
(VOH + VOL / VCC –2) –2Zo
Zo = 50Ω
Zo = 50Ω
50Ω
50Ω
RTT
VCC - 2V
FIN
FOUT
➤
designed to drive 50Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion.
Figures 3A and 3B
show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be rec-
ommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
TERMINATION FOR L VPECL OUTPUTS
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
11
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
GND
Close to the input
pins of the
receiver
U1
R3
VCCA
TL1
C14
PIN 1
TL1N
TL1
VCC
R4
C11 C16
C15
TL1, TL2 are 50 Ohm traces and
equal length
R1
TL1N
R7
VIA
R2
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor . Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality . Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
•The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
•Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality .
•T o prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
•Make sure no other signal trace is routed between the
clock trace pair .
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in this
example.
FIGURE 4B - PCB BOARD LAYOUT FOR ICS8432-101
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
12
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-101.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-101 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW
•Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly af fects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per T able 9 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow ,
and the type of board (single layer or multi-layer).
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
13
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
L VPECL output driver circuit and termination are shown in
Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO- 2V .
•For logic high, V OUT = V OH_MAX = VCCO_MAX – 1.0V
(VCCO_MAX - VOH_MAX) = 1.0V
•For logic low , V OUT = V OL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) =
[(2V - 1V)/50W] * 1V = 20.0mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50W] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
FIGURE 5 - LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCCO
RL
50
VCCO - 2V
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
14
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8432-101 is: 3712
TABLE 10. θJAVS. AIR FLOW TABLE
qJA by V elocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
15
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX
NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA
LOBMYS ABB
MUMINIMLANIMONMUMIXAM
N23
A06.1
1A 50.051.0
2A 53.104.154.1
b03.073.054.0
c90.002.0
DCISAB00.9
1D CISAB00.7
2D 06.5
ECISAB00.9
1E CISAB00.7
2E 06.5
eCISAB08.0
L54.006.057.0
q0
°
7
°
ccc 01.0
TABLE 11. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8432DY-101 www.icst.com/products/hiperclocks.html REV. E JUNE 18, 2002
16
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MHZ, LOW PHASE NOISE,
DIFFERENTIAL-TO-3.3V L VPECL FREQUENCY SYNTHESIZER
TABLE 12. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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101-YD2348SCI101-YD2348SCIPFQLdaeL23yartrep052C°07otC°0
T101-YD2348SCI101-YD2348SCIleeRdnaepaTnoPFQLdaeL230001C°07otC°0
