EL8300ISZ-T7 - Intersil Corporation

FN7347.2

EL8300

200MHz Rail-to-Rail Amplifier

The EL8300 represents a triple rail-to-rail amplifier with a -

3dB bandwidth of 200MHz and slew rate of 200V/µs.

Running off a very low supply current of 2mA per channel,

the EL8300 also features inputs that go to 0.15V below the

VS- rail.

The EL8300 includes a fast-acting disable/power-down

circuit. With a 25ns disable and a 200ns enable, the EL8300

is ideal for multiplexing applications.

The EL8300 is designed for a number of general purpose

video, communication, instrumentation, and industrial

applications. The EL8300 is available in an 16-pin SO and

16-pin QSOP packages and is specified for operation over

the -40°C to +85°C temperature range.

Pinout

EL8300

(16-PIN SO, QSOP)

TOP VIEW

Features

• 200MHz -3dB bandwidth

• 200V/µs slew rate

• Low supply current = 2mA per amplifier

• Supplies from 3V to 5.5V

• Rail-to-rail output

• Input to 0.15V below VS-

• Fast 25ns disable

•Low cost

• Pb-Free pus Anneal available (RoHS compliant)

Applications

• Video amplifiers

• Portable/hand-held products

• Communications devices

INA+

CEA

VS-

CEB

INB+

CEC

INC+

INA-

OUTA

VS+

OUTB

INB-

OUTC

INC-

8 9

Ordering Information

PART

NUMBER PACKAGE TAPE & REEL PKG. DWG. #

EL8300IS 16-Pin SO - MDP0027

EL8300IS-T7 16-Pin SO 7” MDP0027

EL8300IS-T13 16-Pin SO 13” MDP0027

EL8300ISZ

(See Note)

16-Pin SO

(Pb-free)

- MDP0027

EL8300ISZ-T7

(See Note)

16-Pin SO

(Pb-free)

7” MDP0027

EL8300ISZ-T13

(See Note)

16-Pin SO

(Pb-free)

13” MDP0027

EL8300IU 16-Pin QSOP - MDP0040

EL8300IU-T7 16-Pin QSOP 7” MDP0040

EL8300IU-T13 16-Pin QSOP 13” MDP0040

EL8300IUZ

(See Note)

16-Pin QSOP

(Pb-free)

- MDP0040

EL8300IUZ-T7

(See Note)

16-Pin QSOP

(Pb-free)

7” MDP0040

EL8300IUZ-T13

(See Note)

16-Pin QSOP

(Pb-free)

13” MDP0040

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both

SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet May 20, 2005

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = 25°C)

Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

VOS Offset Voltage -5 -0.8 +5 mV

TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX 3µV/°C

IB Input Bias Current VIN = 0V -3 -1.4 µA

IOS Input Offset Current VIN = 0V 0.2 0.55 µA

TCIOS Input Bias Current Temperature

Coefficient

Measured from TMIN to TMAX 2nA/°C

CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V 70 90 dB

CMIR Common Mode Input Range VS- - 0.15 VS+ - 1.5 V

RIN Input Resistance Common Mode 16 MΩ

CIN Input Capacitance 0.5 pF

AVOL Open Loop Gain VOUT = +1.5V to +3.5V, RL = 1kΩ to GND 75 90 dB

VOUT = +1.5V to +3.5V, RL = 150Ω to GND 80 dB

OUTPUT CHARACTERISTICS

ROUT Output Resistance AV = +1 30 mΩ

VOP Positive Output Voltage Swing RL = 1kΩ 4.85 4.88 V

RL = 150Ω 4.65 4.68 V

VON Negative Output Voltage Swing RL = 150Ω150 200 mV

RL = 1kΩ50 65 mV

IOUT Linear Output Current 65 mA

ISC (source) Short Circuit Current RL = 10Ω50 75 mA

ISC (sink) Short Circuit Current RL = 10Ω90 130 mA

POWER SUPPLY

PSRR Power Supply Rejection Ratio VS+ = 4.5V to 5.5V 70 100 dB

IS-ON Supply Current - Enabled per Amplifier 2 2.6 mA

IS-OFF Supply Current - Disabled per Amplifier 40 90 µA

ENABLE

tEN Enable Time 200 ns

tDS Disable Time 25 ns

VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V

VIL-ENB ENABLE Pin Voltage for Shut-down 2 V

EL8300

IIH-ENB ENABLE Pin Input Current High 8.6 µA

IIL-ENB ENABLE Pin Input for Current Low 0.01 µA

AC PERFORMANCE

BW -3dB Bandwidth AV = +1, RF = 0Ω, CL = 1.5pF 200 MHz

AV = -1, RF = 1kΩ, CL = 1.5pF 90 MHz

AV = +2, RF = 1kΩ, CL = 1.5pF 90 MHz

AV = +10, RF = 1kΩ, CL = 1.5pF 10 MHz

BW ±0.1dB Bandwidth AV = +1, RF = 0Ω, CL = 1.5pF 20 MHz

Peak Peaking AV = +1, RF = 1kΩ, CL = 5pF 1 dB

GBWP Gain Bandwidth Product 100 MHz

PM Phase Margin RL = 1kΩ, CL = 1.5pF 55 °

SR Slew Rate AV = 2, RL = 100Ω, VOUT = 0.5V to 4.5V 160 200 V/µs

tRRise Time 2.5VSTEP

, 20% - 80% 8 ns

tFFall Time 2.5VSTEP

, 20% - 80% 7 ns

OS Overshoot 200mV step 10 %

tPD Propagation Delay 200mV step 2 ns

tS0.1% Settling Time 200mV step 20 ns

dG Differential Gain AV = +2, RF = 1kΩ, RL = 150Ω0.035 %

dP Differential Phase AV = +2, RF = 1kΩ, RL = 150Ω0.05 °

eNInput Noise Voltage f = 10kHz 10 nV/√Hz

iN+ Positive Input Noise Current f = 10kHz 1 pA/√Hz

iN- Negative Input Noise Current f = 10kHz 0.8 pA/√Hz

eSChannel Separation f = 100kHz 95 dB

Electrical Specifications VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Pin Descriptions

PIN NAME FUNCTION

1, 5, 8 INA+, INB+, INC+ Non-inverting input for each channel

2, 4, 7 CEA, CEB, CEC Enable and disable input for each channel

3 VS- Negative power supply

6, 11 NC Not connected

9, 12, 16 INC-, INB-, INA- Inverting input for each channel

10, 13, 15 OUTC, OUTB, OUTA Amplifier output for each channel

14 VS+ Positive power supply

EL8300

Typical Performance Curves

FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT

VOLTAGE LEVELS

FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS RLOAD

FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS NON-INVERTING GAINS

FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS INVERTING GAINS

FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS CL

FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS CL

-2

-4

-6

100K 1M 10M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

VS=5V

AV=1

RL=1kΩ

CL=1.5pF VOP-P=200mV

VOP-P=1V

VOP-P=2V

-2

-4

-6

100K 1M 10M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

VS=5V

AV=1

CL=1.5pF RL=330Ω

RL=1kΩ

RL=100Ω

-2

-4

-6

100K 1M 10M 100M 1G

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

VS=5V

RL=1kΩ

CL=1.5pF AV=1

AV=10

AV=5

AV=2

-2

-4

-6

100K 1M 10M 100M 1G

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

VS=5V

RL=1kΩ

CL=1.5pF

RF=1kΩ

AV=-10

AV=-2

AV=-5

-1

-3

-5

100K 1M 10M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

VS=5V

AV=1

RL=1kΩ

VOP-P=200mV

CL=10pF

CL=7pF

CL=5pF

CL=1.5pF

-2

-6

100K 1M 10M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

CL=15pF

CL=1.5pF

CL=56pF

CL=35pF

VS=5V

AV=2

RL=1kΩ

RF=RG=1kΩ

-12

-8

-4

EL8300

FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR

VARIOUS RF AND RG

FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY

FIGURE 9. COMMON-MODE REJECTION RATIO vs

FREQUENCY

FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY

VOLTAGE

FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE

Typical Performance Curves (Continued)

100K 1M 10M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

VS=5V

AV=2

RL=1kΩ

CL=1.5pF

RF=RG=2kΩ

RF=RG=500Ω

RF=RG=1kΩ

110

-10

-50

-90

1K 10K 1M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

RL=1kΩ

PHASE (°)

-45

405

315

225

135

100K 10M

RL=150Ω

RL=1kΩ

-10

-30

-50

-70

-90

-110

100K 1M 10M 100M

FREQUENCY (Hz)

CMRR (dB)

230

170

130

210

3 3.5 4.5 5 5.5

VS (V)

BANDWIDTH (MHz)

RL=1kΩ

CL=1.5pF

AV=1

AV=2

190

110

150

100

0.1

0.01

10K 100K 1M 10M

FREQUENCY (Hz)

IMPEDANCE (Ω)

100M

2.5

3 3.5 4.5 5 5.5

VS (V)

PEAKING (dB)

AV=1

RL=1kΩ

CL=1.5pF

1.5

0.5

EL8300

FIGURE 13. POWER SUPPLY REJECTION RATIO vs

FREQUENCY

FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE

FIGURE 15. DISABLED OUTPUT ISOLATION FREQUENCY

RESPONSE

FIGURE 16. HARMONIC DISTORTION vs FREQUENCY

FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY

Typical Performance Curves (Continued)

-10

-30

-50

-70

-90

-110

1K 10K 10M 100M

FREQUENCY (Hz)

PSRR (dB)

100K 1M

PSRR-

PSRR+

-45

-65

-75

-55

-95

VOP-P (V)

DISTORTION (dBc)

VS=5V

RL=1kΩ

CL=1.5pF

AV=2

-85

342

HD2@10MHz

HD3@10MHz

HD3@5MHz

HD2@5MHz

HD2@1MHz

HD3@1MHz

-10

-30

-50

-70

-90

-110

1K 10K 1M 100M 1G

FREQUENCY (Hz)

GAIN (dB)

VS=5V

AV=1

RL=1kΩ

CL=1.5pF

10M100K

-30

-50

-80

-40

-100

140

FREQUENCY (MHz)

DISTORTION (dBc)

VS=5V

RL=1kΩ

VO=1VP-P for AV=1

VO=2VP-P for AV=2

-90

HD2@A

-70

-60

HD2@AV=1

HD3@A

-60

-75

-90

-65

-100

100 2K

RLOAD (Ω)

DISTORTION (dBc)

-95

VS=5V

VO=1VP-P for AV=1

VO=2VP-P for AV=2

-70

-85

-80

HD2@A

HD2@AV=1

HD3@AV=2

HD3@A

100

0.1

10 100 10K 100K 10M

FREQUENCY (Hz)

VOLTAGE NOISE (nV/√Hz)

CURRENT NOISE (pA/√Hz)

1K 1M

IN+

IN-

EL8300

FIGURE 19. CHANNEL SEPARATION vs FREQUENCY FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE

FIGURE 21. OUTPUT SWING FIGURE 22. SMALL SIGNAL TRANSIENT RESPONSE

FIGURE 23. OUTPUT SWING FIGURE 24. DISABLED RESPONSE

Typical Performance Curves (Continued)

-10

-30

-50

-70

-100

100K 1M 10M 100M 1G

FREQUENCY (Hz)

CHANNELL SEPARATION (dB)

-20

-40

-60

-80

-90

CH1<=>CH2

CH2<=>CH3

CH1<=>CH3

VS=5V, AV=1, RL=1kΩ to 2.5V

10ns/DIV

2.5

VS=5V, AV=5, RL=1kΩ to 2.5V

2µs/DIV

2.5

VS=5V, AV=1, RL=1kΩ to 2.5V CL=1.5pF

10ns/DIV

2.4

2.5

2.6

VS=5V, AV=5, RL=1kΩ to 2.5V

2µs/DIV

2.5

VS=±2.5V, AV=1, RL=1kΩ

CH1, CH2, 0.5V/DIV, M=20ns

CH2

CH1

ENABLE

INPUT

OUTPUT

EL8300

FIGURE 25. ENABLED RESPONSE FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

Typical Performance Curves (Continued)

VS=±2.5V, AV=1, RL=1kΩ

CH1, CH2, 1V/DIV, M=100ns

CH2

CH1

ENABLE

INPUT

VOUT

633mW

=158°C/W

QSOP16

1.2

0.8

0.6

0.4

0 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.2

=110°C/W

SO16 (0.150”)

909mW

893mW

=112°C/W

QSOP16

1.4

1.2

0.8

0.6

0.2

0 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.4

1.250W

=80°C/W

SO16 (0.150”)

EL8300

Simplified Schematic Diagram

Description of Operation and Application

Information

Product Description

The EL8300 is wide bandwidth, single supply, low power and

rail-to-rail output voltage feedback operational amplifier. The

amplifiers are internally compensated for closed loop gain of

+1 of greater. Connected in voltage follower mode and

driving a 1kΩ load, the EL8300 has a -3dB bandwidth of

200MHz. Driving a 150Ω load, the bandwidth is about

130MHz while maintaining a 200V/us slew rate. The EL8300

is available with a power down pin for each channel to

reduce power to 30µA typically while the amplifier is

disabled.

Input, Output and Supply Voltage Range

The EL8300 has been designed to operate with a single

supply voltage from 3V to 5.0V. Split supplies can also be

used as long as their total voltage is within 3V to 5.0V. The

amplifiers have an input common mode voltage range from

0.15V below the negative supply (VS- pin) to within 1.5V of

the positive supply (VS+ pin). If the input signal is outside the

above specified range, it will cause the output signal to be

distorted.

The output of the EL8300 can swing rail to rail. As the load

resistance becomes lower, the ability to drive close to each

rail is reduced. For the load resistor 1kΩ, the output swing is

about 4.9V at a 5V supply. For the load resistor 150Ω, the

output swing is about 4.6V.

Choice of Feedback Resistor and Gain Bandwidth

Product

For applications that require a gain of +1, no feedback

resistor is required. Just short the output pin to the inverting

input pin. For gains greater than +1, the feedback resistor

forms a pole with the parasitic capacitance at the inverting

input. As this pole becomes smaller, the amplifier’s phase

margin is reduced. This causes ringing in the time domain

and peaking in the frequency domain. Therefore, RF has

some maximum value that should not be exceeded for

optimum performance. If a large value of RF must be used, a

small capacitor in the few Pico farad range in parallel with RF

can help to reduce the ringing and peaking at the expense of

reducing the bandwidth.

As far as the output stage of the amplifier is concerned, the

output stage is also a gain stage with the load. RF and RG

appear in parallel with RL for gains other than +1. As this

combination gets smaller, the bandwidth falls off.

Consequently, RF also has a minimum value that should not

be exceeded for optimum performance. For gain of +1, RF=0

is optimum. For the gains other than +1, optimum response

is obtained with RF between 300Ω to 1kΩ.

The EL8300 has a gain bandwidth product of 100MHz. For

gains ≥5, its bandwidth can be predicted by the following

equation:

Video Performance

For good video performance, an amplifier is required to

maintain the same output impedance and the same

frequency response as DC levels are changed at the output.

This is especially difficult when driving a standard video load

of 150Ω, because the change in output current with DC level.

Special circuitry has been incorporated in the EL8300 to

reduce the variation of the output impedance with the current

output. This results in dG and dP specifications of 0.03%

and 0.05°, while driving 150Ω at a gain of 2. Driving high

impedance loads would give a similar or better dG and dP

performance.

IN+ IN-

I1I2R6

R1R2

Q1Q2

VBIAS1

Q5Q6

Q3Q4

R4R5

VS-

OUT

VBIAS2

VS+

DIFFERENTIAL TO

DRIVE

GENERATOR

SINGLE ENDED

Gain BW×100MHz=

EL8300

Driving Capacitive Loads and Cables

The EL8100, EL8101 can drive 10pF loads in parallel with

1kΩ with less than 5dB of peaking at gain of +1. If less

peaking is desired in applications, a small series resistor

(usually between 5Ω to 50Ω) can be placed in series with the

output to eliminate most peaking. However, this will reduce

the gain slightly. If the gain setting is greater than 1, the gain

resistor RG can then be chosen to make up for any gain loss

which may be created by the additional series resistor at the

output.

When used as a cable driver, double termination is always

recommended for reflection-free performance. For those

applications, a back-termination series resistor at the

amplifier’s output will isolate the amplifier from the cable and

allow extensive capacitive drive. However, other applications

may have high capacitive loads without a back-termination

resistor. Again, a small series resistor at the output can help

to reduce peaking.

Disable/Power-Down

The EL8300 can be disabled and placed its output in a high

impedance state. The turn off time for each channel is about

25ns and the turn on time is about 200ns. When disabled,

the amplifier’s supply current is reduced to 30µA typically,

thereby effectively eliminating the power consumption. The

amplifier’s power down can be controlled by standard TTL or

CMOS signal levels at the ENABLE pin. The applied logic

signal is relative to VS- pin. Letting the ENABLE pin float or

applying a signal that is less than 0.8V above VS- will enable

the amplifier. The amplifier will be disabled when the signal

at ENABLE pin is 2V above VS-.

Output Drive Capability

The EL8300 does not have internal short circuit protection

circuitry. They have a typical short circuit current of 70mA

sourcing and 140mA sinking for the output is connected to

half way between the rails with a 10Ω resistor. If the output is

shorted indefinitely, the power dissipation could easily

increase such that the part will be destroyed. Maximum

reliability is maintained if the output current never exceeds

±40mA. This limit is set by the design of the internal metal

interconnections.

Power Dissipation

With the high output drive capability of the EL8300, it is

possible to exceed the 125°C absolute maximum junction

temperature under certain load current conditions.

Therefore, it is important to calculate the maximum junction

temperature for the application to determine if the load

conditions or package types need to be modified for the

amplifier to remain in the safe operating area.

The maximum power dissipation allowed in a package is

determined according to:

Where:

TJMAX = Maximum junction temperature

TAMAX = Maximum ambient temperature

θJA = Thermal resistance of the package

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

For sourcing:

For sinking:

Where:

VS = Total supply voltage

ISMAX = Maximum quiescent supply current

VOUTi = Maximum output voltage of the application for

each channel

RLOADi = Load resistance tied to ground for each channel

ILOADi = Load current for each channel

By setting the two PDMAX equations equal to each other, we

can solve the output current and RLOADi to avoid the device

overheat.

Power Supply Bypassing and Printed Circuit

Board Layout

As with any high frequency device, a good printed circuit

board layout is necessary for optimum performance. Lead

lengths should be as sort as possible. The power supply pin

must be well bypassed to reduce the risk of oscillation. For

normal single supply operation, where the VS- pin is

connected to the ground plane, a single 4.7µF tantalum

capacitor in parallel with a 0.1µF ceramic capacitor from VS+

to GND will suffice. This same capacitor combination should

be placed at each supply pin to ground if split supplies are to

be used. In this case, the VS- pin becomes the negative

supply rail.

For good AC performance, parasitic capacitance should be

kept to a minimum. Use of wire wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier’s inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

PDMAX TJMAX TAMAX

–

θJA

---------------------------------------------=

PDMAX VSISMAX VSVOUTi

–()

VOUTi

RLi

-----------------

i1=

∑

+×=

PDMAX VSISMAX VOUTi VS-–()ILOADi

i1=

∑

+×=

EL8300

Typical Applications

VIDEO SYNC PULSE REMOVER

Many CMOS analog to digital converters have a parasitic

latch up problem when subjected to negative input voltage

levels. Since the sync tip contains no useful video

information and it is a negative going pulse, we can chop it

off. Figure 28 shows a gain of 2 connections for EL8300.

Figure 29 shows the complete input video signal applied at

the input, as well as the output signal with the negative going

sync pulse removed.

MULTIPLEXER

Besides the normal power down usage, the ENABLE pin of

the EL8300 can be used for multiplexing applications.

Figure 30 shows two channels with the outputs tied together,

driving a back terminated 75Ω video load. A 2VP-P 2MHz

sine wave is applied to Amp A and a 1VP-P 2MHz sine wave

is applied to Amp B. Figure 31 shows the ENABLE signal

and the resulting output waveform at VOUT

. Observe the

break-before-make operation of the multiplexing. Amp A is

on and VIN1 is passed through to the output when the

ENABLE signal is low and turns off in about 25ns when the

ENABLE signal is high. About 200ns later, Amp B turns on

and VIN2 is passed through to the output. The break-before-

make operation ensures that more than one amplifier isn’t

trying to drive the bus at the same time.

SINGLE SUPPLY VIDEO LINE DRIVER

The EL8300 is wideband rail-to-rail output op amplifiers with

large output current, excellent dG, dP, and low distortion that

allow them to drive video signals in low supply applications.

Figure 32 is the single supply non-inverting video line driver

configuration and Figure 33 is the inverting video ling driver

configuration. The signal is AC coupled by C1. R1 and R2

are used to level shift the input and output to provide the

largest output swing. RF and RG set the AC gain. C2 isolates

the virtual ground potential. RT and R3 are the termination

resistors for the line. C1, C2 and C3 are selected big enough

to minimize the droop of the luminance signal.

FIGURE 28. SYNC PULSE REMOVER

VOUT

VIN 75Ω

75Ω

VS+

VS-

FIGURE 29. VIDEO SIGNAL

0.5V

M = 10µs/DIV

VOUT

VIN

FIGURE 30. TWO TO ONE MULTIPLEXER

+2.5V

2MHz

75Ω

-2.5V

VOUT

75Ω

1VP-P

+2.5V

2MHz +

75Ω

-2.5V

2VP-P

ENABLE

FIGURE 31. ENABLE SIGNAL

-0.5V

-1.5V

-2.5V

M = 50ns/DIV

ENABLE

B-1V

EL8300

FIGURE 32. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE

DRIVER

VOUT

VIN 75Ω

75Ω

1kΩ

75Ω

470µF

47µF

10K

1kΩ

220µF

FIGURE 33. 5V SINGLE SUPPLY INVERTING VIDEO LINE

DRIVER

VOUT

VIN 75Ω

75Ω

500Ω

75Ω

470µF

47µF

10K

1kΩ

220µF

FIGURE 34. VIDEO LINE DRIVER FREQUENCY RESPONSE

-1

-2

-3

-4

-5

NORMALIZED GAIN (dB)

100K 1M 10M 100M 200M

FREQUENCY (Hz)

AV = -2

AV = 2

EL8300

SO Package Outline Drawing

EL8300

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

QSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

http://www.intersil.com/design/packages/index.asp

EL8300