\"74LVC1G38GW,125\" - NXP SEMICONDUCTORS

1. General description

The 74LVC1G38 provides a 2-input NAND function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device as translator in a mixed 3.3 Vand 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF

circuitry disables the outpu t, preventing the damaging ba ckflow current through the device

when it is powered down.

2. Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant outputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7(1.65 Vto1.95V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V).

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

24 mA output drive (VCC =3.0V)

CMOS low power consumption

Open drain outputs

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from 40 C to +125 C.

74LVC1G38

2-input NAND gate; open drain

Rev. 7 — 4 October 2012 Product data sheet

Product data sheet Rev. 7 — 4 October 2012 2 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

3. Ordering information

4. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

Tabl e 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC1G38GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;

body width 1.25 mm SOT353-1

74LVC1G38GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753

74LVC1G38GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;

6 terminals; body 1  1.45  0.5 mm SOT886

74LVC1G38GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;

6 terminals; body 1 10.5 mm SOT891

74LVC1G38GN 40 C to +125 C XSON6 extremely thin small outlin e package; no l eads;

6 terminals; body 0.9 1.0 0.35 mm SOT1115

74LVC1G38GS 40 C to +125 C XSON6 extremely thin small outlin e package; no l eads;

6 terminals; body 1.0 1.0 0.35 mm SOT1202

74LVC1G38GX 40 C to +125 C X2SON5 X2SON5: plasti c thermal enhanced extremely thin

small outline package; no leads; 5 terminals;

body 0.8 0.8 0.35 mm

SOT1226

Table 2. Marking

Type number Marking code[1]

74LVC1G38GW YB

74LVC1G38GV YB

74LVC1G38GM YB

74LVC1G38GF YB

74LVC1G38GN YB

74LVC1G38GS YB

74LVC1G38GX YB

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

001aab717

001aab716

001aab715

GND

Product data sheet Rev. 7 — 4 October 2012 3 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 4. Pin configu ration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886

74LVC1G38

GND Y

001aab718

74LVC1G38

001aab832

GND

n.c.

VCC

Transparent top view

Fig 6. Pin configu ration SOT891, SOT1115 and

SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5)

74LVC1G38

001aaf180

GND

n.c.

VCC

Transparent top view

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Table 3. Pin description

Symbol Pin Description

TSSOP5 and X2SON5 XSON6

A 1 1 data input

B 2 2 data input

GND 3 3 ground (0 V)

Y 4 4 data output

n.c. - 5 not connected

VCC 5 6 supply voltage

Product data sheet Rev. 7 — 4 October 2012 4 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.

For XSON6 and X2SON 5packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

Table 4. Function table[1]

Input Output

ABY

LLZ

LHZ

HLZ

HHL

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +6.5 V

IIK input clampi n g cu rre nt VI<0V 50 - mA

VIinput voltage [1] 0.5 +6.5 V

IOK output clamping current VO>V

CC or VO<0V - 50 mA

VOoutput voltage Active mode [1][2] 0.5 +6.5 V

Power-down mode [1][2] 0.5 +6.5 V

IOoutput current VO=0VtoV

CC -50 mA

ICC supply current - 100 mA

IGND ground current 100 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb =40 C to +125 C[3] - 300 mW

Product data sheet Rev. 7 — 4 October 2012 5 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

9. Recommended operating conditions

10. Static characteristics

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 1.65 - 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage Active mode 0 - 5.5 V

Disable mode; VCC =1.65Vto5.5V 0 - 5.5 V

Power-down mode; VCC = 0 V 0 - 5.5 V

Tamb ambient temperature 40 - +125 C

t/V input transition rise and

fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V

VCC = 2.7 V to 5.5 V - - 10 ns/V

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb =40 C to +85 C[1]

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7  VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3  VCC V

VOL LOW-level output voltage VI=V

IH or VIL ---

IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V

IO=4mA; V

CC = 1.65 V - - 0.45 V

IO=8mA; V

CC = 2.3 V - - 0.3 V

IO=12mA; V

CC = 2.7 V - - 0.4 V

IO=24mA; V

CC = 3.0 V - - 0.55 V

IO=32mA; V

CC = 4.5 V - - 0.55 V

IIinput leakage current VI= 5.5 V or GND;

VCC =0Vto5.5V -0.1 5A

IOZ OFF-state output current VI=V

IH or VIL; VO=V

CC or GND;

VCC = 5.5 V -0.1 10 A

IOFF power-off leakage current VIor VO=5.5V; V

CC = 0 V - 0.1 10 A

ICC supply current VI= 5.5 V or GND;

VCC =1.65Vto5.5V; I

O=0A -0.110A

ICC additional supply current VI=V

CC 0.6 V; IO=0A;

VCC = 2.3 V to 5.5 V; per pin -5500A

CIinput capacitance - 2.5 - pF

Product data sheet Rev. 7 — 4 October 2012 6 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C.

Tamb =40 C to +125 C

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7  VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3  VCC V

VOL LOW-level output voltage VI=V

IH or VIL ---

IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V

IO=4mA; V

CC = 1.65 V - - 0.70 V

IO=8mA; V

CC = 2.3 V - - 0.45 V

IO=12mA; V

CC = 2.7 V - - 0.60 V

IO=24mA; V

CC = 3.0 V - - 0.80 V

IO=32mA; V

CC = 4.5 V - - 0.80 V

IIinput leakage current VI= 5.5 V or GND;

VCC =0Vto5.5V --100 A

IOZ OFF-state output current VI=V

IH or VIL; VO=V

CC or GND;

VCC = 5.5 V --200 A

IOFF power-off leakage current VIor VO=5.5V; V

CC = 0 V - - 200 A

ICC supply current VI= 5.5 V or GND;

VCC =1.65Vto5.5V; I

O=0A --200A

ICC additional supply current VI=V

CC 0.6 V; IO=0A;

VCC = 2.3 V to 5.5 V; per pin --5000A

Table 7. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 7 — 4 October 2012 7 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

11. Dynamic characteristics

[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2 .7 V, 3.3 V and 5.0 V respectively.

[2] tpd is the same as tPZL and tPLZ.

[3] CPD is used to determine the dynamic power dissipation (PDin W).

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

12. AC waveforms

Table 8. Dynamic characteristics

Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

tpd propagation delay A, B to Y; see Figure 8 [2]

VCC = 1.65 V to 1.95 V 1.0 3.0 10.0 1.0 12.5 ns

VCC = 2.3 V to 2.7 V 0.5 1.8 6.0 0.5 7.5 ns

VCC = 2.7 V 0.5 2.5 5.0 0.5 6.5 ns

VCC = 3.0 V to 3.6 V 0.5 2.3 4.5 0.5 5.7 ns

VCC = 4.5 V to 5.5 V 0.5 1.5 3.9 0.5 4.9 ns

CPD power dissipation

capacitance VCC =3.3V;

VI=GNDtoV

[3] -6- - -pF

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. The input (A, B) to output (Y) propagation delays.

001aab719

tPZL

tPLZ

GND

VCC

VOL

Y output

A, B input

Product data sheet Rev. 7 — 4 October 2012 8 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Table 9. Measurement points

Supply voltage Input Output

VCC VMVMVX

1.65 V to 1.95 V 0.5 VCC 0.5 VCC VOL +0.15V

2.3 V to 2.7 V 0.5 VCC 0.5 VCC VOL +0.15V

2.7V 1.5V 1.5V V

OL +0.3V

3.0 V to 3.6 V 1.5 V 1.5 V VOL +0.3V

4.5 V to 5.5 V 0.5 VCC 0.5 VCC VOL +0.3V

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 9. Test circuit for measuring switching times

VEXT

VCC

VIVO

mna616

DUT

Table 10. Test data

Supply voltage Input Load VEXT

VCC VItr, tfCLRLtPLH, tPHL

1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 kopen

2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open

2.7 V 2.7 V 2.5 ns 50 pF 500 open

3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open

4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open

Product data sheet Rev. 7 — 4 October 2012 9 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

13. Package outline

Fig 10. Package outline SOT353-1 (TSSOP5)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.1

01.0

0.8 0.30

0.15 0.25

0.08 2.25

1.85 1.35

1.15 0.65

1.3 2.25

2.0 0.60

0.15 7°

0°

0.1 0.10.30.425

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.46

0.21

SOT353-1 MO-203 SC-88A 00-09-01

03-02-19

0.15

(A3)

detail X

vMA

1.5 3 mm0

scale

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1

1.1

Product data sheet Rev. 7 — 4 October 2012 10 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 11. Package outline SOT753 (SC-74A)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT753 SC-74A

wBM

detail X

vMA

0 1 2 mm

scale

132

Plastic surface-mounted package; 5 leads SOT753

UNIT A1bpcDEHELpQywv

mm 0.100

0.013 0.40

0.25 3.1

2.7

0.26

0.10 1.7

1.3

0.95 3.0

2.5 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2 0.33

0.23

1.1

0.9

02-04-16

06-03-16

Product data sheet Rev. 7 — 4 October 2012 11 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 12. Package outline SOT886 (XSON6)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT886 MO-252

sot886_po

04-07-22

12-01-05

Unit

max

nom

min

0.5 0.04 1.50

1.45

1.40

1.05

1.00

0.95

0.35

0.30

0.27

0.40

0.35

0.32

0.6

A(1)

Dimensions (mm are the original dimensions)

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886

A1b

0.25

0.20

0.17

DEee

0.5

terminal 1

index area

0 1 2 mm

scale

(2)

Product data sheet Rev. 7 — 4 October 2012 12 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 13. Package outline SOT891 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT891

05-04-06

07-05-15

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

mm 0.20

0.12 1.05

0.95 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.350.55

max

0.5 0.04

6×

(1)

4×

(1)

Note

1. Can be visible in some manufacturing processes.

Product data sheet Rev. 7 — 4 October 2012 13 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 14. Package outline SOT1115 (XSON6)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1115

sot1115_po

10-04-02

10-04-07

Unit

mm max

nom

min

0.35 0.04 0.95

0.90

0.85

1.05

1.00

0.95 0.55 0.3 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads;

6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

e1e1

321

6 5 4

(6×)(2) A1A

Product data sheet Rev. 7 — 4 October 2012 14 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 15. Package outline SOT1202 (XSON6)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1202

sot1202_po

10-04-02

10-04-06

Unit

mm max

nom

min

0.35 0.04 1.05

1.00

0.95

1.05

1.00

0.95 0.55 0.35 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON6: extremely thin small outline package; no leads;

6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

e1e1

123

6 5 4

(6×)(2)

Product data sheet Rev. 7 — 4 October 2012 15 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Fig 16. Package outline SOT1226 (X2SON5)

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Product data sheet Rev. 7 — 4 October 2012 16 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

14. Abbreviations

15. Revision history

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Trans istor Logic

Table 12. Revision history

Document ID Release date Data sheet sta t us Change notice Supersedes

74LVC1 G38 v.7 20121004 Product data sheet - 74 LVC1G38 v.6

Modifications: •Pin configuration SOT1226 (Figure 7) modified.

74LVC1 G38 v.6 20120702 Product data sheet - 74 LVC1G38 v.5

Modifications: •Added type number 74LVC1G38GX (SOT12 26)

•Package outli n e drawing of SOT886 (Figure 12) modified.

74LVC1 G38 v.5 20111206 Product data sheet - 74LVC1G38 v.4

Modifications: •Legal pages updated.

74LVC1 G38 v.4 20101005 Product data sheet - 74 LVC1G38 v.3

74LVC1 G38 v.3 20070827 Product data sheet - 74 LVC1G38 v.2

74LVC1 G38 v.2 20060913 Product data sheet - 74 LVC1G38 v.1

74LVC1 G38 v.1 20041018 Product data sheet - -

Product data sheet Rev. 7 — 4 October 2012 17 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors doe s not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cu stomer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 7 — 4 October 2012 18 of 19

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74LVC1G38

2-input NAND gate; open drain

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 October 2012

Document identifier: 74LVC1G38

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 5

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

12 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17 Contact information. . . . . . . . . . . . . . . . . . . . . 18

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19