AGLE600V2-FFG484C - Microsemi Corp.

October 2008 I

IGLOOe Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-

Power Flash*Freeze Mode

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•FlashLock

® to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

•1.2

V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO®e Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

ARM Processor Support in IGLOOe FPGAs

• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available

with or without Debug

IGLOOe Product Family

IGLOOe Devices AGLE600 AGLE3000

ARM-Enabled IGLOOe Devices M1AGLE3000

System Gates 600 k 3 M

VersaTiles (D-flip-flops) 13,824 75,264

Quiescent Current (typical) in Flash*Freeze Mode (µW) 49 137

RAM kbits (1,024 bits) 108 504

4,608-Bit Blocks 24 112

FlashROM Bits 1 k 1 k

Secure (AES) ISP Yes Yes

CCCs with Integrated PLLs 66

VersaNet Globals118 18

I/O Banks 88

Maximum User I/Os 270 620

Package Pins

FBGA FG256, FG484 FG484, FG896

Notes:

1. Refer to the Cortex-M1 Handbook for more information.

2. Six chip (main) and twelve quadrant global networks are available.

3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook.

v1.2

II v1.2

I/Os Per Package1

IGLOOe Devices AGLE600 AGLE3000

ARM-Enabled IGLOOe Devices M1AGLE3000

Package

I/O Types

Single-Ended

I/O1Differential

I/O Pairs

Single-Ended

I/O1Differential

I/O Pairs

FG256 165 79 – –

FG484 270 135 341 168

FG896 – – 620 310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe Low-Power Flash

FPGAs with Flash*Freeze Technology handbook to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

4. FG256 and FG484 are footprint-compatible packages.

5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per

minibank (group of I/Os). When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular

I/O, the number of single-ended user I/Os available is reduced by one.

6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-

ended user I/Os available is reduced by one.

7. "G" indicates RoHS-compliant packages. Refer to "IGLOOe Ordering Information" on page III for the location of the

"G" in the part number.

IGLOOe FPGAs Package Sizes Dimensions

Package FG256 FG484 FG896

Length × Width (mm × mm) 17 × 17 23 × 23 31 × 31

Nominal Area (mm2)289 529 961

Pitch (mm) 111

Height (mm) 1.6 2.23 2.23

IGLOOe Low-Power Flash FPGAs

v1.2 III

IGLOOe Ordering Information

Notes:

1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.

2. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics

provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be

added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

AGLE3000 FG

Part Number

Speed Grade

Blank = Standard

F = 20% Slower than Standard*

Package Type

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

896 I

Package Lead Count

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I=Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

600,000 System Gates

AGLE600 =

3,000,000 System Gates

AGLE3000 =

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant Packaging

IGLOOe Devices

3,000,000 System Gates

Supply Voltage

2 = 1.2 V to 1.5 V

5 = 1.5 V only

IGLOOe Devices with Cortex-M1

M1AGLE3000 =

IV v1.2

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with

M1 (Cortex-M1).

Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.

Package

AGLE600 AGLE3000

M1AGLPE3000

FG256 C, I –

FG484 C, I C, I

FG896 –C, I

Note: C = Commercial temperature range: 0°C to 70°C ambient temperature.

I = Industrial temperature range: –40°C to 85°C ambient temperature.

Temperature Grade –F 1Std.

C 2✓✓

I 3–✓

Notes:

1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

2. C = Commercial temperature range: 0°C to 70°C ambient temperature.

3. I = Industrial temperature range: –40°C to 85°C ambient temperature.

v1.2 1-1

1 – IGLOOe Device Family Overview

General Description

The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA,

a single-chip solution, small footprint packages, reprogrammability, and an abundance of

advanced features.

The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low-

power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power

management through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the

IGLOOe device is completely functional in the system. This allows the IGLOOe device to control

system power management based on external inputs (e.g., scanning for keyboard stimulus) while

consuming minimal power.

Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOOe is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have

up to 3 million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620

user I/Os.

M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOOe device. The processor runs the ARMv6-M

instruction set, has a configurable nested interrupt controller, and can be implemented with or

without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOOe FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGLE and do not

support AES decryption.

Flash*Freeze Technology

The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOOe devices do not need additional components to turn

off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOOe V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOOe

devices the best fit for portable electronics.

IGLOOe Device Family Overview

1-2 v1.2

Flash Advantages

Low Power

Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

IGLOOe devices also have low dynamic power consumption to further maximize power savings;

power is even further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOOe device the lowest total system power offered by any FPGA.

Security

The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides

a unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in IGLOOe devices can

be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. AES was adopted by the National Institute of Standards and Technology

(NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a built-in AES decryption

engine and a flash-based AES key that make them the most comprehensive programmable logic

device security solution available today. IGLOOe devices with AES-based security allow for secure,

remote field updates over public networks such as the Internet, and ensure that valuable IP

remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a

programmed IGLOOe device cannot be read back, although secure design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES

security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable

IP is protected and secure, making remote ISP possible. An IGLOOe device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

IGLOOe FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based IGLOOe devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based IGLOOe devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOOe device's

flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when

system power is restored. This enables the reduction or complete removal of the configuration

PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB

design. Flash-based IGLOOe devices simplify total system design and reduce cost and design risk

while increasing system reliability and improving system initialization time.

IGLOOe Low-Power Flash FPGAs

v1.2 1-3

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The IGLOOe family device

architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOOe

family a cost-effective ASIC replacement solution, especially for applications in the consumer,

networking/communications, computing, and avionics markets.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-

based FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot

be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors

occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all

modes of operation.

Advanced Architecture

The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The

IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on

page 4):

• Flash*Freeze technology

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the IGLOOe core tile as either a three-input lookup

table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.

The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture

flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash

switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect

programming. Maximum core utilization is possible for virtually any design.

IGLOOe Device Family Overview

1-4 v1.2

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of IGLOOe devices via an IEEE 1532 JTAG interface.

Flash*Freeze Technology

The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all

SRAM and register information and can still quickly return to normal operation. Flash*Freeze

technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating

the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and

global I/Os can still be driven and can be toggling without impact on power consumption, clocks

can still be driven or can be toggling without impact on power consumption, and the device retains

all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode

or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No

power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode.

Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the

power management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to

decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a

regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the

Figure 1-1 • IGLOOe Device Architecture Overview

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

IGLOOe Low-Power Flash FPGAs

v1.2 1-5

inherent low power static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an

illustration of entering/exiting Flash*Freeze mode.

VersaTiles

The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core

tiles. The IGLOOe VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

User Nonvolatile FlashROM

Actel IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for

a user design.

Figure 1-2 • IGLOOe Flash*Freeze Mode

Actel IGLOOe

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-3 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

IGLOOe Device Family Overview

1-6 v1.2

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel IGLOOe development software solutions, Libero® Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit

port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member

of the IGLOOe family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One

CCC (center west side) has a PLL.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used

• Maximum acquisition time is 300 µs

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC

IGLOOe Low-Power Flash FPGAs

v1.2 1-7

Global Clocking

IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

Pro I/Os with Advanced I/O Standards

The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including single-

ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks

per device (two per side). The configuration of these banks determines the I/O standards

supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced

I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.

Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that

minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

IGLOOe banks support M-LVDS with 20 multi-drop points.

IGLOOe Device Family Overview

1-8 v1.2

Part Number and Revision Date

Part Number 51700096-001-3

Revised October 2008

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v1.2) Page

v1.1

(June 2008)

The Quiescent Current values in the "IGLOOe Product Family" table were

updated.

v1.0

(April 2008)

As a result of the Libero IDE v8.4 release, Actel now offers a wide range of

core voltage support. The document was updated to change 1.2 V / 1.5 V to

1.2 V to 1.5 V.

N/A

51700096-001-1

(March 2008)

This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The

second section is a device family overview.

N/A

51700096-001-0

(January 2008)

The "Low Power" section was updated to change "1.2 V and 1.5 V Core

Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 µW)"

was removed from "Low-Power Active FPGA Operation."

1.2_V was added to the list of core and I/O voltages in the "Pro (Professional)

I/O" and "Pro I/Os with Advanced I/O Standards" sections.

I, 1-7

Advance v0.4

(December 2007)

This document was previously in datasheet Advance v0.4. As a result of

moving to the handbook format, Actel has restarted the version numbers.

The new version number is 51700096-001-0.

N/A

Advance v0.3

(September 2007)

Table 1 • IGLOOe Product Family was updated to change the maximum

number of user I/Os for AGLE3000.

Table 2 • IGLOOe FPGAs Package Sizes Dimensions is new. Package

dimensions were removed from the "I/Os Per Package1" table. The number

of I/Os was updated for FG896.

A note regarding marking information was added to "IGLOOe Ordering

Information".

iii

Advance v0.2

(July 2007)

Cortex-M1 device information was added to Cortex-M1 device information

was added to Table 1 • IGLOOe Product Family, the "I/Os Per Package1"

table, "IGLOOe Ordering Information", and Temperature Grade Offerings.

i, ii, iii, iv

Advance v0.1 The words "ambient temperature" were added to the temperature range in

the "IGLOOe Ordering Information", "Temperature Grade Offerings", and

"Speed Grade and Temperature Grade Matrix" sections.

iii, iv

IGLOOe Low-Power Flash FPGAs

v1.2 1-9

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

Advance v0.3 2-1

2 – IGLOOe DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI

and

VMV 3

DC I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

IGLOOe DC and Switching Characteristics

2-2 Advance v0.3

Table 2-2 • Recommended Operating Conditions 4

Symbol Parameter Commercial Industrial Units

TAAmbient Temperature 0 to +70 6 –40 to +85 7°C

TJJunction Temperature 80 to + 85 –40 to +100

VCC 1.5 V DC core supply

voltage1 1.425 to 1.575 1.425 to 1.575 V

1.2 V–1.5 V wide range core

voltage21.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP 5Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation3 0 to 3.45 0 to 3.45 V

VCCPLL 9 Analog power supply (PLL) 1.5 V DC core supply voltage1 1.4 to 1.6 1.4 to 1.6 V

1.2 V–1.5 V wide range core

voltage21.14 to 1.575 1.14 to 1.575 V

VCCI and

VMV 10 1.2 V DC supply voltage2 1.14 to 1.26 1.14 to 1.26 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. For IGLOOe V5 devices

2. For IGLOOe V2 devices only, operating at VCCI

≥

VCC

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-20 on page 2-20. VCCI should be at the same voltage within a given I/O

bank.

4. All parameters representing voltages are measured with respect to GND unless otherwise specified.

5. VPUMP can be left floating during operation (not programming mode).

6. Maximum TJ = 85 °C.

7. Maximum TJ = 100 °C.

8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

9. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.

10. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOOe device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In

addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

IGLOOe I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI

Average VCCI–GND Overshoot or Undershoot Duration

as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. The device meets overshoot/undershoot specification requirements for PCI inputs with VCCI = 3.45 V at 85°C

maximum, whereas the average toggling of inputs at one-sixth of PCI frequency is considered.

IGLOOe DC and Switching Characteristics

2-4 Advance v0.3

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper

powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed

brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1

and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

Figure 2-1 • V5 – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-5

Thermal Characteristics

Introduction

The temperature variable in Actel Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because V

CCI

are below

specification. For the same reason, input

buffers do not meet V

levels, and

output buffers do not meet V

levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

VCC

VCC = 1.14 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.2 V

eactivation trip point:

Vd = 0.75 V ± 0.2 V

Activation trip point:

Va = 0.9 V ± 0.15 V

Deactivation trip point:

Vd = 0.8 V ± 0.15 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, V

, V

, etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because V

CCI

below specification. For the

same reason, input buffers do not

meet V

levels, and output

buffers do not meet V

levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V

is below specification.

VCC = VCCI + VT

IGLOOe DC and Switching Characteristics

2-6 Advance v0.3

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 100°C70°C–

13.6°C/W

------------------------------------ 2 . 2 0 6 W===

Table 2-5 • Package Thermal Resistivities

Package Type Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W

484 3.2 20.5 17.0 15.9 C/W

676 3.2 16.4 13.0 12.0 C/W

896 2.4 13.6 10.4 9.4 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C,VCC = 1.425 V)

For IGLOOe V2 or V5 devices, 1.5 V DC Core Supply Voltage

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.425 0.95 0.96 0.98 1.00 1.01 1.02

1.5 0.880.890.910.930.930.94

1.575 0.82 0.84 0.85 0.87 0.88 0.89

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC =1.14V)

For IGLOOe V2, 1.2 V DC Core Supply Voltage

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 110°C

1.14 0.97 0.98 0.99 1.00 1.01 1.01

1.2 0.840.850.860.870.880.88

1.26 0.76 0.77 0.78 0.79 0.79 0.80

IGLOOe DC and Switching Characteristics

Advance v0.3 2-7

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating

voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power

modes usage. Actel recommends using the PowerCalculator and SmartPower software

estimation tools to evaluate the projected static and active power based on the user design,

power mode usage, operating voltage, and temperature.

Table 2-8 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode*

Core Voltage AGLE600 AGLE3000 Units

Typical (25°C) 1.2 V 34 95 µA

1.5 V 72 310 µA

*IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6

and PDC7).

Table 2-9 • Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)*

Core Voltage AGLE600 AGLE3000 Units

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V 1.7 1.7 µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.8 1.8 µA

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.9 1.9 µA

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.2 2.2 µA

VCCI/VJTAG= 3.3 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.5 2.5 µA

*IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).

Table 2-10 • Quiescent Supply Current (IDD), IGLOOe Shutdown Mode (VCC, VCCI = 0 V)*

Core Voltage AGLE600 AGLE3000 Units

Typical (25°C) 1.2 V / 1.5 V 0 0 µA

*IDD includes VCC , VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6

and PDC7).

IGLOOe DC and Switching Characteristics

2-8 Advance v0.3

Table 2-11 • Quiescent Supply Current, No IGLOOe Flash*Freeze Mode*

Core Voltage AGLE600 AGLE3000 Units

ICCA Current2

Typical (25°C) 1.2 V 28 89 µA

1.5 V 82 320 µA

ICCI or IJTAG Current3, 4

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V 1.7 1.7 µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.8 1.8 µA

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.9 1.9 µA

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.2 2.2 µA

VCCI/VJTAG= 3.3 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.5 2.5 µA

Notes:

1. To calculate total device IDD, multiply the number of banks used in ICCI and add ICCA contribution.

2. Includes VCC, VCCPLL, and VPUMP currents.

3. Per VCCI or VJTAG bank

4. Values do not include I/O static contribution (PDC6 and PDC7).

IGLOOe DC and Switching Characteristics

Advance v0.3 2-9

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

VCCI

(V)

Static Power

PDC6 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL/LVCMOS 3.3 – 16.34

3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49

2.5 V LVCMOS 2.5 – 4.71

2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13

1.8 V LVCMOS 1.8 – 1.66

1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78

1.5 V LVCMOS (JESD8-11) 1.5 – 1.01

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97

1.2 V LVCMOS 31.2 – 0.60

1.2 V LVCMOS – Schmitt trigger 31.2 – 0.53

3.3 V PCI 3.3 – 17.76

3.3 V PCI – Schmitt trigger 3.3 – 19.10

3.3 V PCI-X 3.3 – 17.76

3.3 V PCI-X – Schmitt trigger 3.3 – 19.10

Voltage-Referenced

3.3 V GTL 3.3 2.90 7.07

2.5 V GTL 2.5 2.13 3.62

3.3 V GTL+ 3.3 2.81 2.97

2.5 V GTL+ 2.5 2.57 2.55

HSTL (I) 1.5 0.17 0.85

HSTL (II) 1.5 0.17 0.85

SSTL2 (I) 2.5 1.38 3.30

SSTL2 (II) 2.5 1.38 3.30

SSTL3 (I) 3.3 3.21 8.08

SSTL3 (II) 3.3 3.21 8.08

Differential

LVDS 2.5 2.26 0.95

LVPECL 3.3 5.71 1.62

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. Applicable for IGLOOe V2 devices only.

IGLOOe DC and Switching Characteristics

2-10 Advance v0.3

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD

(pF)

VCCI

(V)

Static Power

PDC7 (mW)2Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS 5 3.3 – 148.00

2.5 V LVCMOS 5 2.5 – 83.23

1.8 V LVCMOS 5 1.8 – 54.58

1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05

1.2 V LVCMOS 45 1.2 – 17.94

3.3 V PCI 10 3.3 – 204.61

3.3 V PCI-X 10 3.3 – 204.61

Voltage-Referenced

3.3 V GTL 10 3.3 – 24.08

2.5 V GTL 10 2.5 – 13.52

3.3 V GTL+ 10 3.3 – 24.10

2.5 V GTL+ 10 2.5 – 13.54

HSTL (I) 20 1.5 7.08 26.22

HSTL (II) 20 1.5 13.88 27.22

SSTL2 (I) 30 2.5 16.69 105.56

SSTL2 (II) 30 2.5 25.91 116.60

SSTL3 (I) 30 3.3 26.02 114.87

SSTL3 (II) 30 3.3 42.21 131.76

Differential

LVDS – 2.5 7.70 89.62

LVPECL – 3.3 19.42 168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. Applicable for IGLOOe V2 devices only.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-11

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices

For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Parameter Definition

Device-Specific Dynamic

Contributions (µW/MHz)

AGLE600 AGLE3000

PAC1 Clock contribution of a Global Rib 19.7 12.77

PAC2 Clock contribution of a Global Spine 4.16 1.85

PAC3 Clock contribution of a VersaTile row 0.88

PAC4 Clock contribution of a VersaTile used as a sequential module 0.11

PAC5 First contribution of a VersaTile used as a sequential module 0.057

PAC6 Second contribution of a VersaTile used as a sequential module 0.207

PAC7 Contribution of a VersaTile used as a combinatorial module 0.207

PAC8 Average contribution of a routing net 0.7

PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-9.

PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-13 on page 2-10.

PAC11 Average contribution of a RAM block during a read operation 25.00

PAC12 Average contribution of a RAM block during a write operation 30.00

PAC13 Dynamic contribution for PLL 2.70

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or

SmartPower in Actel Libero® Integrated Design Environment (IDE) software.

Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Parameter Definition

Device Specific Static Power (mW)

AGLE600 AGLE3000

PDC1 Array static power in Active mode See Table 2-11 on page 2-8.

PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7.

PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7.

PDC4 Static PLL contribution 1.84

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8.

PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9.

PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10.

IGLOOe DC and Switching Characteristics

2-12 Advance v0.3

Table 2-16 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices

For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage

Parameter Definition

Device-Specific Dynamic

Contributions (µW/MHz)

AGLE600 AGLE3000

PAC1 Clock contribution of a Global Rib 12.61 8.17

PAC2 Clock contribution of a Global Spine 2.66 1.18

PAC3 Clock contribution of a VersaTile row 0.56

PAC4 Clock contribution of a VersaTile used as a sequential module 0.071

PAC5 First contribution of a VersaTile used as a sequential module 0.045

PAC6 Second contribution of a VersaTile used as a sequential module 0.186

PAC7 Contribution of a VersaTile used as a combinatorial module 0.109

PAC8 Average contribution of a routing net 0.449

PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-8 on page 2-7.

PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-9 on page 2-7

and Table 2-10 on page 2-7.

PAC11 Average contribution of a RAM block during a read operation 25.00

PAC12 Average contribution of a RAM block during a write operation 30.00

PAC13 Dynamic PLL contribution 2.10

*For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or

SmartPower in Actel Libero IDE software.

Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage

Parameter Definition

Device Specific Static Power (mW)

AGLE600 AGLE3000

PDC1 Array static power in Active mode See Table 2-11 on page 2-8.

PDC2 Array static power in Static (Idle) mode See Table 2-10 on page 2-7.

PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7.

PDC4 Static PLL contribution 0.90

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-11 on page 2-8.

PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9.

PDC7 I/O output pin static power (standard-dependent) See Table 2-13 on page 2-10.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-13

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-18 on

page 2-15.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-19 on page 2-15.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-19 on page 2-15. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided

in Table 2-18 on page 2-15.

NROW is the number of VersaTile rows used in the design—guidelines are provided in

Table 2-18 on page 2-15.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-15.

FCLK is the global clock signal frequency.

IGLOOe DC and Switching Characteristics

2-14 Advance v0.3

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-15.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-15.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-15.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-15.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-19

on page 2-15.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19

on page 2-15.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-15

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of

the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-18 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-19 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

IGLOOe DC and Switching Characteristics

2-16 Advance v0.3

User I/O Characteristics

Timing Model

Figure 2-3 • Timing Model

Operating Conditions: Std. Speed, Commercial Temperature Range (TJ= 70°C), Worst-Case

VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL

LVDS,

BLVDS,

M-LVDS

GTL+ 3.3V

Combinational Cell

I/O Module

(Non-Registered)

LVTTL/LVCMOS 3.3 V

Output drive strength = 24 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5V

Output drive strength = 12 mA

High slew

LVTTL/LVCMOS 3.3 V

Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL/LVCMOS 3.3 V

Clock

Input LVTTL/LVCMOS 3.3 V

Clock

Input LVTTL/LVCMOS 3.3 V

Clock

tPD = 1.19 ns tPD = 1.04 ns

tDP = 1.75 ns

tPD = 1.77 ns tDP = 3.13 ns

tPD = 1.33 ns

tPD = 0.85 ns

tDP = 2.76 ns

tDP = 3.30 ns

tOCLKQ = 1.02 ns

tDP = 1.85 ns

tOSUD = 0.52 ns

tPY = 1.10 ns

tCLKQ = 0.90 ns

tSUD = 0.82 ns

tPY = 1.10 ns

tPD = 0.90 ns

tCLKQ = 0.90 ns

tSUD = 0.82 ns

tPY = 1.62 ns

tPY = 1.10 ns

tICLKQ = 0.43 ns

tISUD = 0.47 ns

tPY = 1.45 ns

IGLOOe DC and Switching Characteristics

Advance v0.3 2-17

Figure 2-4 • Input Buffer Timing Model and Delays (example)

(R)

PAD

GND

(F)

50%

(R) (F)

(R)

DIN

GND

(F)

50%50%

PAD Y

CLK

I/O Interface

DIN

To Array

tDOUT tDOUT

VCC

tPYS

tPY

tPYS

tPY

VCC

Vtrip Vtrip

VIH

VIL

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

tPY tDIN

IGLOOe DC and Switching Characteristics

2-18 Advance v0.3

Figure 2-5 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

IGLOOe DC and Switching Characteristics

Advance v0.3 2-19

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

IGLOOe DC and Switching Characteristics

2-20 Advance v0.3

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions

I/O Standard

Drive

Strength Slew Rate

VIL VIH VOL VOH IOL1IOH1

Min., V Max., V Min., V Max., V Max., V Min., V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65*VCCI 1.9 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65*VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

1.2 V LVCMOS42 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 22

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

2.5 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 2.7 0.4 – 25 25

3.3 V GTL+ 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 35 35

2.5 V GTL+ 33 mA High –0.3 VREF – 0.1 VREF + 0.1 2.7 0.6 – 33 33

HSTL (I) 8 mA High –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 8 8

HSTL (II) 15 mA2High –0.3 VREF – 0.1 VREF + 0.1 1.575 0.4 VCCI – 0.4 15 15

SSTL2 (I) 15 mA High –0.3 VREF – 0.2 VREF + 0.2 2.7 0.54 VCCI – 0.62 15 15

SSTL2 (II) 18 mA High –0.3 VREF – 0.2 VREF + 0.2 2.7 0.35 VCCI – 0.43 18 18

SSTL3 (I) 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14

SSTL3 (II) 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output Slew Rates can be extracted from IBIS Models, located at

http://www.actel.com/download/ibis/default.aspx.

4. Applicable to V2 Devices ONLY, operating in the 1.2 V core range.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-21

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS310 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10 10 15 15

HSTL (II) 10 10 15 15

SSTL2 (I) 10 10 15 15

SSTL2 (II) 10 10 15 15

SSTL3 (I) 10 10 15 15

SSTL3 (II) 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. Applicable to V2 Devices ONLY, operating in the 1.2 V core range.

IGLOOe DC and Switching Characteristics

2-22 Advance v0.3

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-22 • Summary of AC Measuring Points

Standard

Input Reference

Voltage (VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip

Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS – – 1.4 V

2.5 V LVCMOS – – 1.2 V

1.8 V LVCMOS – – 0.90 V

1.5 V LVCMOS – – 0.75 V

1.2 V LVCMOS – – 0.6 V

3.3 V PCI – – 0.285*VCCI (RR)

– – 0.615*VCCI (FF))

3.3 V PCI-X – – 0.285*VCCI (RR)

– – 0.615*VCCI (FF)

3.3 V GTL 0.8 V 1.2 V VREF

2.5 V GTL 0.8 V 1.2 V VREF

3.3 V GTL+ 1.0 V 1.5 V VREF

2.5 V GTL+ 1.0 V 1.5 V VREF

HSTL (I) 0.75 V 0.75 V VREF

HSTL (II) 0.75 V 0.75 V VREF

SSTL2 (I) 1.25 V 1.25 V VREF

SSTL2 (II) 1.25 V 1.25 V VREF

SSTL3 (I) 1.5 V 1.485 V VREF

SSTL3 (II) 1.5 V 1.485 V VREF

LVDS – – Cross point

LVPECL – – Cross point

Table 2-23 • I/O AC Parameter Definitions

Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

IGLOOe DC and Switching Characteristics

Advance v0.3 2-23

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5 – 0.98 2.18 0.19 1.10 1.37 0.67 2.22 1.72 2.78 3.17 5.85 5.35 ns

2.5 V LVCMOS 12 mA High 5 – 0.98 2.21 0.19 1.34 1.45 0.67 2.25 1.89 2.86 3.06 5.88 5.52 ns

1.8 V LVCMOS 12 mA High 5 – 0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11 5.70 ns

1.5 V LVCMOS 12 mA High 5 – 0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98 ns

3.3 V PCI Per PCI

spec

High 10 25 2 0.98 2.44 0.19 0.98 1.45 0.67 2.49 1.84 2.79 3.17 6.12 5.47 ns

3.3 V PCI-X Per PCI-X

spec

High 10 25 2 0.98 2.44 0.19 0.94 1.37 0.67 2.49 1.84 2.79 3.17 6.12 5.47 ns

3.3 V GTL 25 mA High 10 25 0.98 1.83 0.19 2.41 – 0.67 1.84 1.83 0.00 0.00 5.47 5.46 ns

2.5 V GTL 25 mA High 10 25 0.98 1.90 0.19 2.04 – 0.67 1.94 1.87 0.00 0.00 5.57 5.50 ns

3.3 V GTL+ 35 mA High 10 25 0.98 1.85 0.19 1.35 – 0.67 1.88 1.81 0.00 0.00 5.51 5.44 ns

2.5 V GTL+ 33 mA High 10 25 0.98 1.97 0.19 1.29 – 0.67 2.00 1.84 0.00 0.00 5.63 5.47 ns

HSTL (I) 8 mA High 20 50 0.98 2.74 0.19 1.77 – 0.67 2.79 2.73 0.00 0.00 6.42 6.36 ns

HSTL (II) 15 mA High 20 25 0.98 2.62 0.19 1.77 – 0.67 2.66 2.40 0.00 0.00 6.29 6.03 ns

SSTL2 (I) 15 mA High 30 50 0.98 1.91 0.19 1.15 – 0.67 1.94 1.72 0.00 0.00 5.57 5.35 ns

SSTL2 (II) 18 mA High 30 25 0.98 1.94 0.19 1.15 – 0.67 1.97 1.66 0.00 0.00 5.60 5.29 ns

SSTL3 (I) 14 mA High 30 50 0.98 2.05 0.19 1.09 – 0.67 2.09 1.71 0.00 0.00 5.72 5.34 ns

SSTL3 (II) 21 mA High 30 25 0.98 1.86 0.19 1.09 – 0.67 1.89 1.58 0.00 0.00 5.52 5.21 ns

LVDS/B-LVDS/

M-LVDS

24 mA High – – 0.981.770.191.62–––––––– ns

LVPECL 24 mA High – – 0.981.750.191.45–––––––– ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-42 for connectivity. This resistor is not required during normal operation.

IGLOOe DC and Switching Characteristics

2-24 Advance v0.3

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High 5 – 1.55 2.46 0.26 1.31 1.57 1.10 2.51 2.04 3.27 3.96 8.32 7.85 ns

2.5 V LVCMOS 12 mA High 5 – 1.55 2.50 0.26 1.55 1.76 1.10 2.54 2.22 3.34 3.83 8.35 8.03 ns

1.8 V LVCMOS 12 mA High 5 – 1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21 ns

1.5 V LVCMOS 12 mA High 5 – 1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96 8.51 ns

1.2 V LVCMOS 2mA High 5 – 1.55 4.07 0.26 2.06 2.96 1.10 3.90 3.43 3.80 4.02 9.49 9.03 ns

3.3 V PCI Per PCI

spec

High 10 25 2 1.55 2.74 0.26 1.19 1.63 1.10 2.80 2.16 3.28 3.96 8.60 7.97 ns

3.3 V PCI-X Per PCI-X

spec

High 10 25 2 1.55 2.74 0.26 1.21 1.57 1.10 2.80 2.16 3.28 3.96 8.60 7.97 ns

3.3 V GTL 25 mA High 10 25 1.55 2.09 0.26 2.75 – 1.10 2.10 2.09 – – 7.91 7.89 ns

2.5 V GTL 25 mA High 10 25 1.55 2.16 0.26 2.35 – 1.10 2.20 2.13 – – 8.01 7.94 ns

3.3 V GTL+ 35 mA High 10 25 1.55 2.11 0.26 1.61 – 1.10 2.15 2.07 – – 7.95 7.88 ns

2.5 V GTL+ 33 mA High 10 25 1.55 2.23 0.26 1.55 – 1.10 2.28 2.11 – – 8.08 7.91 ns

HSTL (I) 8 mA High 20 50 1.55 3.10 0.26 1.94 – 1.10 3.12 3.10 – – 8.93 8.91 ns

HSTL (II) 15 mA High 20 25 1.55 2.93 0.26 1.94 – 1.10 2.98 2.75 – – 8.79 8.55 ns

SSTL2 (I) 15 mA High 30 50 1.55 2.17 0.26 1.39 – 1.10 2.21 2.04 – – 8.02 7.84 ns

SSTL2 (II) 18 mA High 30 25 1.55 2.20 0.26 1.39 – 1.10 2.24 1.97 – – 8.05 7.78 ns

SSTL3 (I) 14 mA High 30 50 1.55 2.32 0.26 1.32 – 1.10 2.37 2.02 – – 8.17 7.83 ns

SSTL3 (II) 21 mA High 30 25 1.55 2.12 0.26 1.32 – 1.10 2.16 1.89 – – 7.97 7.70 ns

LVDS/B-LVDS/

M-LVDS

24 mA High – – 1.55 2.19 0.26 1.88 – – – – – – – – ns

LVPECL 24 mA High – – 1.55 2.16 0.26 1.70 – – – – – – – – ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-42 for connectivity. This resistor is not required during normal operation.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-25

Detailed I/O DC Characteristics

Table 2-26 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-27 • I/O Output Buffer Maximum Resistances1

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 4 mA 100 200

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCI-X Per PCI/PCI-X

specification

25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

IGLOOe DC and Switching Characteristics

2-26 Advance v0.3

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50

HSTL (II) 15 mA 25 25

SSTL2 (I) 15 mA 27 31

SSTL2 (II) 18 mA 13 15

SSTL3 (I) 14 mA 44 69

SSTL3 (II) 21 mA 18 32

Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R((WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V TBD TBD TBD TBD

Notes:

1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN

Table 2-27 • I/O Output Buffer Maximum Resistances1 (continued)

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

IGLOOe DC and Switching Characteristics

Advance v0.3 2-27

Table 2-29 • I/O Short Currents IOSH/IOSL

Drive Strength IOSH (mA)* IOSL (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

2.5 V LVCMOS 4 mA 16 18

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

1.2 V LVCMOS 2 mA TBD TBD

3.3 V PCI/PCIX Per PCI/PCI-X Specification Per PCI Curves

3.3 V GTL 25 mA 268 181

2.5 V GTL 25 mA 169 124

3.3 V GTL+ 35 mA 268 181

2.5 V GTL+ 33 mA 169 124

HSTL (I) 8 mA 32 39

HSTL (II) 15 mA 66 55

SSTL2 (I) 15 mA 83 87

SSTL2 (II) 18 mA 169 124

SSTL3 (I) 14 mA 51 54

SSTL3 (II) 21 mA 103 109

*TJ = 100°C

IGLOOe DC and Switching Characteristics

2-28 Advance v0.3

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-30 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-31 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement 10 ns* 20 years (110°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement No requirement, but input noise

voltage cannot exceed Schmitt

hysteresis.

20 years (110°C)

HSTL/SSTL/GTL No requirement 10 ns* 10 years (100°C)

LVDS/B-LVDS/M-LVDS/LVPECL No requirement 10 ns* 10 years (100°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-29

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS

standard is supported as part of the 3.3 V LVTTL support.

Table 2-33 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 132 127 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 268 181 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

03.31.4–5

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOOe DC and Switching Characteristics

2-30 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.98 5.04 0.19 1.10 1.37 0.67 5.13 4.10 2.33 2.22 8.76 7.73 ns

8 mA Std. 0.98 4.16 0.19 1.10 1.37 0.67 4.23 3.54 2.60 2.72 7.86 7.17 ns

12 mA Std. 0.98 3.53 0.19 1.10 1.37 0.67 3.60 3.12 2.78 3.03 7.23 6.75 ns

16 mA Std. 0.98 3.36 0.19 1.10 1.37 0.67 3.42 3.03 2.82 3.12 7.05 6.66 ns

24 mA Std. 0.98 3.26 0.19 1.10 1.37 0.67 3.32 3.04 2.87 3.45 6.95 6.67 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.98 2.93 0.19 1.10 1.37 0.67 2.99 2.33 0.00 2.34 6.62 5.96 ns

8 mA Std. 0.98 2.45 0.19 1.10 1.37 0.67 2.50 1.92 2.60 2.84 6.13 5.55 ns

12 mA Std. 0.98 2.18 0.19 1.10 1.37 0.67 2.22 1.72 2.78 3.17 5.85 5.35 ns

16 mA Std. 0.98 2.13 0.19 1.10 1.37 0.67 2.17 1.69 2.83 3.26 5.80 5.32 ns

24 mA Std. 0.98 2.15 0.19 1.10 1.37 0.67 2.19 1.64 2.88 3.58 5.82 5.27 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-31

1.2 V DC Core Voltage

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 5.53 0.26 1.31 1.57 1.10 5.63 4.53 2.78 2.85 11.44 10.34 ns

8 mA Std. 1.55 4.58 0.26 1.31 1.57 1.10 4.67 3.95 3.07 3.44 10.48 9.76 ns

12 mA Std. 1.55 3.92 0.26 1.31 1.57 1.10 3.99 3.51 3.27 3.80 9.80 9.32 ns

16 mA Std. 1.55 3.73 0.26 1.31 1.57 1.10 3.79 3.41 3.31 3.90 9.60 9.22 ns

24 mA Std. 1.55 3.62 0.26 1.31 1.57 1.10 3.69 3.42 3.36 4.28 9.50 9.23 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 3.27 0.26 1.31 1.57 1.10 3.33 2.67 2.78 2.99 9.14 8.48 ns

8 mA Std. 1.55 2.75 0.26 1.31 1.57 1.10 2.81 2.24 3.07 3.58 8.61 8.05 ns

12 mA Std. 1.55 2.46 0.26 1.31 1.57 1.10 2.51 2.04 3.27 3.96 8.32 7.85 ns

16 mA Std. 1.55 2.41 0.26 1.31 1.57 1.10 2.46 2.00 3.32 4.06 8.27 7.81 ns

24 mA Std. 1.55 2.43 0.26 1.31 1.57 1.10 2.48 1.95 3.37 4.44 8.29 7.76 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-32 Advance v0.3

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-39 • Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10

16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 83 87 10 10

24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

02.51.2–5

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOOe DC and Switching Characteristics

Advance v0.3 2-33

Timing Characteristics

1.5 V DC Core Voltage

Table 2-41 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.98 5.70 0.19 1.34 1.45 0.67 5.81 4.87 2.34 2.01 9.44 8.50 ns

8 mA Std. 0.98 4.71 0.19 1.34 1.45 0.67 4.79 4.17 2.65 2.60 8.42 7.80 ns

12 mA Std. 0.98 4.00 0.19 1.34 1.45 0.67 4.07 3.67 2.86 2.99 7.70 7.30 ns

16 mA Std. 0.98 3.78 0.19 1.34 1.45 0.67 3.85 3.56 2.90 3.09 7.48 7.19 ns

24 mA Std. 0.98 3.69 0.19 1.34 1.45 0.67 3.75 3.57 2.96 3.46 7.38 7.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-42 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.98 3.02 0.19 1.34 1.45 0.67 3.08 2.74 2.34 2.08 6.71 6.37 ns

8 mA Std. 0.98 2.51 0.19 1.34 1.45 0.67 2.56 2.17 2.65 2.69 6.19 5.80 ns

12 mA Std. 0.98 2.21 0.19 1.34 1.45 0.67 2.25 1.89 2.86 3.06 5.88 5.52 ns

16 mA Std. 0.98 2.16 0.19 1.34 1.45 0.67 2.20 1.84 2.90 3.17 5.83 5.47 ns

24 mA Std. 0.98 2.17 0.19 1.34 1.45 0.67 2.21 1.77 2.96 3.57 5.84 5.40 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-34 Advance v0.3

1.2 V DC Core Voltage

Table 2-43 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 6.24 0.26 1.55 1.76 1.10 6.36 5.34 2.80 2.61 12.17 11.15 ns

8 mA Std. 1.55 5.17 0.26 1.55 1.76 1.10 5.27 4.61 3.12 3.30 11.08 10.42 ns

12 mA Std. 1.55 4.41 0.26 1.55 1.76 1.10 4.49 4.08 3.34 3.75 10.30 9.89 ns

16 mA Std. 1.55 4.18 0.26 1.55 1.76 1.10 4.26 3.96 3.39 3.87 10.06 9.77 ns

24 mA Std. 1.55 4.08 0.26 1.55 1.76 1.10 4.15 3.98 3.45 4.30 9.96 9.79 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

Table 2-44 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 1.55 3.36 0.26 1.55 1.76 1.10 3.43 3.11 2.80 2.70 9.23 8.92 ns

8 mA Std. 1.55 2.82 0.26 1.55 1.76 1.10 2.87 2.51 3.12 3.40 8.68 8.32 ns

12 mA Std. 1.55 2.50 0.26 1.55 1.76 1.10 2.54 2.22 3.34 3.83 8.35 8.03 ns

16 mA Std. 1.55 2.44 0.26 1.55 1.76 1.10 2.49 2.16 3.39 3.95 8.29 7.97 ns

24 mA Std. 1.55 2.45 0.26 1.55 1.76 1.10 2.50 2.09 3.45 4.42 8.31 7.90 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-35

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 17 22 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 45 51 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12 91 74 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 16 16 91 74 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

01.80.9–5

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOOe DC and Switching Characteristics

2-36 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

Table 2-47 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.98 7.53 0.19 1.30 1.63 0.67 7.67 6.34 2.40 1.21 11.30 9.97 ns

4 mA Std. 0.98 6.24 0.19 1.30 1.63 0.67 6.36 5.38 2.77 2.48 9.99 9.01 ns

6 mA Std. 0.98 5.33 0.19 1.30 1.63 0.67 5.43 4.73 3.01 2.96 9.06 8.36 ns

8 mA Std. 0.98 5.02 0.19 1.30 1.63 0.67 5.11 4.60 3.07 3.09 8.74 8.23 ns

12 mA Std. 0.98 4.93 0.19 1.30 1.63 0.67 5.02 4.61 3.15 3.57 8.65 8.24 ns

16 mA Std. 0.98 4.93 0.19 1.30 1.63 0.67 5.02 4.61 3.15 3.57 8.65 8.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-48 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.98 3.53 0.19 1.30 1.63 0.67 3.59 3.47 2.39 1.23 7.22 7.10 ns

4 mA Std. 0.98 2.90 0.19 1.30 1.63 0.67 2.96 2.65 2.76 2.56 6.59 6.28 ns

6 mA Std. 0.98 2.52 0.19 1.30 1.63 0.67 2.57 2.24 3.01 3.03 6.20 5.87 ns

8 mA Std. 0.98 2.45 0.19 1.30 1.63 0.67 2.49 2.17 3.07 3.17 6.12 5.80 ns

12 mA Std. 0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11 5.70 ns

16 mA Std. 0.98 2.44 0.19 1.30 1.63 0.67 2.48 2.07 3.15 3.67 6.11 5.70 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-37

1.2 V DC Core Voltage

Table 2-49 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 8.20 0.26 1.53 1.95 1.10 8.35 6.89 2.86 1.68 14.16 12.69 ns

4 mA Std. 1.55 6.82 0.26 1.53 1.95 1.10 6.95 5.88 3.25 3.16 12.75 11.69 ns

6 mA Std. 1.55 5.84 0.26 1.53 1.95 1.10 5.95 5.20 3.51 3.71 11.75 11.00 ns

8 mA Std. 1.55 5.51 0.26 1.53 1.95 1.10 5.61 5.06 3.58 3.87 11.42 10.87 ns

12 mA Std. 1.55 5.41 0.26 1.53 1.95 1.10 5.51 5.07 3.66 4.42 11.32 10.88 ns

16 mA Std. 1.55 5.41 0.26 1.53 1.95 1.10 5.51 5.07 3.66 4.42 11.32 10.88 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

Table 2-50 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.91 0.26 1.53 1.95 1.10 3.98 3.88 2.85 1.70 9.79 9.68 ns

4 mA Std. 1.55 3.24 0.26 1.53 1.95 1.10 3.30 3.01 3.24 3.25 9.11 8.82 ns

6 mA Std. 1.55 2.83 0.26 1.53 1.95 1.10 2.88 2.58 3.51 3.80 8.69 8.39 ns

8 mA Std. 1.55 2.75 0.26 1.53 1.95 1.10 2.80 2.51 3.57 3.95 8.61 8.31 ns

12 mA Std. 1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21 ns

16 mA Std. 1.55 2.74 0.26 1.53 1.95 1.10 2.79 2.41 3.66 4.54 8.60 8.21 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-38 Advance v0.3

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-51 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6 6 32 39 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8 8 66 55 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12 66 55 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-10 • AC Loading

Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 1.5 0.75 – 5

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOOe DC and Switching Characteristics

Advance v0.3 2-39

Timing Characteristics

1.5 V DC Core Voltage

Table 2-53 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.98 7.82 0.19 1.50 1.82 0.67 7.97 6.49 2.89 2.41 11.60 10.12 ns

4 mA Std. 0.98 6.72 0.19 1.50 1.82 0.67 6.84 5.71 3.17 2.96 10.47 9.34 ns

6 mA Std. 0.98 6.32 0.19 1.50 1.82 0.67 6.44 5.56 3.24 3.11 10.07 9.19 ns

8 mA Std. 0.98 6.24 0.19 1.50 1.82 0.67 6.36 5.56 3.33 3.66 9.99 9.19 ns

12 mA Std. 0.98 6.24 0.19 1.50 1.82 0.67 6.36 5.56 3.33 3.66 9.99 9.19 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-54 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.98 3.34 0.19 1.50 1.82 0.67 3.41 3.07 2.88 2.50 7.04 6.70 ns

4 mA Std. 0.98 2.88 0.19 1.50 1.82 0.67 2.94 2.57 3.17 3.05 6.57 6.20 ns

6 mA Std. 0.98 3.90 0.19 1.50 1.82 0.67 3.97 3.79 3.17 3.20 7.60 7.42 ns

8 mA Std. 0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98 ns

12 mA Std. 0.98 2.77 0.19 1.50 1.82 0.67 2.82 2.35 3.33 3.78 6.45 5.98 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-40 Advance v0.3

1.2 V DC Core Voltage

Table 2-55 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 8.51 0.26 1.72 2.15 1.10 8.67 7.05 3.38 3.07 14.48 12.86 ns

4 mA Std. 1.55 7.33 0.26 1.72 2.15 1.10 7.47 6.22 3.69 3.71 13.27 12.03 ns

6 mA Std. 1.55 6.90 0.26 1.72 2.15 1.10 7.03 6.07 3.75 3.88 12.84 11.88 ns

8 mA Std. 1.55 6.82 0.26 1.72 2.15 1.10 6.95 6.07 3.86 4.52 12.75 11.88 ns

12 mA Std. 1.55 6.82 0.26 1.72 2.15 1.10 6.95 6.07 3.86 4.52 12.75 11.88 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

Table 2-56 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 3.71 0.26 1.72 2.15 1.10 3.78 3.46 3.37 3.18 9.59 9.26 ns

4 mA Std. 1.55 3.22 0.26 1.72 2.15 1.10 3.28 2.92 3.68 3.81 9.09 8.73 ns

6 mA Std. 1.55 4.30 0.26 1.72 2.15 1.10 4.38 4.21 3.69 4.00 10.19 10.02 ns

8 mA Std. 1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96 8.51 ns

12 mA Std. 1.55 3.09 0.26 1.72 2.15 1.10 3.15 2.70 3.85 4.66 8.96 8.51 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-41

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose

1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Timing Characteristics

1.2 V DC Core Voltage

Table 2-57 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 TBD TBD 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-11 • AC Loading

Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.20.65

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

Table 2-59 • 1.2 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 9.93 0.26 2.06 2.96 1.10 9.50 7.45 3.68 4.03 15.10 13.05 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-60 • 1.2 LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 1.55 4.07 0.26 2.06 2.96 1.10 3.90 3.43 3.80 4.02 9.49 9.03 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

IGLOOe DC and Switching Characteristics

2-42 Advance v0.3

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-12.

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-62.

Table 2-61 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL

HIOSH IOSL IIL IIH

Drive Strength

Min.,

Max.,

Min.,

Max.,

Min.,

AMax., mA

1Max., mA1µA

2µA

Per PCI

specification

Per PCI curves 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-12 • AC Loading

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

Table 2-62 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

–10

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-43

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-63 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 2.44 0.19 0.98 1.45 0.67 2.49 1.84 2.79 3.17 6.12 5.47 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-64 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.74 0.26 1.19 1.63 1.10 2.80 2.16 3.28 3.96 8.60 7.97 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-44 Advance v0.3

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

3.3 V.

Table 2-65 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

25 mA3 –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 268 181 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-13 • AC Loading

Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

10 pF

GTL

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-45

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-67 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.83 0.19 2.41 0.67 1.84 1.83 5.47 5.46 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-68 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.09 0.26 2.75 1.10 2.10 2.09 7.91 7.89 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-46 Advance v0.3

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

2.5 V.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

2.5 GTL VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

25 mA3 –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-14 • AC Loading

Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

10 pF

GTL

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-47

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-71 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.90 0.19 2.04 0.67 1.94 1.87 5.57 5.50 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-72 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.16 0.26 2.35 1.10 2.20 2.13 8.01 7.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-48 Advance v0.3

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

3.3 V

Table 2-73 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

35 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 35 35 268 181 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-15 • AC Loading

Table 2-74 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-49

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-75 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.85 0.19 1.35 0.67 1.88 1.81 5.51 5.44 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-76 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.11 0.26 1.61 1.10 2.15 2.07 7.95 7.88 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-50 Advance v0.3

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

2.5 V.

Table 2-77 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

33 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 33 33 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-16 • AC Loading

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-51

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-79 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.97 0.19 1.29 0.67 2.00 1.84 5.63 5.47 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-80 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.23 0.26 1.55 1.10 2.28 2.11 8.08 7.91 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-52 Advance v0.3

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-81 • Minimum and Maximum DC Input and Output Levels

HSTL Class I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

8 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8 32 39 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-17 • AC Loading

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.10.750.750.75 20

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

20 pF

HSTL

Class I

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-53

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-83 • HSTL Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 2.74 0.19 1.77 0.67 2.79 2.73 6.42 6.36 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-84 • HSTL Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 3.10 0.26 1.94 1.10 3.12 3.10 8.93 8.91 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-54 Advance v0.3

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-85 • Minimum and Maximum DC Input and Output Levels

HSTL Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

15 mA3 –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15 66 55 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-18 • AC Loading

Table 2-86 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.10.750.750.75 20

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

20 pF

HSTL

Class II

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-55

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-87 • HSTL Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 2.62 0.19 1.77 0.67 2.66 2.40 6.29 6.03 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-88 • HSTL Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.93 0.26 1.94 1.10 2.98 2.75 8.79 8.55 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-56 Advance v0.3

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-89 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 83 87 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-19 • AC Loading

Table 2-90 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.21.251.251.25 30

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

30 pF

SSTL2

Class I

VTT

IGLOOe DC and Switching Characteristics

Advance v0.3 2-57

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-91 • SSTL 2 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.91 0.19 1.15 0.67 1.94 1.72 5.57 5.35 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-92 • SSTL 2 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.17 0.26 1.39 1.10 2.21 2.04 8.02 7.84 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-58 Advance v0.3

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-93 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

18 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 169 124 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-20 • AC Loading

Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.21.251.251.25 30

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

30 pF

SSTL2

Class II

VTT

Table 2-95 • SSTL 2 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.94 0.19 1.15 0.67 1.97 1.66 5.60 5.29 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-96 • SSTL 2 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.20 0.26 1.39 1.10 2.24 1.97 8.05 7.78 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-59

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-97 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-21 • AC Loading

Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

30 pF

SSTL3

Class I

VTT

IGLOOe DC and Switching Characteristics

2-60 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-99 • SSTL 3 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 2.05 0.19 1.09 0.67 2.09 1.71 5.72 5.34 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-100 • SSTL 3 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.32 0.26 1.32 1.10 2.37 2.02 8.17 7.83 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-61

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-101 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

21 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI - 0.9 21 21 103 109 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-22 • AC Loading

Table 2-102 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

Note: Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Test Point

30 pF

SSTL3

Class II

VTT

IGLOOe DC and Switching Characteristics

2-62 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-103 • SSTL 3 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.98 1.86 0.19 1.09 0.67 1.89 1.58 5.52 5.21 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-104 • SSTL 3 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 1.55 2.12 0.26 1.32 1.10 2.16 1.89 7.97 7.70 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-63

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by the Actel Designer software

when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation

140 Ω100 Ω

Z0 = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

IGLOOe DC and Switching Characteristics

2-64 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-105 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 2.375 2.5 2.625 V

VOL Output LOW Voltage 0.9 1.075 1.25 V

VOH Output HIGH Voltage 1.25 1.425 1.6 V

IOL 4Output Lower Current 0.65 0.91 1.16 mA

IOH 4Output HIGH Current 0.65 0.91 1.16 mA

VIInput Voltage 0 2.925 V

IIH 3Input HIGH Leakage Current 10 µA

IIL 3Input LOW Leakage Current 10 µA

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common-Mode Voltage 1.125 1.25 1.375 V

VICM Input Common-Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 100 350 mV

Notes:

1. ± 5%

2. Differential input voltage = ±350 mV

3. Currents are measured at 85°C junction temperature.

4. IOL/IOH is defined by VODIFF/(resistor network).

Table 2-106 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.075 1.325 Cross point –

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Table 2-107 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.98 1.77 0.19 1.62 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-108 • LVDS – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

Std. 1.55 2.19 0.26 1.88 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-65

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output

buffer delays are available in the LVDS section in Table 2-107 on page 2-64 and Table 2-108 on

page 2-64.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

RS=60Ω and RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

-T

-R

-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

RSRSRSRSRSRSRSRS

RSRS

Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation

187 W 100 Ω

= 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

IGLOOe DC and Switching Characteristics

2-66 Advance v0.3

Timing Characteristics

1.5 V DC Core Voltage

1.2 V DC Core Voltage

Table 2-109 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 2-110 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.64 1.94 Cross point –

*Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.

Table 2-111 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.98 1.75 0.19 1.45 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-112 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY Units

Std. 1.55 2.16 0.26 1.70 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-67

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

IGLOOe DC and Switching Characteristics

2-68 Advance v0.3

Table 2-113 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-26 on page 2-67 for more information.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-69

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

IGLOOe DC and Switching Characteristics

2-70 Advance v0.3

Table 2-114 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-27 on page 2-69 for more information.

IGLOOe DC and Switching Characteristics

Advance v0.3 2-71

Input Register

Timing Characteristics

1.5 V DC Core Voltage

Figure 2-28 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50% 50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-115 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.42 ns

tISUD Data Setup Time for the Input Data Register 0.47 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.67 ns

tIHE Enable Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.79 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.79 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOOe DC and Switching Characteristics

2-72 Advance v0.3

1.2 V DC Core Voltage

Table 2-116 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.68 ns

tISUD Data Setup Time for the Input Data Register 0.97 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tISUE Enable Setup Time for the Input Data Register 1.02 ns

tIHE Enable Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 1.19 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 1.19 ns